[RISCV] Support shift/rotate amount operands in isAllUsesReadW.

[craig.topper]

Summary

These operands use 6 bits.

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
         Worklist.push_back(UserMI);
         break;
       case RISCV::ORI:
         if (!isUInt<11>(UserMI->getOperand(2).getImm()))
           break;
         Worklist.push_back(UserMI);
         break;
 
+      case RISCV::SLL:
+        // Operand 2 is the shift amount which uses 6 bits.
+        if (OpIdx == 2)
+          break;
+        Worklist.push_back(UserMI);
+        break;
+
+      case RISCV::SRA:
+      case RISCV::SRL:
+      case RISCV::ROL:
+      case RISCV::ROR:
+        // Operand 2 is the shift amount which uses 6 bits.
+        if (OpIdx == 2)
+          break;
+        return false;
+
       case RISCV::ADD_UW:
       case RISCV::SH1ADD_UW:
       case RISCV::SH2ADD_UW:
       case RISCV::SH3ADD_UW:
         // Operand 1 is implicitly zero extended.
         if (OpIdx == 1)
           break;
         Worklist.push_back(UserMI);
for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
       case RISCV::COPY:
       case RISCV::PHI:
 
       case RISCV::ADD:
       case RISCV::ADDI:
       case RISCV::AND:
       case RISCV::MUL:
       case RISCV::OR:
-      case RISCV::SLL:
       case RISCV::SUB:
       case RISCV::XOR:
       case RISCV::XORI:
 
       case RISCV::ANDN:
       case RISCV::CLMUL:
       case RISCV::ORC_B:
       case RISCV::ORN: