[RISCV] Improve support for ADD_UW/SHXADD_UW in isAllUsesReadW.

[craig.topper]

Summary

The first use operand of these is implicitly zero extended. We
can consider that a W read. If the use is the other operand, we
need to look through the instruction.

[asb]

LGTM.

llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp

for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
         Worklist.push_back(UserMI);
         break;
       case RISCV::ORI:
         if (!isUInt<11>(UserMI->getOperand(2).getImm()))
           break;
         Worklist.push_back(UserMI);
         break;
 
+      case RISCV::ADD_UW:
+      case RISCV::SH1ADD_UW:
+      case RISCV::SH2ADD_UW:
+      case RISCV::SH3ADD_UW:
+        // Operand 1 is implicitly zero extended.
+        if (OpIdx == 1)
+          break;
+        Worklist.push_back(UserMI);
+        break;
+
       case RISCV::BEXTI:
         if (UserMI->getOperand(2).getImm() >= 32)
           return false;
         break;
 
       case RISCV::SB:
       case RISCV::SH:
       case RISCV::SW:
for (auto &UserOp : MRI.use_operands(MI->getOperand(0).getReg())) {
       case RISCV::AND:
       case RISCV::MUL:
       case RISCV::OR:
       case RISCV::SLL:
       case RISCV::SUB:
       case RISCV::XOR:
       case RISCV::XORI:
 
-      case RISCV::ADD_UW:
       case RISCV::ANDN:
       case RISCV::CLMUL:
       case RISCV::ORC_B:
       case RISCV::ORN:
       case RISCV::SH1ADD:
-      case RISCV::SH1ADD_UW:
       case RISCV::SH2ADD:
-      case RISCV::SH2ADD_UW:
       case RISCV::SH3ADD:
-      case RISCV::SH3ADD_UW:
       case RISCV::XNOR:
         Worklist.push_back(UserMI);
         break;
       }
     }
   }
 
   return true;