[RISCV][CodeGen] Account for LMUL for Vector Fixed-Point Arithmetic Instructions

[michaelmaitland]

Summary

It is likley that subtargets act differently for vector fixed-point arithmetic instructions based on the LMUL. This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.

[michaelmaitland]

Fixed formatting

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

def V  : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
                   ReadVIDivV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
            Sched<[WriteVIDivX_UpperBound, ReadVIDivV_UpperBound,
                   ReadVIDivX_UpperBound, ReadVMask]>;
 }
 
 multiclass VSALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
+           Sched<[WriteVSALUV_UpperBound, ReadVSALUV_UpperBound,
+                  ReadVSALUV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
+           Sched<[WriteVSALUX_UpperBound, ReadVSALUV_UpperBound,
+                  ReadVSALUX_UpperBound, ReadVMask]>;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
-           Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>;
+           Sched<[WriteVSALUI_UpperBound, ReadVSALUV_UpperBound,
+                  ReadVMask]>;
 }
 
 multiclass VSALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
+           Sched<[WriteVSALUV_UpperBound, ReadVSALUV_UpperBound,
+                  ReadVSALUV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
+           Sched<[WriteVSALUX_UpperBound, ReadVSALUV_UpperBound,
+                  ReadVSALUX_UpperBound, ReadVMask]>;
 }
 
 multiclass VAALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V  : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>;
+           Sched<[WriteVAALUV_UpperBound, ReadVAALUV_UpperBound,
+                  ReadVAALUV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>;
+           Sched<[WriteVAALUX_UpperBound, ReadVAALUV_UpperBound,
+                  ReadVAALUX_UpperBound, ReadVMask]>;
 }
 
 multiclass VSMUL_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>;
+           Sched<[WriteVSMulV_UpperBound, ReadVSMulV_UpperBound,
+                  ReadVSMulV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>;
+           Sched<[WriteVSMulX_UpperBound, ReadVSMulV_UpperBound,
+                  ReadVSMulX_UpperBound, ReadVMask]>;
 }
 
 multiclass VSSHF_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>;
+           Sched<[WriteVSShiftV_UpperBound, ReadVSShiftV_UpperBound,
+                  ReadVSShiftV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>;
+           Sched<[WriteVSShiftX_UpperBound, ReadVSShiftV_UpperBound,
+                  ReadVSShiftX_UpperBound, ReadVMask]>;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
-           Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>;
+           Sched<[WriteVSShiftI_UpperBound, ReadVSShiftV_UpperBound,
+                  ReadVMask]>;
 }
 
 multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">,
-           Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>;
+           Sched<[WriteVNClipV_UpperBound, ReadVNClipV_UpperBound,
+                  ReadVNClipV_UpperBound, ReadVMask]>;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
-           Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>;
+           Sched<[WriteVNClipX_UpperBound, ReadVNClipV_UpperBound,
+                  ReadVNClipX_UpperBound, ReadVMask]>;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
-           Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>;
+           Sched<[WriteVNClipI_UpperBound, ReadVNClipV_UpperBound,
+                  ReadVMask]>;
 }
 
 multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">,
            Sched<[WriteVISlideX, ReadVISlideV, ReadVISlideX, ReadVMask]>;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>,
            Sched<[WriteVISlideI, ReadVISlideV, ReadVMask]>;
 }

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

defm "" : VPseudoBinaryV_VV<Constraint>,
             Sched<[WriteVGatherV, ReadVGatherV, ReadVGatherV, ReadVMask]>;
   defm "" : VPseudoBinaryV_VX<Constraint>,
             Sched<[WriteVGatherX, ReadVGatherV, ReadVGatherX, ReadVMask]>;
   defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
             Sched<[WriteVGatherI, ReadVGatherV, ReadVMask]>;
 }
 
 multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
-  defm "" : VPseudoBinaryV_VV<Constraint>,
-            Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VX<Constraint>,
-            Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
-            Sched<[WriteVSALUI, ReadVSALUV, ReadVMask]>;
+  foreach m = MxList in {
+    defvar mx = m.MX;
+    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
+    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
+    defvar WriteVSALUI_MX = !cast<SchedWrite>("WriteVSALUI_" # mx);
+    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
+    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+
+    defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+              Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
+  }
 }
 
 
 multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVShiftV_MX = !cast<SchedWrite>("WriteVShiftV_" # mx);
     defvar WriteVShiftX_MX = !cast<SchedWrite>("WriteVShiftX_" # mx);
     defvar WriteVShiftI_MX = !cast<SchedWrite>("WriteVShiftI_" # mx);
     defvar ReadVShiftV_MX = !cast<SchedRead>("ReadVShiftV_" # mx);
     defvar ReadVShiftX_MX = !cast<SchedRead>("ReadVShiftX_" # mx);
 
     defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
               Sched<[WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
               Sched<[WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
               Sched<[WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoVSSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
-  defm "" : VPseudoBinaryV_VV<Constraint>,
-            Sched<[WriteVSShiftV, ReadVSShiftV, ReadVSShiftV, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VX<Constraint>,
-            Sched<[WriteVSShiftX, ReadVSShiftV, ReadVSShiftX, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
-            Sched<[WriteVSShiftI, ReadVSShiftV, ReadVMask]>;
+  foreach m = MxList in {
+    defvar mx = m.MX;
+    defvar WriteVSShiftV_MX = !cast<SchedWrite>("WriteVSShiftV_" # mx);
+    defvar WriteVSShiftX_MX = !cast<SchedWrite>("WriteVSShiftX_" # mx);
+    defvar WriteVSShiftI_MX = !cast<SchedWrite>("WriteVSShiftI_" # mx);
+    defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
+    defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
+
+    defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+              Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+              Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+              Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
+  }
 }
 
 multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVIALUV_MX = !cast<SchedWrite>("WriteVIALUV_" # mx);
     defvar WriteVIALUX_MX = !cast<SchedWrite>("WriteVIALUX_" # mx);
     defvar WriteVIALUI_MX = !cast<SchedWrite>("WriteVIALUI_" # mx);
     defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
     defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
 
     defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
             Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
             Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
     defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
             Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
   }
 }
 
 multiclass VPseudoVSALU_VV_VX {
-  defm "" : VPseudoBinaryV_VV,
-            Sched<[WriteVSALUV, ReadVSALUV, ReadVSALUV, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VX,
-            Sched<[WriteVSALUX, ReadVSALUV, ReadVSALUX, ReadVMask]>;
+  foreach m = MxList in {
+    defvar mx = m.MX;
+    defvar WriteVSALUV_MX = !cast<SchedWrite>("WriteVSALUV_" # mx);
+    defvar WriteVSALUX_MX = !cast<SchedWrite>("WriteVSALUX_" # mx);
+    defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
+    defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
+
+    defm "" : VPseudoBinaryV_VV_LMUL<m>,
+              Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VX_LMUL<m>,
+              Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
+  }
 }
 
 multiclass VPseudoVSMUL_VV_VX {
-  defm "" : VPseudoBinaryV_VV,
-            Sched<[WriteVSMulV, ReadVSMulV, ReadVSMulV, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VX,
-            Sched<[WriteVSMulX, ReadVSMulV, ReadVSMulX, ReadVMask]>;
+  foreach m = MxList in {
+    defvar mx = m.MX;
+    defvar WriteVSMulV_MX = !cast<SchedWrite>("WriteVSMulV_" # mx);
+    defvar WriteVSMulX_MX = !cast<SchedWrite>("WriteVSMulX_" # mx);
+    defvar ReadVSMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
+    defvar ReadVSMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
+
+    defm "" : VPseudoBinaryV_VV_LMUL<m>,
+              Sched<[WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VX_LMUL<m>,
+              Sched<[WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX, ReadVMask]>;
+  }
 }
 
 multiclass VPseudoVAALU_VV_VX {
-  defm "" : VPseudoBinaryV_VV,
-            Sched<[WriteVAALUV, ReadVAALUV, ReadVAALUV, ReadVMask]>;
-  defm "" : VPseudoBinaryV_VX,
-            Sched<[WriteVAALUX, ReadVAALUV, ReadVAALUX, ReadVMask]>;
+  foreach m = MxList in {
+    defvar mx = m.MX;
+    defvar WriteVAALUV_MX = !cast<SchedWrite>("WriteVAALUV_" # mx);
+    defvar WriteVAALUX_MX = !cast<SchedWrite>("WriteVAALUX_" # mx);
+    defvar ReadVAALUV_MX = !cast<SchedRead>("ReadVAALUV_" # mx);
+    defvar ReadVAALUX_MX = !cast<SchedRead>("ReadVAALUX_" # mx);
+
+    defm "" : VPseudoBinaryV_VV_LMUL<m>,
+              Sched<[WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_VX_LMUL<m>,
+              Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
+  }
 }
 
 multiclass VPseudoVMINMAX_VV_VX {
   foreach m = MxList in {
     defvar mx = m.MX;
     defvar WriteVICmpV_MX = !cast<SchedWrite>("WriteVICmpV_" # mx);
     defvar WriteVICmpX_MX = !cast<SchedWrite>("WriteVICmpX_" # mx);
     defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
foreach m = MxList in {
     defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
               Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
     defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
               Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
   }
 }
 
 multiclass VPseudoVNCLP_WV_WX_WI {
-  defm "" : VPseudoBinaryV_WV,
-            Sched<[WriteVNClipV, ReadVNClipV, ReadVNClipV, ReadVMask]>;
-  defm "" : VPseudoBinaryV_WX,
-            Sched<[WriteVNClipX, ReadVNClipV, ReadVNClipX, ReadVMask]>;
-  defm "" : VPseudoBinaryV_WI,
-            Sched<[WriteVNClipI, ReadVNClipV, ReadVMask]>;
+  foreach m = MxListW in {
+    defvar mx = m.MX;
+    defvar WriteVNClipV_MX = !cast<SchedWrite>("WriteVNClipV_" # mx);
+    defvar WriteVNClipX_MX = !cast<SchedWrite>("WriteVNClipX_" # mx);
+    defvar WriteVNClipI_MX = !cast<SchedWrite>("WriteVNClipI_" # mx);
+    defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
+    defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
+
+    defm "" : VPseudoBinaryV_WV_LMUL<m>,
+              Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_WX_LMUL<m>,
+              Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
+    defm "" : VPseudoBinaryV_WI_LMUL<m>,
+              Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
+  }
 }
 
 multiclass VPseudoVNSHT_WV_WX_WI {
   foreach m = MxListW in {
     defvar mx = m.MX;
     defvar WriteVNShiftV_MX = !cast<SchedWrite>("WriteVNShiftV_" # mx);
     defvar WriteVNShiftX_MX = !cast<SchedWrite>("WriteVNShiftX_" # mx);
     defvar WriteVNShiftI_MX = !cast<SchedWrite>("WriteVNShiftI_" # mx);

llvm/lib/Target/RISCV/RISCVScheduleV.td

 defm "" : LMULSchedWrites<"WriteVIMergeI">;
 // 11.16. Vector Integer Move Instructions
 defm "" : LMULSchedWrites<"WriteVIMovV">;
 defm "" : LMULSchedWrites<"WriteVIMovX">;
 defm "" : LMULSchedWrites<"WriteVIMovI">;
 
 // 12. Vector Fixed-Point Arithmetic Instructions
 // 12.1. Vector Single-Width Saturating Add and Subtract
-def WriteVSALUV       : SchedWrite;
-def WriteVSALUX       : SchedWrite;
-def WriteVSALUI       : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVSALUV">;
+defm "" : LMULSchedWrites<"WriteVSALUX">;
+defm "" : LMULSchedWrites<"WriteVSALUI">;
 // 12.2. Vector Single-Width Averaging Add and Subtract
-def WriteVAALUV       : SchedWrite;
-def WriteVAALUX       : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVAALUV">;
+defm "" : LMULSchedWrites<"WriteVAALUX">;
 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
-def WriteVSMulV       : SchedWrite;
-def WriteVSMulX       : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVSMulV">;
+defm "" : LMULSchedWrites<"WriteVSMulX">;
 // 12.4. Vector Single-Width Scaling Shift Instructions
-def WriteVSShiftV     : SchedWrite;
-def WriteVSShiftX     : SchedWrite;
-def WriteVSShiftI     : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVSShiftV">;
+defm "" : LMULSchedWrites<"WriteVSShiftX">;
+defm "" : LMULSchedWrites<"WriteVSShiftI">;
 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
-def WriteVNClipV      : SchedWrite;
-def WriteVNClipX      : SchedWrite;
-def WriteVNClipI      : SchedWrite;
+defm "" : LMULSchedWrites<"WriteVNClipV", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVNClipX", SchedMxListW>;
+defm "" : LMULSchedWrites<"WriteVNClipI", SchedMxListW>;
 
 // 13. Vector Floating-Point Instructions
 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
 def WriteVFALUV       : SchedWrite;
 def WriteVFALUF       : SchedWrite;
 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
 def WriteVFWALUV      : SchedWrite;
 def WriteVFWALUF      : SchedWrite;

 defm "" : LMULSchedReads<"ReadVIMergeV">;
 defm "" : LMULSchedReads<"ReadVIMergeX">;
 // 11.16. Vector Integer Move Instructions
 defm "" : LMULSchedReads<"ReadVIMovV">;
 defm "" : LMULSchedReads<"ReadVIMovX">;
 
 // 12. Vector Fixed-Point Arithmetic Instructions
 // 12.1. Vector Single-Width Saturating Add and Subtract
-def ReadVSALUV        : SchedRead;
-def ReadVSALUX        : SchedRead;
+defm "" : LMULSchedReads<"ReadVSALUV">;
+defm "" : LMULSchedReads<"ReadVSALUX">;
 // 12.2. Vector Single-Width Averaging Add and Subtract
-def ReadVAALUV        : SchedRead;
-def ReadVAALUX        : SchedRead;
+defm "" : LMULSchedReads<"ReadVAALUV">;
+defm "" : LMULSchedReads<"ReadVAALUX">;
 // 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
-def ReadVSMulV        : SchedRead;
-def ReadVSMulX        : SchedRead;
+defm "" : LMULSchedReads<"ReadVSMulV">;
+defm "" : LMULSchedReads<"ReadVSMulX">;
 // 12.4. Vector Single-Width Scaling Shift Instructions
-def ReadVSShiftV      : SchedRead;
-def ReadVSShiftX      : SchedRead;
+defm "" : LMULSchedReads<"ReadVSShiftV">;
+defm "" : LMULSchedReads<"ReadVSShiftX">;
 // 12.5. Vector Narrowing Fixed-Point Clip Instructions
-def ReadVNClipV       : SchedRead;
-def ReadVNClipX       : SchedRead;
+defm "" : LMULSchedReads<"ReadVNClipV", SchedMxListW>;
+defm "" : LMULSchedReads<"ReadVNClipX", SchedMxListW>;
 
 // 13. Vector Floating-Point Instructions
 // 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
 def ReadVFALUV        : SchedRead;
 def ReadVFALUF        : SchedRead;
 // 13.3. Vector Widening Floating-Point Add/Subtract Instructions
 def ReadVFWALUV       : SchedRead;
 def ReadVFWALUF       : SchedRead;

 defm "" : LMULWriteRes<"WriteVIMergeV", []>;
 defm "" : LMULWriteRes<"WriteVIMergeX", []>;
 defm "" : LMULWriteRes<"WriteVIMergeI", []>;
 defm "" : LMULWriteRes<"WriteVIMovV", []>;
 defm "" : LMULWriteRes<"WriteVIMovX", []>;
 defm "" : LMULWriteRes<"WriteVIMovI", []>;
 
 // 12. Vector Fixed-Point Arithmetic Instructions
-def : WriteRes<WriteVSALUV, []>;
-def : WriteRes<WriteVSALUX, []>;
-def : WriteRes<WriteVSALUI, []>;
-def : WriteRes<WriteVAALUV, []>;
-def : WriteRes<WriteVAALUX, []>;
-def : WriteRes<WriteVSMulV, []>;
-def : WriteRes<WriteVSMulX, []>;
-def : WriteRes<WriteVSShiftV, []>;
-def : WriteRes<WriteVSShiftX, []>;
-def : WriteRes<WriteVSShiftI, []>;
-def : WriteRes<WriteVNClipV, []>;
-def : WriteRes<WriteVNClipX, []>;
-def : WriteRes<WriteVNClipI, []>;
+defm "" : LMULWriteRes<"WriteVSALUV", []>;
+defm "" : LMULWriteRes<"WriteVSALUX", []>;
+defm "" : LMULWriteRes<"WriteVSALUI", []>;
+defm "" : LMULWriteRes<"WriteVAALUV", []>;
+defm "" : LMULWriteRes<"WriteVAALUX", []>;
+defm "" : LMULWriteRes<"WriteVSMulV", []>;
+defm "" : LMULWriteRes<"WriteVSMulX", []>;
+defm "" : LMULWriteRes<"WriteVSShiftV", []>;
+defm "" : LMULWriteRes<"WriteVSShiftX", []>;
+defm "" : LMULWriteRes<"WriteVSShiftI", []>;
+defm "" : LMULWriteRes<"WriteVNClipV", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVNClipX", [], SchedMxListW>;
+defm "" : LMULWriteRes<"WriteVNClipI", [], SchedMxListW>;
 
 // 13. Vector Floating-Point Instructions
 def : WriteRes<WriteVFALUV, []>;
 def : WriteRes<WriteVFALUF, []>;
 def : WriteRes<WriteVFWALUV, []>;
 def : WriteRes<WriteVFWALUF, []>;
 def : WriteRes<WriteVFMulV, []>;
 def : WriteRes<WriteVFMulF, []>;

 defm "" : LMULReadAdvance<"ReadVIWMulAddV", 0, SchedMxListW>;
 defm "" : LMULReadAdvance<"ReadVIWMulAddX", 0, SchedMxListW>;
 defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;
 defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;
 defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
 defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
 
 // 12. Vector Fixed-Point Arithmetic Instructions
-def : ReadAdvance<ReadVSALUV, 0>;
-def : ReadAdvance<ReadVSALUX, 0>;
-def : ReadAdvance<ReadVAALUV, 0>;
-def : ReadAdvance<ReadVAALUX, 0>;
-def : ReadAdvance<ReadVSMulV, 0>;
-def : ReadAdvance<ReadVSMulX, 0>;
-def : ReadAdvance<ReadVSShiftV, 0>;
-def : ReadAdvance<ReadVSShiftX, 0>;
-def : ReadAdvance<ReadVNClipV, 0>;
-def : ReadAdvance<ReadVNClipX, 0>;
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvance<"ReadVNClipV", 0, SchedMxListW>;
+defm "" : LMULReadAdvance<"ReadVNClipX", 0, SchedMxListW>;
 
 // 13. Vector Floating-Point Instructions
 def : ReadAdvance<ReadVFALUV, 0>;
 def : ReadAdvance<ReadVFALUF, 0>;
 def : ReadAdvance<ReadVFWALUV, 0>;
 def : ReadAdvance<ReadVFWALUF, 0>;
 def : ReadAdvance<ReadVFMulV, 0>;
 def : ReadAdvance<ReadVFMulF, 0>;