[AArch64][SVE2] Add the SVE2.1 bfmlslb and bfmlslt instructions

[david-arm]

Summary

This patch adds the assembly/disassembly for the following instructions:

BFMLSLB : BFloat16 floating-point multiply-subtract long

from single-precision (bottom)

BFMLSLT : BFloat16 floating-point multiply-subtract long

from single-precision (top)

Both the vector and indexed forms are added for each.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[c-rhodes]

Just one nit but otherwise LGTM

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

2123

I know it's not introduced by your patch but this should be ZZZI as well, same for next instruction.

[david-arm]

• As a result of changing the instruction name from BFMLALB_ZZI to BFMLALB_ZZZI I started to see failures building AArch64SchedNeoverse.td. I have no idea why this happens, but the solution is the same as elsewhere, i.e. to add SVEUnsupported.F to the list of unsupported features.
• As a result of a comment on a previous patch in this chain I have moved the tests into llvm/test/MC/AArch64/SVE2p1 and removed the sme2_or_sve2p1 part from the names.

[c-rhodes]

llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

2051

I suspect the reason the scheduler model failed to compile is this regex no longer matches and the model is marked as complete? The regex should now be ^BFMLAL[BT]_ZZZI?$, although I don't really get how what you did fixed this.

[david-arm]

• Used @c-rhodes's suggestion about how to fix the neoverse sched file.
• Added _S suffix to SVE2p1 instructions.

[david-arm]

llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

2051

Good shout! I've fixed the regex instead.

llvm/lib/Target/AArch64/AArch64.td

 //===----------------------------------------------------------------------===//
 // Unsupported features to disable for scheduling models
 //===----------------------------------------------------------------------===//
 
 class AArch64Unsupported { list<Predicate> F; }
 
 def SVEUnsupported : AArch64Unsupported {
   let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
-           HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME];
+           HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME, HasSVE2p1_or_HasSME2];
 }
 
 def PAUnsupported : AArch64Unsupported {
   let F = [HasPAuth];
 }
 
 def SMEUnsupported : AArch64Unsupported {
   let F = [HasSME, HasSMEF64F64, HasSMEI16I64, HasSME2, HasSVE2p1_or_HasSME2];

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasBF16, HasSVEorSME] in {
   defm BFDOT_ZZI    : sve_bfloat_dot_indexed<"bfdot", int_aarch64_sve_bfdot_lane>;
 } // End HasBF16, HasSVEorSME
 
 let Predicates = [HasBF16, HasSVE] in {
   defm BFMMLA_ZZZ   : sve_bfloat_matmul<"bfmmla", int_aarch64_sve_bfmmla>;
 } // End HasBF16, HasSVE
 
 let Predicates = [HasBF16, HasSVEorSME] in {
-  defm BFMLALB_ZZZ : sve_bfloat_matmul_longvecl<0b0, "bfmlalb", int_aarch64_sve_bfmlalb>;
-  defm BFMLALT_ZZZ : sve_bfloat_matmul_longvecl<0b1, "bfmlalt", int_aarch64_sve_bfmlalt>;
-  defm BFMLALB_ZZI : sve_bfloat_matmul_longvecl_idx<0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>;
-  defm BFMLALT_ZZI : sve_bfloat_matmul_longvecl_idx<0b1, "bfmlalt", int_aarch64_sve_bfmlalt_lane>;
+  defm BFMLALB_ZZZ : sve_bfloat_matmul_longvecl<0b0, 0b0, "bfmlalb", int_aarch64_sve_bfmlalb>;
+  defm BFMLALT_ZZZ : sve_bfloat_matmul_longvecl<0b1, 0b0, "bfmlalt", int_aarch64_sve_bfmlalt>;
+  defm BFMLALB_ZZZI : sve_bfloat_matmul_longvecl_idx<0b0, 0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>;
+  defm BFMLALT_ZZZI : sve_bfloat_matmul_longvecl_idx<0b1, 0b0, "bfmlalt", int_aarch64_sve_bfmlalt_lane>;
   defm BFCVT_ZPmZ   : sve_bfloat_convert<0b1, "bfcvt",   int_aarch64_sve_fcvt_bf16f32>;
   defm BFCVTNT_ZPmZ : sve_bfloat_convert<0b0, "bfcvtnt", int_aarch64_sve_fcvtnt_bf16f32>;
 } // End HasBF16, HasSVEorSME
 
 let Predicates = [HasSVEorSME] in {
   // InstAliases
   def : InstAlias<"mov $Zd, $Zn",
                   (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;

 //===----------------------------------------------------------------------===//
 // SME2 or SVE2.1 instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasSVE2p1_or_HasSME2] in {
 defm FCLAMP_ZZZ : sve2p1_fclamp<"fclamp">;
 def FDOT_ZZZ    : sve_float_dot<0b0, "fdot">;
 def FDOT_ZZZI   : sve_float_dot_indexed<0b0, "fdot">;
+def BFMLSLB_ZZZ : sve_bfloat_matmul_longvecl<0b0, 0b1, "bfmlslb">;
+def BFMLSLT_ZZZ : sve_bfloat_matmul_longvecl<0b1, 0b1, "bfmlslt">;
+def BFMLSLB_ZZZI : sve_bfloat_matmul_longvecl_idx<0b0, 0b1, "bfmlslb">;
+def BFMLSLT_ZZZI : sve_bfloat_matmul_longvecl_idx<0b1, 0b1, "bfmlslt">;
 } // End HasSVE2p1_or_HasSME2

llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td

 def NeoverseN2Model : SchedMachineModel {
   let IssueWidth            =  10; // Micro-ops dispatched at a time.
   let MicroOpBufferSize     = 160; // Entries in micro-op re-order buffer.
   let LoadLatency           =   4; // Optimistic load latency.
   let MispredictPenalty     =  10; // Extra cycles for mispredicted branch.
   let LoopMicroOpBufferSize =  16; // NOTE: Copied from Cortex-A57.
   let CompleteModel         =   1;
 
-  list<Predicate> UnsupportedFeatures = SMEUnsupported.F;
+  list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+                                                    SMEUnsupported.F);
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available on Neoverse N2.
 // Instructions are first fetched and then decoded into internal macro-ops
 // (MOPs). From there, the MOPs proceed through register renaming and dispatch
 // stages. A MOP can be split into two micro-ops further down the pipeline
 // after the decode stage. Once dispatched, micro-ops wait for their operands

 
 // Dot product
 def : InstRW<[N2Write_4cyc_1V], (instrs BFDOT_ZZI, BFDOT_ZZZ)>;
 
 // Matrix multiply accumulate
 def : InstRW<[N2Write_5cyc_1V], (instrs BFMMLA_ZZZ)>;
 
 // Multiply accumulate long
 def : InstRW<[N2Write_4cyc_1V], (instregex "^BFMLAL[BT]_ZZ[ZI]$")>;
 
 // SVE Load instructions
 // -----------------------------------------------------------------------------
 
 // Load vector
 def : InstRW<[N2Write_6cyc_1L], (instrs LDR_ZXI)>;
 
 // Load predicate

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
   let ElementSize = ElementSizeH;
 }
 
 multiclass sve_bfloat_matmul<string asm, SDPatternOperator op> {
   def NAME : sve_bfloat_matmul<asm>;
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv8bf16, nxv8bf16 ,!cast<Instruction>(NAME)>;
 }
 
-class sve_bfloat_matmul_longvecl<bit BT, string asm>
+class sve_bfloat_matmul_longvecl<bit BT, bit sub, string asm>
 : sve_bfloat_matmul<asm> {
   let Inst{23}    = 0b1;
-  let Inst{14-13} = 0b00;
+  let Inst{14}    = 0b0;
+  let Inst{13}    = sub;
   let Inst{10}    = BT;
 }
 
-multiclass sve_bfloat_matmul_longvecl<bit BT, string asm, SDPatternOperator op> {
-  def NAME : sve_bfloat_matmul_longvecl<BT, asm>;
+multiclass sve_bfloat_matmul_longvecl<bit BT, bit sub, string asm, SDPatternOperator op> {
+  def NAME : sve_bfloat_matmul_longvecl<BT, sub, asm>;
   def : SVE_3_Op_Pat<nxv4f32, op, nxv4f32, nxv8bf16, nxv8bf16 ,!cast<Instruction>(NAME)>;
 }
 
-class sve_bfloat_matmul_longvecl_idx<bit BT, string asm>
+class sve_bfloat_matmul_longvecl_idx<bit BT, bit sub, string asm>
 : sve_bfloat_dot_base<0b01, asm, "\t$Zda, $Zn, $Zm$iop",
   (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexH:$iop)> {
   bits<3> iop;
   bits<3> Zm;
   let Inst{23}    = 0b1;
   let Inst{20-19} = iop{2-1};
   let Inst{18-16} = Zm;
+  let Inst{13}    = sub;
   let Inst{11}    = iop{0};
   let Inst{10}    = BT;
 }
 
-multiclass sve_bfloat_matmul_longvecl_idx<bit BT, string asm, SDPatternOperator op> {
-  def NAME : sve_bfloat_matmul_longvecl_idx<BT, asm>;
+multiclass sve_bfloat_matmul_longvecl_idx<bit BT, bit sub, string asm, SDPatternOperator op> {
+  def NAME : sve_bfloat_matmul_longvecl_idx<BT, sub, asm>;
   def : SVE_4_Op_Imm_Pat<nxv4f32, op, nxv4f32, nxv8bf16, nxv8bf16, i64, VectorIndexH_timm, !cast<Instruction>(NAME)>;
 }
 
 class sve_bfloat_convert<bit N, string asm>
 : I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> {
   bits<5> Zd;
   bits<3> Pg;

llvm/test/MC/AArch64/SVE2p1/bfmlslb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfmlslb z0.s, z0.h, z0.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlslb z0.s, z0.h, z0.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslb z0.s, z0.h, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlslb z0.s, z0.h, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslb z0.s, z0.h, z8.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmlslb z0.s, z0.h, z8.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmlslb z0.s, z0.s, z0.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmlslb z0.s, z0.s, z0.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslb z23.d, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmlslb z23.d, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslb z23.d, z23.h, z13.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmlslb z23.d, z23.h, z13.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/bfmlslb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+movprfx z23, z31
+bfmlslb z23.s, z13.h, z8.h  // 01100100-11101000-10100001-10110111
+// CHECK-INST:  movprfx z23, z31
+// CHECK-INST: bfmlslb z23.s, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xa1,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e8a1b7 <unknown>
+
+bfmlslb z0.s, z0.h, z0.h  // 01100100-11100000-10100000-00000000
+// CHECK-INST: bfmlslb z0.s, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xa0,0xe0,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e0a000 <unknown>
+
+bfmlslb z21.s, z10.h, z21.h  // 01100100-11110101-10100001-01010101
+// CHECK-INST: bfmlslb z21.s, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xa1,0xf5,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64f5a155 <unknown>
+
+bfmlslb z23.s, z13.h, z8.h  // 01100100-11101000-10100001-10110111
+// CHECK-INST: bfmlslb z23.s, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xa1,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e8a1b7 <unknown>
+
+bfmlslb z31.s, z31.h, z31.h  // 01100100-11111111-10100011-11111111
+// CHECK-INST: bfmlslb z31.s, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xa3,0xff,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64ffa3ff <unknown>
+
+movprfx z23, z31
+bfmlslb z23.s, z13.h, z0.h[3]  // 01100100-11101000-01101001-10110111
+// CHECK-INST:  movprfx z23, z31
+// CHECK-INST: bfmlslb z23.s, z13.h, z0.h[3]
+// CHECK-ENCODING: [0xb7,0x69,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e869b7 <unknown>
+
+bfmlslb z0.s, z0.h, z0.h[0]  // 01100100-11100000-01100000-00000000
+// CHECK-INST: bfmlslb z0.s, z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x60,0xe0,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e06000 <unknown>
+
+bfmlslb z21.s, z10.h, z5.h[4]  // 01100100-11110101-01100001-01010101
+// CHECK-INST: bfmlslb z21.s, z10.h, z5.h[4]
+// CHECK-ENCODING: [0x55,0x61,0xf5,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64f56155 <unknown>
+
+bfmlslb z23.s, z13.h, z0.h[3]  // 01100100-11101000-01101001-10110111
+// CHECK-INST: bfmlslb z23.s, z13.h, z0.h[3]
+// CHECK-ENCODING: [0xb7,0x69,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e869b7 <unknown>
+
+bfmlslb z31.s, z31.h, z7.h[7]  // 01100100-11111111-01101011-11111111
+// CHECK-INST: bfmlslb z31.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xff,0x6b,0xff,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64ff6bff <unknown>

llvm/test/MC/AArch64/SVE2p1/bfmlslt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector lane index
+
+bfmlslt z0.s, z0.h, z0.h[8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslt z0.s, z0.h, z0.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
+// CHECK-NEXT: bfmlslt z0.s, z0.h, z0.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslt z0.s, z0.h, z8.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: bfmlslt z0.s, z0.h, z8.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid vector suffix
+
+bfmlslt z0.s, z0.s, z0.s[0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmlslt z0.s, z0.s, z0.s[0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslt z23.d, z23.h, z13.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bfmlslt z23.d, z23.h, z13.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bfmlslt z23.d, z23.h, z13.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/bfmlslt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+movprfx z23, z31
+bfmlslt z23.s, z13.h, z8.h  // 01100100-11101000-10100101-10110111
+// CHECK-INST:  movprfx z23, z31
+// CHECK-INST: bfmlslt z23.s, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xa5,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e8a5b7 <unknown>
+
+bfmlslt z0.s, z0.h, z0.h  // 01100100-11100000-10100100-00000000
+// CHECK-INST: bfmlslt z0.s, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xa4,0xe0,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e0a400 <unknown>
+
+bfmlslt z21.s, z10.h, z21.h  // 01100100-11110101-10100101-01010101
+// CHECK-INST: bfmlslt z21.s, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xa5,0xf5,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64f5a555 <unknown>
+
+bfmlslt z23.s, z13.h, z8.h  // 01100100-11101000-10100101-10110111
+// CHECK-INST: bfmlslt z23.s, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xa5,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e8a5b7 <unknown>
+
+bfmlslt z31.s, z31.h, z31.h  // 01100100-11111111-10100111-11111111
+// CHECK-INST: bfmlslt z31.s, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xa7,0xff,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64ffa7ff <unknown>
+
+movprfx z23, z31
+bfmlslt z23.s, z13.h, z0.h[3]  // 01100100-11101000-01101101-10110111
+// CHECK-INST:  movprfx z23, z31
+// CHECK-INST: bfmlslt z23.s, z13.h, z0.h[3]
+// CHECK-ENCODING: [0xb7,0x6d,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e86db7 <unknown>
+
+bfmlslt z0.s, z0.h, z0.h[0]  // 01100100-11100000-01100100-00000000
+// CHECK-INST: bfmlslt z0.s, z0.h, z0.h[0]
+// CHECK-ENCODING: [0x00,0x64,0xe0,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e06400 <unknown>
+
+bfmlslt z21.s, z10.h, z5.h[4]  // 01100100-11110101-01100101-01010101
+// CHECK-INST: bfmlslt z21.s, z10.h, z5.h[4]
+// CHECK-ENCODING: [0x55,0x65,0xf5,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64f56555 <unknown>
+
+bfmlslt z23.s, z13.h, z0.h[3]  // 01100100-11101000-01101101-10110111
+// CHECK-INST: bfmlslt z23.s, z13.h, z0.h[3]
+// CHECK-ENCODING: [0xb7,0x6d,0xe8,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64e86db7 <unknown>
+
+bfmlslt z31.s, z31.h, z7.h[7]  // 01100100-11111111-01101111-11111111
+// CHECK-INST: bfmlslt z31.s, z31.h, z7.h[7]
+// CHECK-ENCODING: [0xff,0x6f,0xff,0x64]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: 64ff6fff <unknown>