This is an archive of the discontinued LLVM Phabricator instance.

Differential D136366

[PowerPC] Add new DMR register classes to Future CPU.
ClosedPublic

Authored by stefanp on Oct 20 2022, 9:12 AM.

Details

Reviewers
lei
amyk
nemanjai
saghir
Group Reviewers
Restricted Project
Commits
rG9df924a634ac: [PowerPC] Add new DMR register classes to Future CPU.
Summary

A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.

This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.

Diff Detail

Event Timeline

stefanp created this revision.Oct 20 2022, 9:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2022, 9:12 AM
Herald added subscribers: shchenz, kbarton, hiraditya, dschuff. · View Herald Transcript
stefanp requested review of this revision.Oct 20 2022, 9:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 20 2022, 9:12 AM
Herald added subscribers: jdoerfert, aheejin. · View Herald Transcript
stefanp added a reviewer: Restricted Project.Oct 20 2022, 9:12 AM
stefanp updated this revision to Diff 469255.Oct 20 2022, 9:18 AM

nit: Fixed some spacing.

Harbormaster completed remote builds in B193255: Diff 469255.Oct 20 2022, 10:21 AM
amyk accepted this revision as: amyk.Oct 24 2022, 4:06 PM

I have a couple minor nit comments but I think it overall LGTM.

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
367

Unrelated space change?

llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
38

nit: Align spacing.

llvm/test/CodeGen/PowerPC/future-check-features.ll
1

nit: Are these run lines too long?

This revision is now accepted and ready to land.Oct 24 2022, 4:06 PM
stefanp updated this revision to Diff 471261.Oct 27 2022, 12:32 PM

Rebased patch to top of main and addressed a couple of nits.

llvm/test/CodeGen/PowerPC/future-check-features.ll
1

nit: Are these run lines too long?

Yes, they are too long.
I actually think they were too long in the original test too but I'll fix it with this patch.

Harbormaster completed remote builds in B194733: Diff 471261.Oct 27 2022, 2:34 PM
saghir accepted this revision as: saghir.Oct 28 2022, 4:09 PM
saghir added a subscriber: saghir.

LGTM. Thanks!

stefanp updated this revision to Diff 472744.Nov 2 2022, 1:36 PM

Rebased patch to top of main branch.

Harbormaster completed remote builds in B195792: Diff 472744.Nov 2 2022, 3:13 PM
stefanp updated this revision to Diff 472824.Nov 2 2022, 6:32 PM

Moved the include location for PPCInstrFutureMMA.td.

Harbormaster completed remote builds in B195852: Diff 472824.Nov 2 2022, 7:20 PM
This revision was landed with ongoing or failed builds.Nov 3 2022, 6:29 AM
Closed by commit rG9df924a634ac: [PowerPC] Add new DMR register classes to Future CPU. (authored by stefanp). · Explain Why
This revision was automatically updated to reflect the committed changes.
stefanp added a commit: rG9df924a634ac: [PowerPC] Add new DMR register classes to Future CPU..
stefanp mentioned this in D136992: [PowerPC] Add new load/store with length instructions to Future CPU..Nov 3 2022, 12:32 PM

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
361 lines
IR/
1 line
Support/
360 lines
lib/
CodeGen/
2 lines
Target/
PowerPC/
AsmParser/
86 lines
Disassembler/
42 lines
MCTargetDesc/
31 lines
15 lines
116 lines
1 line
27 lines
46 lines
164 lines
9 lines
test/
CodeGen/
PowerPC/
10 lines
MC/
Disassembler/
PowerPC/
41 lines
35 lines
PowerPC/
50 lines
utils/
TableGen/
1 line

Diff 469253

llvm/include/llvm/CodeGen/ValueTypes.td

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
def v8i1 : ValueType<8, 20>; // 8 x i1 vector value def v8i1 : ValueType<8, 20>; // 8 x i1 vector value
def v16i1 : ValueType<16, 21>; // 16 x i1 vector value def v16i1 : ValueType<16, 21>; // 16 x i1 vector value
def v32i1 : ValueType<32, 22>; // 32 x i1 vector value def v32i1 : ValueType<32, 22>; // 32 x i1 vector value
def v64i1 : ValueType<64, 23>; // 64 x i1 vector value def v64i1 : ValueType<64, 23>; // 64 x i1 vector value
def v128i1 : ValueType<128, 24>; // 128 x i1 vector value def v128i1 : ValueType<128, 24>; // 128 x i1 vector value
def v256i1 : ValueType<256, 25>; // 256 x i1 vector value def v256i1 : ValueType<256, 25>; // 256 x i1 vector value
def v512i1 : ValueType<512, 26>; // 512 x i1 vector value def v512i1 : ValueType<512, 26>; // 512 x i1 vector value
def v1024i1 : ValueType<1024, 27>; // 1024 x i1 vector value def v1024i1 : ValueType<1024, 27>; // 1024 x i1 vector value
def v2048i1 : ValueType<2048, 28>; // 2048 x i1 vector value
def v128i2 : ValueType<256, 28>; // 128 x i2 vector value def v128i2 : ValueType<256, 29>; // 128 x i2 vector value
def v256i2 : ValueType<512, 29>; // 256 x i2 vector value def v256i2 : ValueType<512, 30>; // 256 x i2 vector value
def v64i4 : ValueType<256, 30>; // 64 x i4 vector value def v64i4 : ValueType<256, 31>; // 64 x i4 vector value
def v128i4 : ValueType<512, 31>; // 128 x i4 vector value def v128i4 : ValueType<512, 32>; // 128 x i4 vector value
def v1i8 : ValueType<8, 32>; // 1 x i8 vector value def v1i8 : ValueType<8, 33>; // 1 x i8 vector value
def v2i8 : ValueType<16, 33>; // 2 x i8 vector value def v2i8 : ValueType<16, 34>; // 2 x i8 vector value
def v4i8 : ValueType<32, 34>; // 4 x i8 vector value def v4i8 : ValueType<32, 35>; // 4 x i8 vector value
def v8i8 : ValueType<64, 35>; // 8 x i8 vector value def v8i8 : ValueType<64, 36>; // 8 x i8 vector value
def v16i8 : ValueType<128, 36>; // 16 x i8 vector value def v16i8 : ValueType<128, 37>; // 16 x i8 vector value
def v32i8 : ValueType<256, 37>; // 32 x i8 vector value def v32i8 : ValueType<256, 38>; // 32 x i8 vector value
def v64i8 : ValueType<512, 38>; // 64 x i8 vector value def v64i8 : ValueType<512, 39>; // 64 x i8 vector value
def v128i8 : ValueType<1024, 39>; // 128 x i8 vector value def v128i8 : ValueType<1024, 40>; // 128 x i8 vector value
def v256i8 : ValueType<2048, 40>; // 256 x i8 vector value def v256i8 : ValueType<2048, 41>; // 256 x i8 vector value
def v512i8 : ValueType<4096, 41>; // 512 x i8 vector value def v512i8 : ValueType<4096, 42>; // 512 x i8 vector value
def v1024i8 : ValueType<8192, 42>; // 1024 x i8 vector value def v1024i8 : ValueType<8192, 43>; // 1024 x i8 vector value
def v1i16 : ValueType<16, 43>; // 1 x i16 vector value def v1i16 : ValueType<16, 44>; // 1 x i16 vector value
def v2i16 : ValueType<32, 44>; // 2 x i16 vector value def v2i16 : ValueType<32, 45>; // 2 x i16 vector value
def v3i16 : ValueType<48, 45>; // 3 x i16 vector value def v3i16 : ValueType<48, 46>; // 3 x i16 vector value
def v4i16 : ValueType<64, 46>; // 4 x i16 vector value def v4i16 : ValueType<64, 47>; // 4 x i16 vector value
def v8i16 : ValueType<128, 47>; // 8 x i16 vector value def v8i16 : ValueType<128, 48>; // 8 x i16 vector value
def v16i16 : ValueType<256, 48>; // 16 x i16 vector value def v16i16 : ValueType<256, 49>; // 16 x i16 vector value
def v32i16 : ValueType<512, 49>; // 32 x i16 vector value def v32i16 : ValueType<512, 50>; // 32 x i16 vector value
def v64i16 : ValueType<1024, 50>; // 64 x i16 vector value def v64i16 : ValueType<1024, 51>; // 64 x i16 vector value
def v128i16 : ValueType<2048, 51>; // 128 x i16 vector value def v128i16 : ValueType<2048, 52>; // 128 x i16 vector value
def v256i16 : ValueType<4096, 52>; // 256 x i16 vector value def v256i16 : ValueType<4096, 53>; // 256 x i16 vector value
def v512i16 : ValueType<8192, 53>; // 512 x i16 vector value def v512i16 : ValueType<8192, 54>; // 512 x i16 vector value
def v1i32 : ValueType<32, 54>; // 1 x i32 vector value def v1i32 : ValueType<32, 55>; // 1 x i32 vector value
def v2i32 : ValueType<64, 55>; // 2 x i32 vector value def v2i32 : ValueType<64, 56>; // 2 x i32 vector value
def v3i32 : ValueType<96, 56>; // 3 x i32 vector value def v3i32 : ValueType<96, 57>; // 3 x i32 vector value
def v4i32 : ValueType<128, 57>; // 4 x i32 vector value def v4i32 : ValueType<128, 58>; // 4 x i32 vector value
def v5i32 : ValueType<160, 58>; // 5 x i32 vector value def v5i32 : ValueType<160, 59>; // 5 x i32 vector value
def v6i32 : ValueType<192, 59>; // 6 x f32 vector value def v6i32 : ValueType<192, 60>; // 6 x f32 vector value
def v7i32 : ValueType<224, 60>; // 7 x f32 vector value def v7i32 : ValueType<224, 61>; // 7 x f32 vector value
def v8i32 : ValueType<256, 61>; // 8 x i32 vector value def v8i32 : ValueType<256, 62>; // 8 x i32 vector value
def v16i32 : ValueType<512, 62>; // 16 x i32 vector value def v16i32 : ValueType<512, 63>; // 16 x i32 vector value
def v32i32 : ValueType<1024, 63>; // 32 x i32 vector value def v32i32 : ValueType<1024, 64>; // 32 x i32 vector value
def v64i32 : ValueType<2048, 64>; // 64 x i32 vector value def v64i32 : ValueType<2048, 65>; // 64 x i32 vector value
def v128i32 : ValueType<4096, 65>; // 128 x i32 vector value def v128i32 : ValueType<4096, 66>; // 128 x i32 vector value
def v256i32 : ValueType<8192, 66>; // 256 x i32 vector value def v256i32 : ValueType<8192, 67>; // 256 x i32 vector value
def v512i32 : ValueType<16384, 67>; // 512 x i32 vector value def v512i32 : ValueType<16384, 68>; // 512 x i32 vector value
def v1024i32 : ValueType<32768, 68>; // 1024 x i32 vector value def v1024i32 : ValueType<32768, 69>; // 1024 x i32 vector value
def v2048i32 : ValueType<65536, 69>; // 2048 x i32 vector value def v2048i32 : ValueType<65536, 70>; // 2048 x i32 vector value
def v1i64 : ValueType<64, 70>; // 1 x i64 vector value def v1i64 : ValueType<64, 71>; // 1 x i64 vector value
def v2i64 : ValueType<128, 71>; // 2 x i64 vector value def v2i64 : ValueType<128, 72>; // 2 x i64 vector value
def v3i64 : ValueType<192, 72>; // 3 x i64 vector value def v3i64 : ValueType<192, 73>; // 3 x i64 vector value
def v4i64 : ValueType<256, 73>; // 4 x i64 vector value def v4i64 : ValueType<256, 74>; // 4 x i64 vector value
def v8i64 : ValueType<512, 74>; // 8 x i64 vector value def v8i64 : ValueType<512, 75>; // 8 x i64 vector value
def v16i64 : ValueType<1024, 75>; // 16 x i64 vector value def v16i64 : ValueType<1024, 76>; // 16 x i64 vector value
def v32i64 : ValueType<2048, 76>; // 32 x i64 vector value def v32i64 : ValueType<2048, 77>; // 32 x i64 vector value
def v64i64 : ValueType<4096, 77>; // 64 x i64 vector value def v64i64 : ValueType<4096, 78>; // 64 x i64 vector value
def v128i64 : ValueType<8192, 78>; // 128 x i64 vector value def v128i64 : ValueType<8192, 79>; // 128 x i64 vector value
def v256i64 : ValueType<16384, 79>; // 256 x i64 vector value def v256i64 : ValueType<16384, 80>; // 256 x i64 vector value
def v1i128 : ValueType<128, 80>; // 1 x i128 vector value def v1i128 : ValueType<128, 81>; // 1 x i128 vector value
def v1f16 : ValueType<16, 81>; // 1 x f16 vector value def v1f16 : ValueType<16, 82>; // 1 x f16 vector value
def v2f16 : ValueType<32, 82>; // 2 x f16 vector value def v2f16 : ValueType<32, 83>; // 2 x f16 vector value
def v3f16 : ValueType<48, 83>; // 3 x f16 vector value def v3f16 : ValueType<48, 84>; // 3 x f16 vector value
def v4f16 : ValueType<64, 84>; // 4 x f16 vector value def v4f16 : ValueType<64, 85>; // 4 x f16 vector value
def v8f16 : ValueType<128, 85>; // 8 x f16 vector value def v8f16 : ValueType<128, 86>; // 8 x f16 vector value
def v16f16 : ValueType<256, 86>; // 16 x f16 vector value def v16f16 : ValueType<256, 87>; // 16 x f16 vector value
def v32f16 : ValueType<512, 87>; // 32 x f16 vector value def v32f16 : ValueType<512, 88>; // 32 x f16 vector value
def v64f16 : ValueType<1024, 88>; // 64 x f16 vector value def v64f16 : ValueType<1024, 89>; // 64 x f16 vector value
def v128f16 : ValueType<2048, 89>; // 128 x f16 vector value def v128f16 : ValueType<2048, 90>; // 128 x f16 vector value
def v256f16 : ValueType<4096, 90>; // 256 x f16 vector value def v256f16 : ValueType<4096, 91>; // 256 x f16 vector value
def v512f16 : ValueType<8192, 91>; // 512 x f16 vector value def v512f16 : ValueType<8192, 92>; // 512 x f16 vector value
def v2bf16 : ValueType<32, 92>; // 2 x bf16 vector value def v2bf16 : ValueType<32, 93>; // 2 x bf16 vector value
def v3bf16 : ValueType<48, 93>; // 3 x bf16 vector value def v3bf16 : ValueType<48, 94>; // 3 x bf16 vector value
def v4bf16 : ValueType<64, 94>; // 4 x bf16 vector value def v4bf16 : ValueType<64, 95>; // 4 x bf16 vector value
def v8bf16 : ValueType<128, 95>; // 8 x bf16 vector value def v8bf16 : ValueType<128, 96>; // 8 x bf16 vector value
def v16bf16 : ValueType<256, 96>; // 16 x bf16 vector value def v16bf16 : ValueType<256, 97>; // 16 x bf16 vector value
def v32bf16 : ValueType<512, 97>; // 32 x bf16 vector value def v32bf16 : ValueType<512, 98>; // 32 x bf16 vector value
def v64bf16 : ValueType<1024, 98>; // 64 x bf16 vector value def v64bf16 : ValueType<1024, 99>; // 64 x bf16 vector value
def v128bf16 : ValueType<2048, 99>; // 128 x bf16 vector value def v128bf16 : ValueType<2048, 100>; // 128 x bf16 vector value
def v1f32 : ValueType<32, 100>; // 1 x f32 vector value def v1f32 : ValueType<32, 101>; // 1 x f32 vector value
def v2f32 : ValueType<64, 101>; // 2 x f32 vector value def v2f32 : ValueType<64, 102>; // 2 x f32 vector value
def v3f32 : ValueType<96, 102>; // 3 x f32 vector value def v3f32 : ValueType<96, 103>; // 3 x f32 vector value
def v4f32 : ValueType<128, 103>; // 4 x f32 vector value def v4f32 : ValueType<128, 104>; // 4 x f32 vector value
def v5f32 : ValueType<160, 104>; // 5 x f32 vector value def v5f32 : ValueType<160, 105>; // 5 x f32 vector value
def v6f32 : ValueType<192, 105>; // 6 x f32 vector value def v6f32 : ValueType<192, 106>; // 6 x f32 vector value
def v7f32 : ValueType<224, 106>; // 7 x f32 vector value def v7f32 : ValueType<224, 107>; // 7 x f32 vector value
def v8f32 : ValueType<256, 107>; // 8 x f32 vector value def v8f32 : ValueType<256, 108>; // 8 x f32 vector value
def v16f32 : ValueType<512, 108>; // 16 x f32 vector value def v16f32 : ValueType<512, 109>; // 16 x f32 vector value
def v32f32 : ValueType<1024, 109>; // 32 x f32 vector value def v32f32 : ValueType<1024, 110>; // 32 x f32 vector value
def v64f32 : ValueType<2048, 110>; // 64 x f32 vector value def v64f32 : ValueType<2048, 111>; // 64 x f32 vector value
def v128f32 : ValueType<4096, 111>; // 128 x f32 vector value def v128f32 : ValueType<4096, 112>; // 128 x f32 vector value
def v256f32 : ValueType<8192, 112>; // 256 x f32 vector value def v256f32 : ValueType<8192, 113>; // 256 x f32 vector value
def v512f32 : ValueType<16384, 113>; // 512 x f32 vector value def v512f32 : ValueType<16384, 114>; // 512 x f32 vector value
def v1024f32 : ValueType<32768, 114>; // 1024 x f32 vector value def v1024f32 : ValueType<32768, 115>; // 1024 x f32 vector value
def v2048f32 : ValueType<65536, 115>; // 2048 x f32 vector value def v2048f32 : ValueType<65536, 116>; // 2048 x f32 vector value
def v1f64 : ValueType<64, 116>; // 1 x f64 vector value def v1f64 : ValueType<64, 117>; // 1 x f64 vector value
def v2f64 : ValueType<128, 117>; // 2 x f64 vector value def v2f64 : ValueType<128, 118>; // 2 x f64 vector value
def v3f64 : ValueType<192, 118>; // 3 x f64 vector value def v3f64 : ValueType<192, 119>; // 3 x f64 vector value
def v4f64 : ValueType<256, 119>; // 4 x f64 vector value def v4f64 : ValueType<256, 120>; // 4 x f64 vector value
def v8f64 : ValueType<512, 120>; // 8 x f64 vector value def v8f64 : ValueType<512, 121>; // 8 x f64 vector value
def v16f64 : ValueType<1024, 121>; // 16 x f64 vector value def v16f64 : ValueType<1024, 122>; // 16 x f64 vector value
def v32f64 : ValueType<2048, 122>; // 32 x f64 vector value def v32f64 : ValueType<2048, 123>; // 32 x f64 vector value
def v64f64 : ValueType<4096, 123>; // 64 x f64 vector value def v64f64 : ValueType<4096, 124>; // 64 x f64 vector value
def v128f64 : ValueType<8192, 124>; // 128 x f64 vector value def v128f64 : ValueType<8192, 125>; // 128 x f64 vector value
def v256f64 : ValueType<16384, 125>; // 256 x f64 vector value def v256f64 : ValueType<16384, 126>; // 256 x f64 vector value
def nxv1i1 : ValueType<1, 126>; // n x 1 x i1 vector value def nxv1i1 : ValueType<1, 127>; // n x 1 x i1 vector value
def nxv2i1 : ValueType<2, 127>; // n x 2 x i1 vector value def nxv2i1 : ValueType<2, 128>; // n x 2 x i1 vector value
def nxv4i1 : ValueType<4, 128>; // n x 4 x i1 vector value def nxv4i1 : ValueType<4, 129>; // n x 4 x i1 vector value
def nxv8i1 : ValueType<8, 129>; // n x 8 x i1 vector value def nxv8i1 : ValueType<8, 130>; // n x 8 x i1 vector value
def nxv16i1 : ValueType<16, 130>; // n x 16 x i1 vector value def nxv16i1 : ValueType<16, 131>; // n x 16 x i1 vector value
def nxv32i1 : ValueType<32, 131>; // n x 32 x i1 vector value def nxv32i1 : ValueType<32, 132>; // n x 32 x i1 vector value
def nxv64i1 : ValueType<64, 132>; // n x 64 x i1 vector value def nxv64i1 : ValueType<64, 133>; // n x 64 x i1 vector value
def nxv1i8 : ValueType<8, 133>; // n x 1 x i8 vector value def nxv1i8 : ValueType<8, 134>; // n x 1 x i8 vector value
def nxv2i8 : ValueType<16, 134>; // n x 2 x i8 vector value def nxv2i8 : ValueType<16, 135>; // n x 2 x i8 vector value
def nxv4i8 : ValueType<32, 135>; // n x 4 x i8 vector value def nxv4i8 : ValueType<32, 136>; // n x 4 x i8 vector value
def nxv8i8 : ValueType<64, 136>; // n x 8 x i8 vector value def nxv8i8 : ValueType<64, 137>; // n x 8 x i8 vector value
def nxv16i8 : ValueType<128, 137>; // n x 16 x i8 vector value def nxv16i8 : ValueType<128, 138>; // n x 16 x i8 vector value
def nxv32i8 : ValueType<256, 138>; // n x 32 x i8 vector value def nxv32i8 : ValueType<256, 139>; // n x 32 x i8 vector value
def nxv64i8 : ValueType<512, 139>; // n x 64 x i8 vector value def nxv64i8 : ValueType<512, 140>; // n x 64 x i8 vector value
def nxv1i16 : ValueType<16, 140>; // n x 1 x i16 vector value def nxv1i16 : ValueType<16, 141>; // n x 1 x i16 vector value
def nxv2i16 : ValueType<32, 141>; // n x 2 x i16 vector value def nxv2i16 : ValueType<32, 142>; // n x 2 x i16 vector value
def nxv4i16 : ValueType<64, 142>; // n x 4 x i16 vector value def nxv4i16 : ValueType<64, 143>; // n x 4 x i16 vector value
def nxv8i16 : ValueType<128, 143>; // n x 8 x i16 vector value def nxv8i16 : ValueType<128, 144>; // n x 8 x i16 vector value
def nxv16i16 : ValueType<256, 144>; // n x 16 x i16 vector value def nxv16i16 : ValueType<256, 145>; // n x 16 x i16 vector value
def nxv32i16 : ValueType<512, 145>; // n x 32 x i16 vector value def nxv32i16 : ValueType<512, 146>; // n x 32 x i16 vector value
def nxv1i32 : ValueType<32, 146>; // n x 1 x i32 vector value def nxv1i32 : ValueType<32, 147>; // n x 1 x i32 vector value
def nxv2i32 : ValueType<64, 147>; // n x 2 x i32 vector value def nxv2i32 : ValueType<64, 148>; // n x 2 x i32 vector value
def nxv4i32 : ValueType<128, 148>; // n x 4 x i32 vector value def nxv4i32 : ValueType<128, 149>; // n x 4 x i32 vector value
def nxv8i32 : ValueType<256, 149>; // n x 8 x i32 vector value def nxv8i32 : ValueType<256, 150>; // n x 8 x i32 vector value
def nxv16i32 : ValueType<512, 150>; // n x 16 x i32 vector value def nxv16i32 : ValueType<512, 151>; // n x 16 x i32 vector value
def nxv32i32 : ValueType<1024, 151>; // n x 32 x i32 vector value def nxv32i32 : ValueType<1024, 152>; // n x 32 x i32 vector value
def nxv1i64 : ValueType<64, 152>; // n x 1 x i64 vector value def nxv1i64 : ValueType<64, 153>; // n x 1 x i64 vector value
def nxv2i64 : ValueType<128, 153>; // n x 2 x i64 vector value def nxv2i64 : ValueType<128, 154>; // n x 2 x i64 vector value
def nxv4i64 : ValueType<256, 154>; // n x 4 x i64 vector value def nxv4i64 : ValueType<256, 155>; // n x 4 x i64 vector value
def nxv8i64 : ValueType<512, 155>; // n x 8 x i64 vector value def nxv8i64 : ValueType<512, 156>; // n x 8 x i64 vector value
def nxv16i64 : ValueType<1024, 156>; // n x 16 x i64 vector value def nxv16i64 : ValueType<1024, 157>; // n x 16 x i64 vector value
def nxv32i64 : ValueType<2048, 157>; // n x 32 x i64 vector value def nxv32i64 : ValueType<2048, 158>; // n x 32 x i64 vector value
def nxv1f16 : ValueType<16, 158>; // n x 1 x f16 vector value def nxv1f16 : ValueType<16, 159>; // n x 1 x f16 vector value
def nxv2f16 : ValueType<32, 159>; // n x 2 x f16 vector value def nxv2f16 : ValueType<32, 160>; // n x 2 x f16 vector value
def nxv4f16 : ValueType<64, 160>; // n x 4 x f16 vector value def nxv4f16 : ValueType<64, 161>; // n x 4 x f16 vector value
def nxv8f16 : ValueType<128, 161>; // n x 8 x f16 vector value def nxv8f16 : ValueType<128, 162>; // n x 8 x f16 vector value
def nxv16f16 : ValueType<256, 162>; // n x 16 x f16 vector value def nxv16f16 : ValueType<256, 163>; // n x 16 x f16 vector value
def nxv32f16 : ValueType<512, 163>; // n x 32 x f16 vector value def nxv32f16 : ValueType<512, 164>; // n x 32 x f16 vector value
def nxv1bf16 : ValueType<16, 164>; // n x 1 x bf16 vector value def nxv1bf16 : ValueType<16, 165>; // n x 1 x bf16 vector value
def nxv2bf16 : ValueType<32, 165>; // n x 2 x bf16 vector value def nxv2bf16 : ValueType<32, 166>; // n x 2 x bf16 vector value
def nxv4bf16 : ValueType<64, 166>; // n x 4 x bf16 vector value def nxv4bf16 : ValueType<64, 167>; // n x 4 x bf16 vector value
def nxv8bf16 : ValueType<128, 167>; // n x 8 x bf16 vector value def nxv8bf16 : ValueType<128, 168>; // n x 8 x bf16 vector value
def nxv16bf16 : ValueType<256, 168>; // n x 16 x bf16 vector value def nxv16bf16 : ValueType<256, 169>; // n x 16 x bf16 vector value
def nxv32bf16 : ValueType<512, 169>; // n x 32 x bf16 vector value def nxv32bf16 : ValueType<512, 170>; // n x 32 x bf16 vector value
def nxv1f32 : ValueType<32, 170>; // n x 1 x f32 vector value def nxv1f32 : ValueType<32, 171>; // n x 1 x f32 vector value
def nxv2f32 : ValueType<64, 171>; // n x 2 x f32 vector value def nxv2f32 : ValueType<64, 172>; // n x 2 x f32 vector value
def nxv4f32 : ValueType<128, 172>; // n x 4 x f32 vector value def nxv4f32 : ValueType<128, 173>; // n x 4 x f32 vector value
def nxv8f32 : ValueType<256, 173>; // n x 8 x f32 vector value def nxv8f32 : ValueType<256, 174>; // n x 8 x f32 vector value
def nxv16f32 : ValueType<512, 174>; // n x 16 x f32 vector value def nxv16f32 : ValueType<512, 175>; // n x 16 x f32 vector value
def nxv1f64 : ValueType<64, 175>; // n x 1 x f64 vector value def nxv1f64 : ValueType<64, 176>; // n x 1 x f64 vector value
def nxv2f64 : ValueType<128, 176>; // n x 2 x f64 vector value def nxv2f64 : ValueType<128, 177>; // n x 2 x f64 vector value
def nxv4f64 : ValueType<256, 177>; // n x 4 x f64 vector value def nxv4f64 : ValueType<256, 178>; // n x 4 x f64 vector value
def nxv8f64 : ValueType<512, 178>; // n x 8 x f64 vector value def nxv8f64 : ValueType<512, 179>; // n x 8 x f64 vector value
def x86mmx : ValueType<64, 179>; // X86 MMX value def x86mmx : ValueType<64, 180>; // X86 MMX value
def FlagVT : ValueType<0, 180>; // Pre-RA sched glue def FlagVT : ValueType<0, 181>; // Pre-RA sched glue
def isVoid : ValueType<0, 181>; // Produces no value def isVoid : ValueType<0, 182>; // Produces no value
def untyped : ValueType<8, 182>; // Produces an untyped value def untyped : ValueType<8, 183>; // Produces an untyped value
def funcref : ValueType<0, 183>; // WebAssembly's funcref type def funcref : ValueType<0, 184>; // WebAssembly's funcref type
def externref : ValueType<0, 184>; // WebAssembly's externref type def externref : ValueType<0, 185>; // WebAssembly's externref type
def x86amx : ValueType<8192, 185>; // X86 AMX value def x86amx : ValueType<8192, 186>; // X86 AMX value
def i64x8 : ValueType<512, 186>; // 8 Consecutive GPRs (AArch64) def i64x8 : ValueType<512, 187>; // 8 Consecutive GPRs (AArch64)
def token : ValueType<0, 248>; // TokenTy def token : ValueType<0, 248>; // TokenTy
def MetadataVT : ValueType<0, 249>; // Metadata def MetadataVT : ValueType<0, 249>; // Metadata
// Pseudo valuetype mapped to the current pointer size to any address space. // Pseudo valuetype mapped to the current pointer size to any address space.
// Should only be used in TableGen. // Should only be used in TableGen.
def iPTRAny : ValueType<0, 250>; def iPTRAny : ValueType<0, 250>;
Show All 25 Lines

llvm/include/llvm/IR/Intrinsics.td

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Lines
def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1 def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1
def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1 def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1
def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1 def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1
def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1 def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1
def llvm_v256i1_ty : LLVMType<v256i1>; // 256 x i1 def llvm_v256i1_ty : LLVMType<v256i1>; // 256 x i1
def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1 def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1
def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1 def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
def llvm_v2048i1_ty : LLVMType<v2048i1>; //2048 x i1
def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8 def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8 def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8 def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8 def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8 def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8
def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8 def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8 def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8
▲ Show 20 Lines • Show All 1,845 Lines • Show Last 20 Lines

llvm/include/llvm/Support/MachineValueType.h

//===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===// //===- Support/MachineValueType.h - Machine-Level types ---------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines the set of machine-level target independent types which // This file defines the set of machine-level target independent types which
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines enum SimpleValueType : uint8_t {
v8i1 = 20, // 8 x i1 v8i1 = 20, // 8 x i1
v16i1 = 21, // 16 x i1 v16i1 = 21, // 16 x i1
v32i1 = 22, // 32 x i1 v32i1 = 22, // 32 x i1
v64i1 = 23, // 64 x i1 v64i1 = 23, // 64 x i1
v128i1 = 24, // 128 x i1 v128i1 = 24, // 128 x i1
v256i1 = 25, // 256 x i1 v256i1 = 25, // 256 x i1
v512i1 = 26, // 512 x i1 v512i1 = 26, // 512 x i1
v1024i1 = 27, // 1024 x i1 v1024i1 = 27, // 1024 x i1
v2048i1 = 28, // 2048 x i1
v128i2 = 28, // 128 x i2 v128i2 = 29, // 128 x i2
v256i2 = 29, // 256 x i2 v256i2 = 30, // 256 x i2
v64i4 = 30, // 64 x i4 v64i4 = 31, // 64 x i4
v128i4 = 31, // 128 x i4 v128i4 = 32, // 128 x i4
v1i8 = 32, // 1 x i8 v1i8 = 33, // 1 x i8
v2i8 = 33, // 2 x i8 v2i8 = 34, // 2 x i8
v4i8 = 34, // 4 x i8 v4i8 = 35, // 4 x i8
v8i8 = 35, // 8 x i8 v8i8 = 36, // 8 x i8
v16i8 = 36, // 16 x i8 v16i8 = 37, // 16 x i8
v32i8 = 37, // 32 x i8 v32i8 = 38, // 32 x i8
v64i8 = 38, // 64 x i8 v64i8 = 39, // 64 x i8
v128i8 = 39, // 128 x i8 v128i8 = 40, // 128 x i8
v256i8 = 40, // 256 x i8 v256i8 = 41, // 256 x i8
v512i8 = 41, // 512 x i8 v512i8 = 42, // 512 x i8
v1024i8 = 42, // 1024 x i8 v1024i8 = 43, // 1024 x i8
v1i16 = 43, // 1 x i16 v1i16 = 44, // 1 x i16
v2i16 = 44, // 2 x i16 v2i16 = 45, // 2 x i16
v3i16 = 45, // 3 x i16 v3i16 = 46, // 3 x i16
v4i16 = 46, // 4 x i16 v4i16 = 47, // 4 x i16
v8i16 = 47, // 8 x i16 v8i16 = 48, // 8 x i16
v16i16 = 48, // 16 x i16 v16i16 = 49, // 16 x i16
v32i16 = 49, // 32 x i16 v32i16 = 50, // 32 x i16
v64i16 = 50, // 64 x i16 v64i16 = 51, // 64 x i16
v128i16 = 51, // 128 x i16 v128i16 = 52, // 128 x i16
v256i16 = 52, // 256 x i16 v256i16 = 53, // 256 x i16
v512i16 = 53, // 512 x i16 v512i16 = 54, // 512 x i16
v1i32 = 54, // 1 x i32 v1i32 = 55, // 1 x i32
v2i32 = 55, // 2 x i32 v2i32 = 56, // 2 x i32
v3i32 = 56, // 3 x i32 v3i32 = 57, // 3 x i32
v4i32 = 57, // 4 x i32 v4i32 = 58, // 4 x i32
v5i32 = 58, // 5 x i32 v5i32 = 59, // 5 x i32
v6i32 = 59, // 6 x i32 v6i32 = 60, // 6 x i32
v7i32 = 60, // 7 x i32 v7i32 = 61, // 7 x i32
v8i32 = 61, // 8 x i32 v8i32 = 62, // 8 x i32
v16i32 = 62, // 16 x i32 v16i32 = 63, // 16 x i32
v32i32 = 63, // 32 x i32 v32i32 = 64, // 32 x i32
v64i32 = 64, // 64 x i32 v64i32 = 65, // 64 x i32
v128i32 = 65, // 128 x i32 v128i32 = 66, // 128 x i32
v256i32 = 66, // 256 x i32 v256i32 = 67, // 256 x i32
v512i32 = 67, // 512 x i32 v512i32 = 68, // 512 x i32
v1024i32 = 68, // 1024 x i32 v1024i32 = 69, // 1024 x i32
v2048i32 = 69, // 2048 x i32 v2048i32 = 70, // 2048 x i32
v1i64 = 70, // 1 x i64 v1i64 = 71, // 1 x i64
v2i64 = 71, // 2 x i64 v2i64 = 72, // 2 x i64
v3i64 = 72, // 3 x i64 v3i64 = 73, // 3 x i64
v4i64 = 73, // 4 x i64 v4i64 = 74, // 4 x i64
v8i64 = 74, // 8 x i64 v8i64 = 75, // 8 x i64
v16i64 = 75, // 16 x i64 v16i64 = 76, // 16 x i64
v32i64 = 76, // 32 x i64 v32i64 = 77, // 32 x i64
v64i64 = 77, // 64 x i64 v64i64 = 78, // 64 x i64
v128i64 = 78, // 128 x i64 v128i64 = 79, // 128 x i64
v256i64 = 79, // 256 x i64 v256i64 = 80, // 256 x i64
v1i128 = 80, // 1 x i128 v1i128 = 81, // 1 x i128
FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1, FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128, LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
v1f16 = 81, // 1 x f16 v1f16 = 82, // 1 x f16
v2f16 = 82, // 2 x f16 v2f16 = 83, // 2 x f16
v3f16 = 83, // 3 x f16 v3f16 = 84, // 3 x f16
v4f16 = 84, // 4 x f16 v4f16 = 85, // 4 x f16
v8f16 = 85, // 8 x f16 v8f16 = 86, // 8 x f16
v16f16 = 86, // 16 x f16 v16f16 = 87, // 16 x f16
v32f16 = 87, // 32 x f16 v32f16 = 88, // 32 x f16
v64f16 = 88, // 64 x f16 v64f16 = 89, // 64 x f16
v128f16 = 89, // 128 x f16 v128f16 = 90, // 128 x f16
v256f16 = 90, // 256 x f16 v256f16 = 91, // 256 x f16
v512f16 = 91, // 512 x f16 v512f16 = 92, // 512 x f16
v2bf16 = 92, // 2 x bf16 v2bf16 = 93, // 2 x bf16
v3bf16 = 93, // 3 x bf16 v3bf16 = 94, // 3 x bf16
v4bf16 = 94, // 4 x bf16 v4bf16 = 95, // 4 x bf16
v8bf16 = 95, // 8 x bf16 v8bf16 = 96, // 8 x bf16
v16bf16 = 96, // 16 x bf16 v16bf16 = 97, // 16 x bf16
v32bf16 = 97, // 32 x bf16 v32bf16 = 98, // 32 x bf16
v64bf16 = 98, // 64 x bf16 v64bf16 = 99, // 64 x bf16
v128bf16 = 99, // 128 x bf16 v128bf16 = 100, // 128 x bf16
v1f32 = 100, // 1 x f32 v1f32 = 101, // 1 x f32
v2f32 = 101, // 2 x f32 v2f32 = 102, // 2 x f32
v3f32 = 102, // 3 x f32 v3f32 = 103, // 3 x f32
v4f32 = 103, // 4 x f32 v4f32 = 104, // 4 x f32
v5f32 = 104, // 5 x f32 v5f32 = 105, // 5 x f32
v6f32 = 105, // 6 x f32 v6f32 = 106, // 6 x f32
v7f32 = 106, // 7 x f32 v7f32 = 107, // 7 x f32
v8f32 = 107, // 8 x f32 v8f32 = 108, // 8 x f32
v16f32 = 108, // 16 x f32 v16f32 = 109, // 16 x f32
v32f32 = 109, // 32 x f32 v32f32 = 110, // 32 x f32
v64f32 = 110, // 64 x f32 v64f32 = 111, // 64 x f32
v128f32 = 111, // 128 x f32 v128f32 = 112, // 128 x f32
v256f32 = 112, // 256 x f32 v256f32 = 113, // 256 x f32
v512f32 = 113, // 512 x f32 v512f32 = 114, // 512 x f32
v1024f32 = 114, // 1024 x f32 v1024f32 = 115, // 1024 x f32
v2048f32 = 115, // 2048 x f32 v2048f32 = 116, // 2048 x f32
v1f64 = 116, // 1 x f64 v1f64 = 117, // 1 x f64
v2f64 = 117, // 2 x f64 v2f64 = 118, // 2 x f64
v3f64 = 118, // 3 x f64 v3f64 = 119, // 3 x f64
v4f64 = 119, // 4 x f64 v4f64 = 120, // 4 x f64
v8f64 = 120, // 8 x f64 v8f64 = 121, // 8 x f64
v16f64 = 121, // 16 x f64 v16f64 = 122, // 16 x f64
v32f64 = 122, // 32 x f64 v32f64 = 123, // 32 x f64
v64f64 = 123, // 64 x f64 v64f64 = 124, // 64 x f64
v128f64 = 124, // 128 x f64 v128f64 = 125, // 128 x f64
v256f64 = 125, // 256 x f64 v256f64 = 126, // 256 x f64
FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16, FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16,
LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64, LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1, FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64, LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
nxv1i1 = 126, // n x 1 x i1 nxv1i1 = 127, // n x 1 x i1
nxv2i1 = 127, // n x 2 x i1 nxv2i1 = 128, // n x 2 x i1
nxv4i1 = 128, // n x 4 x i1 nxv4i1 = 129, // n x 4 x i1
nxv8i1 = 129, // n x 8 x i1 nxv8i1 = 130, // n x 8 x i1
nxv16i1 = 130, // n x 16 x i1 nxv16i1 = 131, // n x 16 x i1
nxv32i1 = 131, // n x 32 x i1 nxv32i1 = 132, // n x 32 x i1
nxv64i1 = 132, // n x 64 x i1 nxv64i1 = 133, // n x 64 x i1
nxv1i8 = 133, // n x 1 x i8 nxv1i8 = 134, // n x 1 x i8
nxv2i8 = 134, // n x 2 x i8 nxv2i8 = 135, // n x 2 x i8
nxv4i8 = 135, // n x 4 x i8 nxv4i8 = 136, // n x 4 x i8
nxv8i8 = 136, // n x 8 x i8 nxv8i8 = 137, // n x 8 x i8
nxv16i8 = 137, // n x 16 x i8 nxv16i8 = 138, // n x 16 x i8
nxv32i8 = 138, // n x 32 x i8 nxv32i8 = 139, // n x 32 x i8
nxv64i8 = 139, // n x 64 x i8 nxv64i8 = 140, // n x 64 x i8
nxv1i16 = 140, // n x 1 x i16 nxv1i16 = 141, // n x 1 x i16
nxv2i16 = 141, // n x 2 x i16 nxv2i16 = 142, // n x 2 x i16
nxv4i16 = 142, // n x 4 x i16 nxv4i16 = 143, // n x 4 x i16
nxv8i16 = 143, // n x 8 x i16 nxv8i16 = 144, // n x 8 x i16
nxv16i16 = 144, // n x 16 x i16 nxv16i16 = 145, // n x 16 x i16
nxv32i16 = 145, // n x 32 x i16 nxv32i16 = 146, // n x 32 x i16
nxv1i32 = 146, // n x 1 x i32 nxv1i32 = 147, // n x 1 x i32
nxv2i32 = 147, // n x 2 x i32 nxv2i32 = 148, // n x 2 x i32
nxv4i32 = 148, // n x 4 x i32 nxv4i32 = 149, // n x 4 x i32
nxv8i32 = 149, // n x 8 x i32 nxv8i32 = 150, // n x 8 x i32
nxv16i32 = 150, // n x 16 x i32 nxv16i32 = 151, // n x 16 x i32
nxv32i32 = 151, // n x 32 x i32 nxv32i32 = 152, // n x 32 x i32
nxv1i64 = 152, // n x 1 x i64 nxv1i64 = 153, // n x 1 x i64
nxv2i64 = 153, // n x 2 x i64 nxv2i64 = 154, // n x 2 x i64
nxv4i64 = 154, // n x 4 x i64 nxv4i64 = 155, // n x 4 x i64
nxv8i64 = 155, // n x 8 x i64 nxv8i64 = 156, // n x 8 x i64
nxv16i64 = 156, // n x 16 x i64 nxv16i64 = 157, // n x 16 x i64
nxv32i64 = 157, // n x 32 x i64 nxv32i64 = 158, // n x 32 x i64
FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1, FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64, LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
nxv1f16 = 158, // n x 1 x f16 nxv1f16 = 159, // n x 1 x f16
nxv2f16 = 159, // n x 2 x f16 nxv2f16 = 160, // n x 2 x f16
nxv4f16 = 160, // n x 4 x f16 nxv4f16 = 161, // n x 4 x f16
nxv8f16 = 161, // n x 8 x f16 nxv8f16 = 162, // n x 8 x f16
nxv16f16 = 162, // n x 16 x f16 nxv16f16 = 163, // n x 16 x f16
nxv32f16 = 163, // n x 32 x f16 nxv32f16 = 164, // n x 32 x f16
nxv1bf16 = 164, // n x 1 x bf16 nxv1bf16 = 165, // n x 1 x bf16
nxv2bf16 = 165, // n x 2 x bf16 nxv2bf16 = 166, // n x 2 x bf16
nxv4bf16 = 166, // n x 4 x bf16 nxv4bf16 = 167, // n x 4 x bf16
nxv8bf16 = 167, // n x 8 x bf16 nxv8bf16 = 168, // n x 8 x bf16
nxv16bf16 = 168, // n x 16 x bf16 nxv16bf16 = 169, // n x 16 x bf16
nxv32bf16 = 169, // n x 32 x bf16 nxv32bf16 = 170, // n x 32 x bf16
nxv1f32 = 170, // n x 1 x f32 nxv1f32 = 171, // n x 1 x f32
nxv2f32 = 171, // n x 2 x f32 nxv2f32 = 172, // n x 2 x f32
nxv4f32 = 172, // n x 4 x f32 nxv4f32 = 173, // n x 4 x f32
nxv8f32 = 173, // n x 8 x f32 nxv8f32 = 174, // n x 8 x f32
nxv16f32 = 174, // n x 16 x f32 nxv16f32 = 175, // n x 16 x f32
nxv1f64 = 175, // n x 1 x f64 nxv1f64 = 176, // n x 1 x f64
nxv2f64 = 176, // n x 2 x f64 nxv2f64 = 177, // n x 2 x f64
nxv4f64 = 177, // n x 4 x f64 nxv4f64 = 178, // n x 4 x f64
nxv8f64 = 178, // n x 8 x f64 nxv8f64 = 179, // n x 8 x f64
FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16, FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64, LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1, FIRST_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64, LAST_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
FIRST_VECTOR_VALUETYPE = v1i1, FIRST_VECTOR_VALUETYPE = v1i1,
LAST_VECTOR_VALUETYPE = nxv8f64, LAST_VECTOR_VALUETYPE = nxv8f64,
x86mmx = 179, // This is an X86 MMX value x86mmx = 180, // This is an X86 MMX value
Glue = 180, // This glues nodes together during pre-RA sched Glue = 181, // This glues nodes together during pre-RA sched
isVoid = 181, // This has no value isVoid = 182, // This has no value
Untyped = 182, // This value takes a register, but has Untyped = 183, // This value takes a register, but has
// unspecified type. The register class // unspecified type. The register class
// will be determined by the opcode. // will be determined by the opcode.
funcref = 183, // WebAssembly's funcref type funcref = 184, // WebAssembly's funcref type
externref = 184, // WebAssembly's externref type externref = 185, // WebAssembly's externref type
x86amx = 185, // This is an X86 AMX value x86amx = 186, // This is an X86 AMX value
i64x8 = 186, // 8 Consecutive GPRs (AArch64) i64x8 = 187, // 8 Consecutive GPRs (AArch64)
FIRST_VALUETYPE = 1, // This is always the beginning of the list. FIRST_VALUETYPE = 1, // This is always the beginning of the list.
LAST_VALUETYPE = i64x8, // This always remains at the end of the list. LAST_VALUETYPE = i64x8, // This always remains at the end of the list.
VALUETYPE_SIZE = LAST_VALUETYPE + 1, VALUETYPE_SIZE = LAST_VALUETYPE + 1,
// This is the current maximum for LAST_VALUETYPE. // This is the current maximum for LAST_VALUETYPE.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
// This value must be a multiple of 32. // This value must be a multiple of 32.
▲ Show 20 Lines • Show All 159 Lines • ▼ Show 20 Lines bool is1024BitVector() const {
SimpleTy == MVT::v64bf16); SimpleTy == MVT::v64bf16);
} }
/// Return true if this is a 2048-bit vector type. /// Return true if this is a 2048-bit vector type.
bool is2048BitVector() const { bool is2048BitVector() const {
return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 || return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 ||
SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 || SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 ||
SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 || SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 ||
SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16); SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16 ||
SimpleTy == MVT::v2048i1);
} }
/// Return true if this is an overloaded type for TableGen. /// Return true if this is an overloaded type for TableGen.
bool isOverloaded() const { bool isOverloaded() const {
return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny || return (SimpleTy == MVT::Any || SimpleTy == MVT::iAny ||
SimpleTy == MVT::fAny || SimpleTy == MVT::vAny || SimpleTy == MVT::fAny || SimpleTy == MVT::vAny ||
SimpleTy == MVT::iPTRAny); SimpleTy == MVT::iPTRAny);
} }
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines MVT getVectorElementType() const {
case v8i1: case v8i1:
case v16i1: case v16i1:
case v32i1: case v32i1:
case v64i1: case v64i1:
case v128i1: case v128i1:
case v256i1: case v256i1:
case v512i1: case v512i1:
case v1024i1: case v1024i1:
case v2048i1:
case nxv1i1: case nxv1i1:
case nxv2i1: case nxv2i1:
case nxv4i1: case nxv4i1:
case nxv8i1: case nxv8i1:
case nxv16i1: case nxv16i1:
case nxv32i1: case nxv32i1:
case nxv64i1: return i1; case nxv64i1: return i1;
case v128i2: case v128i2:
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines MVT getVectorElementType() const {
// clang-format on // clang-format on
} }
/// Given a vector type, return the minimum number of elements it contains. /// Given a vector type, return the minimum number of elements it contains.
unsigned getVectorMinNumElements() const { unsigned getVectorMinNumElements() const {
switch (SimpleTy) { switch (SimpleTy) {
default: default:
llvm_unreachable("Not a vector MVT!"); llvm_unreachable("Not a vector MVT!");
case v2048i1:
case v2048i32: case v2048i32:
case v2048f32: return 2048; case v2048f32: return 2048;
case v1024i1: case v1024i1:
case v1024i8: case v1024i8:
case v1024i32: case v1024i32:
case v1024f32: return 1024; case v1024f32: return 1024;
case v512i1: case v512i1:
case v512i8: case v512i8:
▲ Show 20 Lines • Show All 334 Lines • ▼ Show 20 Lines TypeSize getSizeInBits() const {
case v32i32: case v32i32:
case v16i64: case v16i64:
case v64f16: case v64f16:
case v64bf16: case v64bf16:
case v32f32: case v32f32:
case v16f64: return TypeSize::Fixed(1024); case v16f64: return TypeSize::Fixed(1024);
case nxv32i32: case nxv32i32:
case nxv16i64: return TypeSize::Scalable(1024); case nxv16i64: return TypeSize::Scalable(1024);
case v2048i1:
case v256i8: case v256i8:
case v128i16: case v128i16:
case v64i32: case v64i32:
case v32i64: case v32i64:
case v128f16: case v128f16:
case v128bf16: case v128bf16:
case v64f32: case v64f32:
case v32f64: return TypeSize::Fixed(2048); case v32f64: return TypeSize::Fixed(2048);
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines static MVT getVectorVT(MVT VT, unsigned NumElements) {
if (NumElements == 8) return MVT::v8i1; if (NumElements == 8) return MVT::v8i1;
if (NumElements == 16) return MVT::v16i1; if (NumElements == 16) return MVT::v16i1;
if (NumElements == 32) return MVT::v32i1; if (NumElements == 32) return MVT::v32i1;
if (NumElements == 64) return MVT::v64i1; if (NumElements == 64) return MVT::v64i1;
if (NumElements == 128) return MVT::v128i1; if (NumElements == 128) return MVT::v128i1;
if (NumElements == 256) return MVT::v256i1; if (NumElements == 256) return MVT::v256i1;
if (NumElements == 512) return MVT::v512i1; if (NumElements == 512) return MVT::v512i1;
if (NumElements == 1024) return MVT::v1024i1; if (NumElements == 1024) return MVT::v1024i1;
if (NumElements == 2048) return MVT::v2048i1;
break; break;
case MVT::i2: case MVT::i2:
if (NumElements == 128) return MVT::v128i2; if (NumElements == 128) return MVT::v128i2;
if (NumElements == 256) return MVT::v256i2; if (NumElements == 256) return MVT::v256i2;
break; break;
case MVT::i4: case MVT::i4:
if (NumElements == 64) return MVT::v64i4; if (NumElements == 64) return MVT::v64i4;
if (NumElements == 128) return MVT::v128i4; if (NumElements == 128) return MVT::v128i4;
▲ Show 20 Lines • Show All 280 Lines • Show Last 20 Lines

llvm/lib/CodeGen/ValueTypes.cpp

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 LinesType *EVT::getTypeForEVT(LLVMContext &Context) const {
case MVT::v128i1: case MVT::v128i1:
return FixedVectorType::get(Type::getInt1Ty(Context), 128); return FixedVectorType::get(Type::getInt1Ty(Context), 128);
case MVT::v256i1: case MVT::v256i1:
return FixedVectorType::get(Type::getInt1Ty(Context), 256); return FixedVectorType::get(Type::getInt1Ty(Context), 256);
case MVT::v512i1: case MVT::v512i1:
return FixedVectorType::get(Type::getInt1Ty(Context), 512); return FixedVectorType::get(Type::getInt1Ty(Context), 512);
case MVT::v1024i1: case MVT::v1024i1:
return FixedVectorType::get(Type::getInt1Ty(Context), 1024); return FixedVectorType::get(Type::getInt1Ty(Context), 1024);
case MVT::v2048i1:
return FixedVectorType::get(Type::getInt1Ty(Context), 2048);
case MVT::v128i2: case MVT::v128i2:
return FixedVectorType::get(Type::getIntNTy(Context, 2), 128); return FixedVectorType::get(Type::getIntNTy(Context, 2), 128);
case MVT::v256i2: case MVT::v256i2:
return FixedVectorType::get(Type::getIntNTy(Context, 2), 256); return FixedVectorType::get(Type::getIntNTy(Context, 2), 256);
case MVT::v64i4: case MVT::v64i4:
return FixedVectorType::get(Type::getIntNTy(Context, 4), 64); return FixedVectorType::get(Type::getIntNTy(Context, 4), 64);
case MVT::v128i4: case MVT::v128i4:
return FixedVectorType::get(Type::getIntNTy(Context, 4), 128); return FixedVectorType::get(Type::getIntNTy(Context, 4), 128);
▲ Show 20 Lines • Show All 349 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/PPCMCExpr.h" #include "MCTargetDesc/PPCMCExpr.h"
Show All 14 Lines
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCSymbolELF.h"
#include "llvm/MC/TargetRegistry.h" #include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/SourceMgr.h" #include "llvm/Support/SourceMgr.h"
#include "llvm/Support/raw_ostream.h" #include "llvm/Support/raw_ostream.h"
using namespace llvm; using namespace llvm;
DEFINE_PPC_REGCLASSES; DEFINE_PPC_REGCLASSES
// Evaluate an expression containing condition register // Evaluate an expression containing condition register
// or condition register field symbols. Returns positive // or condition register field symbols. Returns positive
// value on success, or -1 on error. // value on success, or -1 on error.
static int64_t static int64_t
EvaluateCRExpr(const MCExpr *E) { EvaluateCRExpr(const MCExpr *E) {
switch (E->getKind()) { switch (E->getKind()) {
case MCExpr::Target: case MCExpr::Target:
▲ Show 20 Lines • Show All 245 Lines • ▼ Show 20 Lines unsigned getVSReg() const {
return (unsigned) Imm.Val; return (unsigned) Imm.Val;
} }
unsigned getACCReg() const { unsigned getACCReg() const {
assert(isACCRegNumber() && "Invalid access!"); assert(isACCRegNumber() && "Invalid access!");
return (unsigned) Imm.Val; return (unsigned) Imm.Val;
} }
unsigned getDMRROWReg() const {
assert(isDMRROWRegNumber() && "Invalid access!");
return (unsigned) Imm.Val;
}
unsigned getDMRROWpReg() const {
assert(isDMRROWpRegNumber() && "Invalid access!");
return (unsigned) Imm.Val;
}
unsigned getDMRReg() const {
assert(isDMRRegNumber() && "Invalid access!");
return (unsigned) Imm.Val;
}
unsigned getDMRpReg() const {
assert(isDMRpRegNumber() && "Invalid access!");
return (unsigned) Imm.Val;
}
unsigned getVSRpEvenReg() const { unsigned getVSRpEvenReg() const {
assert(isVSRpEvenRegNumber() && "Invalid access!"); assert(isVSRpEvenRegNumber() && "Invalid access!");
return (unsigned) Imm.Val >> 1; return (unsigned) Imm.Val >> 1;
} }
unsigned getG8pReg() const { unsigned getG8pReg() const {
assert(isEvenRegNumber() && "Invalid access!"); assert(isEvenRegNumber() && "Invalid access!");
return (unsigned)Imm.Val; return (unsigned)Imm.Val;
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines bool isS34ImmX16() const {
return Kind == Expression || return Kind == Expression ||
(Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0);
} }
bool isS34Imm() const { bool isS34Imm() const {
// Once the PC-Rel ABI is finalized, evaluate whether a 34-bit // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit
// ContextImmediate is needed. // ContextImmediate is needed.
return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); return Kind == Expression || (Kind == Immediate && isInt<34>(getImm()));
} }
amykUnsubmitted
Not Done
ReplyInline Actions

Unrelated space change?

amyk: Unrelated space change?
bool isTLSReg() const { return Kind == TLSRegister; } bool isTLSReg() const { return Kind == TLSRegister; }
bool isDirectBr() const { bool isDirectBr() const {
if (Kind == Expression) if (Kind == Expression)
return true; return true;
if (Kind != Immediate) if (Kind != Immediate)
return false; return false;
// Operand must be 64-bit aligned, signed 27-bit immediate. // Operand must be 64-bit aligned, signed 27-bit immediate.
if ((getImm() & 3) != 0) if ((getImm() & 3) != 0)
Show All 10 Linespublic:
bool isCondBr() const { return Kind == Expression || bool isCondBr() const { return Kind == Expression ||
(Kind == Immediate && isInt<16>(getImm()) && (Kind == Immediate && isInt<16>(getImm()) &&
(getImm() & 3) == 0); } (getImm() & 3) == 0); }
bool isImmZero() const { return Kind == Immediate && getImm() == 0; } bool isImmZero() const { return Kind == Immediate && getImm() == 0; }
bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
bool isACCRegNumber() const { bool isACCRegNumber() const {
return Kind == Immediate && isUInt<3>(getImm()); return Kind == Immediate && isUInt<3>(getImm());
} }
bool isDMRROWRegNumber() const {
return Kind == Immediate && isUInt<6>(getImm());
}
bool isDMRROWpRegNumber() const {
return Kind == Immediate && isUInt<5>(getImm());
}
bool isDMRRegNumber() const {
return Kind == Immediate && isUInt<3>(getImm());
}
bool isDMRpRegNumber() const {
return Kind == Immediate && isUInt<2>(getImm());
}
bool isVSRpEvenRegNumber() const { bool isVSRpEvenRegNumber() const {
return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0); return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0);
} }
bool isVSRegNumber() const { bool isVSRegNumber() const {
return Kind == Immediate && isUInt<6>(getImm()); return Kind == Immediate && isUInt<6>(getImm());
} }
bool isCCRegNumber() const { return (Kind == Expression bool isCCRegNumber() const { return (Kind == Expression
&& isUInt<3>(getExprCRVal())) || && isUInt<3>(getExprCRVal())) ||
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines void addRegSPERCOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); Inst.addOperand(MCOperand::createReg(SPERegs[getReg()]));
} }
void addRegACCRCOperands(MCInst &Inst, unsigned N) const { void addRegACCRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()])); Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()]));
} }
void addRegDMRROWRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(DMRROWRegs[getDMRROWReg()]));
}
void addRegDMRROWpRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(DMRROWpRegs[getDMRROWpReg()]));
}
void addRegDMRRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(DMRRegs[getDMRReg()]));
}
void addRegDMRpRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(DMRpRegs[getDMRpReg()]));
}
void addRegWACCRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(WACCRegs[getACCReg()]));
}
void addRegWACC_HIRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(WACC_HIRegs[getACCReg()]));
}
void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const { void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
} }
void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const { void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!"); assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
▲ Show 20 Lines • Show All 695 Lines • ▼ Show 20 Lines RegNo = FRegs[IntVal];
!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
RegNo = VSRegs[IntVal]; RegNo = VSRegs[IntVal];
} else if (Name.startswith_insensitive("v") && } else if (Name.startswith_insensitive("v") &&
!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
RegNo = VRegs[IntVal]; RegNo = VRegs[IntVal];
} else if (Name.startswith_insensitive("cr") && } else if (Name.startswith_insensitive("cr") &&
!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
RegNo = CRRegs[IntVal]; RegNo = CRRegs[IntVal];
} else if (Name.startswith_insensitive("acc") &&
!Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
RegNo = ACCRegs[IntVal];
} else if (Name.startswith_insensitive("wacc_hi") &&
!Name.substr(7).getAsInteger(10, IntVal) && IntVal < 8) {
RegNo = ACCRegs[IntVal];
} else if (Name.startswith_insensitive("wacc") &&
!Name.substr(4).getAsInteger(10, IntVal) && IntVal < 8) {
RegNo = WACCRegs[IntVal];
} else if (Name.startswith_insensitive("dmrrowp") &&
!Name.substr(7).getAsInteger(10, IntVal) && IntVal < 32) {
RegNo = DMRROWpRegs[IntVal];
} else if (Name.startswith_insensitive("dmrrow") &&
!Name.substr(6).getAsInteger(10, IntVal) && IntVal < 64) {
RegNo = DMRROWRegs[IntVal];
} else if (Name.startswith_insensitive("dmrp") &&
!Name.substr(4).getAsInteger(10, IntVal) && IntVal < 4) {
RegNo = DMRROWpRegs[IntVal];
} else if (Name.startswith_insensitive("dmr") &&
!Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
RegNo = DMRRegs[IntVal];
} else } else
return true; return true;
getParser().Lex(); getParser().Lex();
return false; return false;
} }
bool PPCAsmParser:: bool PPCAsmParser::
ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
▲ Show 20 Lines • Show All 560 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "MCTargetDesc/PPCMCTargetDesc.h" #include "MCTargetDesc/PPCMCTargetDesc.h"
#include "TargetInfo/PowerPCTargetInfo.h" #include "TargetInfo/PowerPCTargetInfo.h"
#include "llvm/MC/MCDecoderOps.h" #include "llvm/MC/MCDecoderOps.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCInst.h" #include "llvm/MC/MCInst.h"
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h" #include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Endian.h" #include "llvm/Support/Endian.h"
using namespace llvm; using namespace llvm;
DEFINE_PPC_REGCLASSES; DEFINE_PPC_REGCLASSES
#define DEBUG_TYPE "ppc-disassembler" #define DEBUG_TYPE "ppc-disassembler"
typedef MCDisassembler::DecodeStatus DecodeStatus; typedef MCDisassembler::DecodeStatus DecodeStatus;
namespace { namespace {
class PPCDisassembler : public MCDisassembler { class PPCDisassembler : public MCDisassembler {
bool IsLittleEndian; bool IsLittleEndian;
▲ Show 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
} }
static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const MCDisassembler *Decoder) { const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, ACCRegs); return decodeRegisterClass(Inst, RegNo, ACCRegs);
} }
static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, WACCRegs);
}
static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
}
// TODO: Make this function static when the register class is used by a new
// instruction.
DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
}
static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
}
static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, DMRRegs);
}
// TODO: Make this function static when the register class is used by a new
// instruction.
DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder) {
return decodeRegisterClass(Inst, RegNo, DMRpRegs);
}
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo, static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address, uint64_t Address,
const MCDisassembler *Decoder) { const MCDisassembler *Decoder) {
return decodeRegisterClass(Inst, RegNo, VSRpRegs); return decodeRegisterClass(Inst, RegNo, VSRpRegs);
} }
#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
▲ Show 20 Lines • Show All 265 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h

//===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===// //===-- PPCMCTargetDesc.h - PowerPC Target Descriptions ---------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file provides PowerPC specific target descriptions. // This file provides PowerPC specific target descriptions.
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
#define PPC_REGS0_31(X) \ #define PPC_REGS0_31(X) \
{ \ { \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \ X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
} }
#define PPC_REGS0_63(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \
X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \
X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \
X##62, X##63 \
}
#define PPC_REGS_NO0_31(Z, X) \ #define PPC_REGS_NO0_31(Z, X) \
{ \ { \
Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \ Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \ X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \ X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
} }
#define PPC_REGS_LO_HI(LO, HI) \ #define PPC_REGS_LO_HI(LO, HI) \
{ \ { \
LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \ LO##0, LO##1, LO##2, LO##3, LO##4, LO##5, LO##6, LO##7, LO##8, LO##9, \
LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \ LO##10, LO##11, LO##12, LO##13, LO##14, LO##15, LO##16, LO##17, \
LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \ LO##18, LO##19, LO##20, LO##21, LO##22, LO##23, LO##24, LO##25, \
LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \ LO##26, LO##27, LO##28, LO##29, LO##30, LO##31, HI##0, HI##1, HI##2, \
HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \ HI##3, HI##4, HI##5, HI##6, HI##7, HI##8, HI##9, HI##10, HI##11, \
HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \ HI##12, HI##13, HI##14, HI##15, HI##16, HI##17, HI##18, HI##19, \
HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \ HI##20, HI##21, HI##22, HI##23, HI##24, HI##25, HI##26, HI##27, \
HI##28, HI##29, HI##30, HI##31 \ HI##28, HI##29, HI##30, HI##31 \
} }
#define PPC_REGS0_7(X) \
{ \
X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
}
#define PPC_REGS0_3(X) \
{ \
X##0, X##1, X##2, X##3 \
}
using llvm::MCPhysReg; using llvm::MCPhysReg;
#define DEFINE_PPC_REGCLASSES \ #define DEFINE_PPC_REGCLASSES \
static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \ static const MCPhysReg RRegs[32] = PPC_REGS0_31(PPC::R); \
static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \ static const MCPhysReg XRegs[32] = PPC_REGS0_31(PPC::X); \
static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \ static const MCPhysReg FRegs[32] = PPC_REGS0_31(PPC::F); \
static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \ static const MCPhysReg VSRpRegs[32] = PPC_REGS0_31(PPC::VSRp); \
static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \ static const MCPhysReg SPERegs[32] = PPC_REGS0_31(PPC::S); \
Show All 14 Lines static const MCPhysReg CRBITRegs[32] = { \
PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \ PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, \
PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \ PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, \
PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \ PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, \
PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \ PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, \
PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \ PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, \
PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \ PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \ PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \ static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC) static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \
static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \
static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \
static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \
static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \
static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \
static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);
#endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H #endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H

llvm/lib/Target/PowerPC/PPCInstrFuture.td

  • This file was added.
//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the instructions introduced for the Future CPU.
//
//===----------------------------------------------------------------------===//
include "PPCInstrFutureMMA.td"

llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td

  • This file was added.
//===-- PPCInstrFutureMMA.td - Future Instruction Set ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the instructions introduced for the Future CPU for MMA.
//
//===----------------------------------------------------------------------===//
class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<5> XAp;
bits<5> XBp;
bits<1> P;
let Pattern = pattern;
let Inst{6-8} = AT{2-0};
let Inst{9-10} = 0;
let Inst{11-14} = XAp{3-0};
let Inst{15} = P;
let Inst{16-19} = XBp{3-0};
let Inst{20} = 0;
let Inst{21-28} = xo;
let Inst{29} = XAp{4};
let Inst{30} = XBp{4};
let Inst{31} = 0;
}
class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {
amykUnsubmitted
Not Done
ReplyInline Actions
class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
- string asmstr, list<dag> pattern>
+ string asmstr, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {

nit: Align spacing.

amyk: nit: Align spacing.
bits<3> AT;
bits<5> XBp;
bits<2> P;
let Pattern = pattern;
let Inst{6-8} = AT{2-0};
let Inst{9-14} = 0;
let Inst{15} = P{0};
let Inst{16-19} = XBp{3-0};
let Inst{20} = P{1};
let Inst{21-29} = xo;
let Inst{30} = XBp{4};
let Inst{31} = 0;
}
class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern>
: I <opcode, OOL, IOL, asmstr, NoItinerary> {
bits<3> AT;
bits<3> AB;
let Pattern = pattern;
let Inst{6-8} = AT{2-0};
let Inst{9-10} = 0;
let Inst{11-15} = o;
let Inst{16-18} = AB{2-0};
let Inst{19-20} = 0;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
let Predicates = [IsISAFuture] in {
def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
(outs vsrprc:$XAp, vsrprc:$XBp),
(ins wacc:$AT),
"dmxxextfdmr512 $AT, $XAp, $XBp, 0", []> {
let P = 0;
}
def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
(outs vsrprc:$XAp, vsrprc:$XBp),
(ins wacc_hi:$AT),
"dmxxextfdmr512 $AT, $XAp, $XBp, 1", []> {
let P = 1;
}
def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
"dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
let P = 0;
}
def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
(ins vsrprc:$XAp, vsrprc:$XBp),
"dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
let P = 1;
}
def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
(ins dmrrowp:$AT, u2imm:$P),
"dmxxextfdmr256 $AT, $XBp, $P", []>;
def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
"dmxxinstfdmr256 $AT, $XBp, $P", []>;
def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
"dmmr $AT, $AB", []>;
def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
"dmxor $AT, $AB", []>,
RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
"dmsetdmrz $AT", NoItinerary, []>;
}

llvm/lib/Target/PowerPC/PPCInstrInfo.td

Show First 20 Lines • Show All 3,272 Lines • ▼ Show 20 Lines
def crnot : OutPatFrag<(ops node:$in), def crnot : OutPatFrag<(ops node:$in),
(CRNOT $in)>; (CRNOT $in)>;
def : Pat<(not i1:$in), def : Pat<(not i1:$in),
(crnot $in)>; (crnot $in)>;
// Prefixed instructions may require access to the above defs at a later // Prefixed instructions may require access to the above defs at a later
// time so we include this after the def. // time so we include this after the def.
include "PPCInstrP10.td" include "PPCInstrP10.td"
include "PPCInstrFuture.td"
include "PPCInstrMMA.td" include "PPCInstrMMA.td"
// Patterns for arithmetic i1 operations. // Patterns for arithmetic i1 operations.
def : Pat<(add i1:$a, i1:$b), def : Pat<(add i1:$a, i1:$b),
(CRXOR $a, $b)>; (CRXOR $a, $b)>;
def : Pat<(sub i1:$a, i1:$b), def : Pat<(sub i1:$a, i1:$b),
(CRXOR $a, $b)>; (CRXOR $a, $b)>;
def : Pat<(mul i1:$a, i1:$b), def : Pat<(mul i1:$a, i1:$b),
▲ Show 20 Lines • Show All 1,853 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===// //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format suggested style edits found:

Lint: Lint: clang-format suggested style edits found:
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file contains the PowerPC implementation of the TargetRegisterInfo // This file contains the PowerPC implementation of the TargetRegisterInfo
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines switch (RegName[0]) {
case 'f': case 'f':
case 'v': case 'v':
if (RegName[1] == 's') { if (RegName[1] == 's') {
if (RegName[2] == 'p') if (RegName[2] == 'p')
return RegName + 3; return RegName + 3;
return RegName + 2; return RegName + 2;
} }
return RegName + 1; return RegName + 1;
case 'c': if (RegName[1] == 'r') return RegName + 2; case 'c':
if (RegName[1] == 'r') return RegName + 2;
break;
case 'w':
// For wacc and wacc_hi
if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
if (RegName[4] == '_')
return RegName + 7;
else
return RegName + 4;
}
break;
case 'd':
// For dmr, dmrp, dmrrow, dmrrowp
if (RegName[1] == 'm' && RegName[2] == 'r') {
if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
RegName[6] == 'p')
return RegName + 7;
else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
return RegName + 6;
else if (RegName[3] == 'p')
return RegName + 4;
else
return RegName + 3;
}
break;
} }
return RegName; return RegName;
} }
bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override { bool isNonallocatableRegisterCalleeSave(MCRegister Reg) const override {
return Reg == PPC::LR || Reg == PPC::LR8; return Reg == PPC::LR || Reg == PPC::LR8;
} }
}; };
} // end namespace llvm } // end namespace llvm
#endif #endif

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

Show First 20 Lines • Show All 440 Lines • ▼ Show 20 Linesdef G8pRC :
let AltOrders = [(add (sub G8pRC, G8p1), G8p1)]; let AltOrders = [(add (sub G8pRC, G8p1), G8p1)];
let AltOrderSelect = [{ let AltOrderSelect = [{
return MF.getSubtarget<PPCSubtarget>().is64BitELFABI(); return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}]; }];
let Size = 128; let Size = 128;
} }
include "PPCRegisterInfoMMA.td" include "PPCRegisterInfoMMA.td"
include "PPCRegisterInfoDMR.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PowerPC Operand Definitions. // PowerPC Operand Definitions.
// In the default PowerPC assembler syntax, registers are specified simply // In the default PowerPC assembler syntax, registers are specified simply
// by number, so they cannot be distinguished from immediate values (without // by number, so they cannot be distinguished from immediate values (without
// looking at the opcode). This means that the default operand matching logic // looking at the opcode). This means that the default operand matching logic
// for the asm parser does not work, and we need to specify custom matchers. // for the asm parser does not work, and we need to specify custom matchers.
▲ Show 20 Lines • Show All 551 Lines • ▼ Show 20 Lines
def acc : RegisterOperand<ACCRC> { def acc : RegisterOperand<ACCRC> {
let ParserMatchClass = PPCRegACCRCAsmOperand; let ParserMatchClass = PPCRegACCRCAsmOperand;
} }
def uacc : RegisterOperand<UACCRC> { def uacc : RegisterOperand<UACCRC> {
let ParserMatchClass = PPCRegACCRCAsmOperand; let ParserMatchClass = PPCRegACCRCAsmOperand;
} }
// DMR Register Operands
def PPCRegDMRROWRCAsmOperand : AsmOperandClass {
let Name = "RegDMRROWRC";
let PredicateMethod = "isDMRROWRegNumber";
}
def dmrrow : RegisterOperand<DMRROWRC> {
let ParserMatchClass = PPCRegDMRROWRCAsmOperand;
}
def PPCRegDMRROWpRCAsmOperand : AsmOperandClass {
let Name = "RegDMRROWpRC";
let PredicateMethod = "isDMRROWpRegNumber";
}
def dmrrowp : RegisterOperand<DMRROWpRC> {
let ParserMatchClass = PPCRegDMRROWpRCAsmOperand;
}
def wacc : RegisterOperand<WACCRC> {
let ParserMatchClass = PPCRegACCRCAsmOperand;
}
def wacc_hi : RegisterOperand<WACC_HIRC> {
let ParserMatchClass = PPCRegACCRCAsmOperand;
}
def PPCRegDMRRCAsmOperand : AsmOperandClass {
let Name = "RegDMRRC";
let PredicateMethod = "isDMRRegNumber";
}
def dmr : RegisterOperand<DMRRC> {
let ParserMatchClass = PPCRegDMRRCAsmOperand;
}
def PPCRegDMRpRCAsmOperand : AsmOperandClass {
let Name = "RegDMRpRC";
let PredicateMethod = "isDMRpRegNumber";
}
def dmrp : RegisterOperand<DMRpRC> {
let ParserMatchClass = PPCRegDMRpRCAsmOperand;
}

llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td

  • This file was added.
//===- PPCRegisterInfoDMR.td - The PowerPC Register File *- tablegen -*----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// Register info specific to Power PC Dense Math Registers(DMR).
//
// Register classes in this file are related to the Dense Math Registers (DMR).
// There are a total of 8 DMR registers numbered 0 to 7.
// The 4 different views of each DMR register.
//
// [ DMR0 ]
// | WACC0 | WACC_HI0 |
// | DMRROWp0 | DMRROWp1 | DMRROWp2 | DMRROWp3 |
// |DMRROW0|DMRROW1|DMRROW2|DMRROW3|DMRROW4|DMRROW5|DMRROW6|DMRROW7|
// [128bits|128bits|128bits|128bits|128bits|128bits|128bits|128bits]
//
// In addition to the above classes two consecutive DMR registers make a DMR
// DMR pair (DMRp) that is 2048 bits.
//===----------------------------------------------------------------------===//
let Namespace = "PPC" in {
def sub_dmrrow0 : SubRegIndex<128>;
def sub_dmrrow1 : SubRegIndex<128, 128>;
def sub_dmrrowp0 : SubRegIndex<256>;
def sub_dmrrowp1 : SubRegIndex<256, 256>;
def sub_wacc_lo : SubRegIndex<512>;
def sub_wacc_hi : SubRegIndex<512, 512>;
def sub_dmr0 : SubRegIndex<1024>;
def sub_dmr1 : SubRegIndex<1024, 1024>;
}
// A single row in a DMR register.
// There are 8 128 bit rows in each DMR register and 8 DMR registers so that
// makes 64 DMRROW registers in total.
class DMRROW<bits<6> num, string n> : PPCReg<n> {
let HWEncoding{5-0} = num;
}
// A consecutive pair of DMR row registers.
class DMRROWp<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {
let HWEncoding{4-0} = num;
let SubRegs = subregs;
}
// WACC - Wide ACC registers. Accumulator registers that are subregs of DMR.
// These ACC registers no longer include VSR regs as subregs.
class WACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
let HWEncoding{2-0} = num;
let SubRegs = subregs;
}
// High bits for the ACC registers.
// When the ACC register is used these bits are ignored.
// When the ACC register is the target, these bits are set to zero.
class WACC_HI<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
let HWEncoding{2-0} = num;
let SubRegs = subregs;
}
class DMR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
let HWEncoding{2-0} = num;
let SubRegs = subregs;
}
class DMRp<bits<2> num, string n, list<Register> subregs> : PPCReg<n> {
let HWEncoding{1-0} = num;
let SubRegs = subregs;
}
// The DMR Row type registers are the lowest level of registers and have no
// subregs.
foreach Index = 0-63 in {
def DMRROW#Index : DMRROW<Index, "dmrrow"#Index>, DwarfRegNum<[-1, -1]>;
}
// DMRROW pairs are consecutive pairs.
// DMRROWp0 = DMRROW0, DMRROW1
// DMRROWp1 = DMRROW2, DMRROW3
// DMRROWp2 = DMRROW4, DMRROW5
// etc...
let SubRegIndices = [sub_dmrrow0, sub_dmrrow1] in {
foreach Index = 0-31 in {
def DMRROWp#Index : DMRROWp<Index, "dmrrowp"#Index,
[!cast<DMRROW>("DMRROW"#!mul(Index, 2)),
!cast<DMRROW>("DMRROW"#!add(!mul(Index, 2), 1))]>, DwarfRegNum<[-1, -1]>;
}
}
let SubRegIndices = [sub_dmrrowp0, sub_dmrrowp1] in {
// WACC0 = DMRROWp0, DMRROWp1
// WACC1 = DMRROWp4, DMRROWp5
// WACC2 = DMRROWp8, DMRROWp9
// etc...
foreach Index = 0-7 in {
def WACC#Index : WACC<Index, "wacc"#Index,
[!cast<DMRROWp>("DMRROWp"#!mul(Index, 4)),
!cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 1))]>, DwarfRegNum<[-1, -1]>;
}
// WACC_HI0 = DMRROWp2, DMRROWp3
// WACC_HI1 = DMRROWp6, DMRROWp7
// WACC_HI2 = DMRROWp10, DMRROWp11
// etc...
foreach Index = 0-7 in {
def WACC_HI#Index : WACC_HI<Index, "wacc_hi"#Index,
[!cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 2)),
!cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 3))]>, DwarfRegNum<[-1, -1]>;
}
}
// DMR0 = WACC0, WACC_HI0
// DMR1 = WACC1, WACC_HI1
// DMR2 = WACC2, WACC_HI2
// etc...
let SubRegIndices = [sub_wacc_lo, sub_wacc_hi] in {
foreach Index = 0-7 in {
def DMR#Index : DMR<Index, "dmr"#Index, [!cast<WACC>("WACC"#Index), !cast<WACC_HI>("WACC_HI"#Index)]>, DwarfRegNum<[-1, -1]>;
}
}
// DMRp0 = DMR0, DMR1
// DMRp1 = DMR2, DMR3
// DMRp2 = DMR4, DMR5
// DMRp3 = DMR6, DMR7
let SubRegIndices = [sub_dmr0, sub_dmr1] in {
def DMRp0 : DMRp<0, "dmrp0", [DMR0, DMR1]>, DwarfRegNum<[-1, -1]>;
def DMRp1 : DMRp<1, "dmrp1", [DMR2, DMR3]>, DwarfRegNum<[-1, -1]>;
def DMRp2 : DMRp<2, "dmrp2", [DMR4, DMR5]>, DwarfRegNum<[-1, -1]>;
def DMRp3 : DMRp<3, "dmrp3", [DMR6, DMR7]>, DwarfRegNum<[-1, -1]>;
}
def DMRROWRC : RegisterClass<"PPC", [v128i1], 128,
(add (sequence "DMRROW%u", 0, 63))> {
let Size = 128;
}
def DMRROWpRC : RegisterClass<"PPC", [v256i1], 128,
(add (sequence "DMRROWp%u", 0, 31))> {
let Size = 256;
}
def WACCRC : RegisterClass<"PPC", [v512i1], 128,
(add (sequence "WACC%u", 0, 7))> {
let Size = 512;
}
def WACC_HIRC : RegisterClass<"PPC", [v512i1], 128,
(add (sequence "WACC_HI%u", 0, 7))> {
let Size = 512;
}
def DMRRC : RegisterClass<"PPC", [v1024i1], 128,
(add (sequence "DMR%u", 0, 7))> {
let Size = 1024;
}
def DMRpRC : RegisterClass<"PPC", [v2048i1], 128,
(add DMRp0, DMRp1, DMRp2, DMRp3)> {
let Size = 2048;
}

llvm/lib/Target/PowerPC/PPCScheduleP9.td

Show All 32 Linesdef P9Model : SchedMachineModel {
// As iops are dispatched to a slice, they are held in an independent slice // As iops are dispatched to a slice, they are held in an independent slice
// issue queue until all register sources and other dependencies have been // issue queue until all register sources and other dependencies have been
// resolved and they can be issued. Each of four execution slices has an // resolved and they can be issued. Each of four execution slices has an
// 11-entry iop issue queue. // 11-entry iop issue queue.
let MicroOpBufferSize = 44; let MicroOpBufferSize = 44;
let CompleteModel = 1; let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on // Do not support SPE (Signal Processing Engine) or prefixed instructions on
// Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions // Power 9, or MMA, or paired vector mem ops, or PC relative mem ops, or
// introduced in ISA 3.1. // instructions introduced after ISA 3.0.
let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA, let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
PairedVectorMemops,
PCRelativeMemops, IsISA3_1, IsISAFuture]; PCRelativeMemops, IsISA3_1, IsISAFuture];
} }
let SchedModel = P9Model in { let SchedModel = P9Model in {
// ***************** Processor Resources ***************** // ***************** Processor Resources *****************
// Dispatcher slots: // Dispatcher slots:
▲ Show 20 Lines • Show All 375 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/future-check-features.ll

; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \ ; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
amykUnsubmitted
Not Done
ReplyInline Actions

nit: Are these run lines too long?

amyk: nit: Are these run lines too long?
stefanpAuthorUnsubmitted
Not Done
ReplyInline Actions

nit: Are these run lines too long?

Yes, they are too long.
I actually think they were too long in the original test too but I'll fix it with this patch.

stefanp: > nit: Are these run lines too long? Yes, they are too long. I actually think they were too…
; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \ ; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ ; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
; RUN: -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
; RUN: -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() { define dso_local signext i32 @f() {
entry: entry:
ret i32 0 ret i32 0
} }
; Make sure that all of the features listed are recognized. ; Make sure that all of the features listed are recognized.
; CHECK-NOT: is not a recognized feature for this target ; CHECK-NOT: is not a recognized feature for this target
; Make sure that the test was actually compiled. ; Make sure that the test was actually compiled.
; CHECK: li r3, 0 ; CHECK: li r3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr

llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt

  • This file was added.
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
# RUN: -mcpu=future | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-aix-gnu \
# RUN: -mcpu=future | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \
# RUN: -mcpu=future | FileCheck %s
#CHECK: dmxxextfdmr512 1, 2, 34, 0
0xf0 0x82 0x17 0x12
#CHECK: dmxxextfdmr512 1, 2, 34, 1
0xf0 0x83 0x17 0x12
#CHECK: dmxxextfdmr256 3, 8, 0
0xf1 0x80 0x47 0x90
#CHECK: dmxxextfdmr256 3, 8, 3
0xf1 0x81 0x4f 0x90
#CHECK: dmxxinstfdmr512 1, 2, 34, 0
0xf0 0x82 0x17 0x52
#CHECK: dmxxinstfdmr512 1, 2, 34, 1
0xf0 0x83 0x17 0x52
#CHECK: dmxxinstfdmr256 3, 8, 0
0xf1 0x80 0x47 0x94
#CHECK: dmxxinstfdmr256 3, 8, 3
0xf1 0x81 0x4f 0x94
#CHECK: dmsetdmrz 3
0x7d 0x82 0x01 0x62
#CHECK: dmmr 4, 5
0x7e 0x06 0xa1 0x62
#CHECK: dmxor 6, 7
0x7f 0x07 0xe1 0x62

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt

  • This file was added.
# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown \
# RUN: -mcpu=future | FileCheck %s
#CHECK: dmxxextfdmr512 1, 2, 34, 0
0x12 0x17 0x82 0xf0
#CHECK: dmxxextfdmr512 1, 2, 34, 1
0x12 0x17 0x83 0xf0
#CHECK: dmxxextfdmr256 3, 8, 0
0x90 0x47 0x80 0xf1
#CHECK: dmxxextfdmr256 3, 8, 3
0x90 0x4f 0x81 0xf1
#CHECK: dmxxinstfdmr512 1, 2, 34, 0
0x52 0x17 0x82 0xf0
#CHECK: dmxxinstfdmr512 1, 2, 34, 1
0x52 0x17 0x83 0xf0
#CHECK: dmxxinstfdmr256 3, 8, 0
0x94 0x47 0x80 0xf1
#CHECK: dmxxinstfdmr256 3, 8, 3
0x94 0x4f 0x81 0xf1
#CHECK: dmsetdmrz 3
0x62 0x01 0x82 0x7d
#CHECK: dmmr 4, 5
0x62 0xa1 0x06 0x7e
#CHECK: dmxor 6, 7
0x62 0xe1 0x07 0x7f

llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s

  • This file was added.
# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-BE %s
# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-LE %s
# RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
# RUN: FileCheck -check-prefix=CHECK-BE %s
# CHECK-BE: dmxxextfdmr512 1, 2, 34, 0 # encoding: [0xf0,0x82,0x17,0x12]
# CHECK-LE: dmxxextfdmr512 1, 2, 34, 0 # encoding: [0x12,0x17,0x82,0xf0]
dmxxextfdmr512 1, 2, 34, 0
# CHECK-BE: dmxxextfdmr512 1, 2, 34, 1 # encoding: [0xf0,0x83,0x17,0x12]
# CHECK-LE: dmxxextfdmr512 1, 2, 34, 1 # encoding: [0x12,0x17,0x83,0xf0]
dmxxextfdmr512 1, 2, 34, 1
# CHECK-BE: dmxxextfdmr256 3, 8, 0 # encoding: [0xf1,0x80,0x47,0x90]
# CHECK-LE: dmxxextfdmr256 3, 8, 0 # encoding: [0x90,0x47,0x80,0xf1]
dmxxextfdmr256 3, 8, 0
# CHECK-BE: dmxxextfdmr256 3, 8, 3 # encoding: [0xf1,0x81,0x4f,0x90]
# CHECK-LE: dmxxextfdmr256 3, 8, 3 # encoding: [0x90,0x4f,0x81,0xf1]
dmxxextfdmr256 3, 8, 3
# CHECK-BE: dmxxinstfdmr512 1, 2, 34, 0 # encoding: [0xf0,0x82,0x17,0x52]
# CHECK-LE: dmxxinstfdmr512 1, 2, 34, 0 # encoding: [0x52,0x17,0x82,0xf0]
dmxxinstfdmr512 1, 2, 34, 0
# CHECK-BE: dmxxinstfdmr512 1, 2, 34, 1 # encoding: [0xf0,0x83,0x17,0x52]
# CHECK-LE: dmxxinstfdmr512 1, 2, 34, 1 # encoding: [0x52,0x17,0x83,0xf0]
dmxxinstfdmr512 1, 2, 34, 1
# CHECK-BE: dmxxinstfdmr256 3, 8, 0 # encoding: [0xf1,0x80,0x47,0x94]
# CHECK-LE: dmxxinstfdmr256 3, 8, 0 # encoding: [0x94,0x47,0x80,0xf1]
dmxxinstfdmr256 3, 8, 0
# CHECK-BE: dmxxinstfdmr256 3, 8, 3 # encoding: [0xf1,0x81,0x4f,0x94]
# CHECK-LE: dmxxinstfdmr256 3, 8, 3 # encoding: [0x94,0x4f,0x81,0xf1]
dmxxinstfdmr256 3, 8, 3
# CHECK-BE: dmsetdmrz 3 # encoding: [0x7d,0x82,0x01,0x62]
# CHECK-LE: dmsetdmrz 3 # encoding: [0x62,0x01,0x82,0x7d]
dmsetdmrz 3
# CHECK-BE: dmmr 4, 5 # encoding: [0x7e,0x06,0xa1,0x62]
# CHECK-LE: dmmr 4, 5 # encoding: [0x62,0xa1,0x06,0x7e]
dmmr 4, 5
# CHECK-BE: dmxor 6, 7 # encoding: [0x7f,0x07,0xe1,0x62]
# CHECK-LE: dmxor 6, 7 # encoding: [0x62,0xe1,0x07,0x7f]
dmxor 6, 7

llvm/utils/TableGen/CodeGenTarget.cpp

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 LinesStringRef llvm::getEnumName(MVT::SimpleValueType T) {
case MVT::v8i1: return "MVT::v8i1"; case MVT::v8i1: return "MVT::v8i1";
case MVT::v16i1: return "MVT::v16i1"; case MVT::v16i1: return "MVT::v16i1";
case MVT::v32i1: return "MVT::v32i1"; case MVT::v32i1: return "MVT::v32i1";
case MVT::v64i1: return "MVT::v64i1"; case MVT::v64i1: return "MVT::v64i1";
case MVT::v128i1: return "MVT::v128i1"; case MVT::v128i1: return "MVT::v128i1";
case MVT::v256i1: return "MVT::v256i1"; case MVT::v256i1: return "MVT::v256i1";
case MVT::v512i1: return "MVT::v512i1"; case MVT::v512i1: return "MVT::v512i1";
case MVT::v1024i1: return "MVT::v1024i1"; case MVT::v1024i1: return "MVT::v1024i1";
case MVT::v2048i1: return "MVT::v2048i1";
case MVT::v128i2: return "MVT::v128i2"; case MVT::v128i2: return "MVT::v128i2";
case MVT::v256i2: return "MVT::v256i2"; case MVT::v256i2: return "MVT::v256i2";
case MVT::v64i4: return "MVT::v64i4"; case MVT::v64i4: return "MVT::v64i4";
case MVT::v128i4: return "MVT::v128i4"; case MVT::v128i4: return "MVT::v128i4";
case MVT::v1i8: return "MVT::v1i8"; case MVT::v1i8: return "MVT::v1i8";
case MVT::v2i8: return "MVT::v2i8"; case MVT::v2i8: return "MVT::v2i8";
case MVT::v4i8: return "MVT::v4i8"; case MVT::v4i8: return "MVT::v4i8";
case MVT::v8i8: return "MVT::v8i8"; case MVT::v8i8: return "MVT::v8i8";
▲ Show 20 Lines • Show All 846 Lines • Show Last 20 Lines