[PowerPC] Add new load/store with length instructions to Future CPU.

[maryammo]

Summary

This patch adds 8 news load and store with length instructions including
lxvrl, lxvrll, stxvrl, stxvrll, lxvprl, lxvprll, stxvprl, stxvprll.

[stefanp]

Other than a very minor nit I think this LGTM.

Please note that since https://reviews.llvm.org/D136366 has gone in I suspect you will have to rebase your patch to the top of main branch before you deliver this change.

llvm/lib/Target/PowerPC/PPCInstrFuture.td

16

nit:
I think alignment is 1 space off here. (and on line 19).

[amyk]

Nit: Please also rebase this patch as the newly added files have been committed in Stefan's patch: rG9df924a634ac5ea702b0d8d0d8b737c819a98095

llvm/lib/Target/PowerPC/PPCInstrFuture.td

14

I might be mistaken but I think we may need a let mayLoad = 1 in { } for the loads and a let mayStore = 1 in { } for the stores.

16

Minor nit on indenting.

19

Minor nit on indenting.

[lei]

llvm/lib/Target/PowerPC/PPCInstrFuture.td

14

I second that. We should add it for load and stores instrs.

llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s

6

run line for powerpc64-unknown-aix-gnu?

[saghir]

Besides other comments, LGTM. Thanks!

[maryammo]

Rebased patch to top of main branch and address the review comments

[amyk]

Thanks for addressing the initial comments that I had. I think aside from these comments I have, the patch LGTM.

llvm/lib/Target/PowerPC/PPCInstrFuture.td

15

Another minor nit, but could we:

• Indent the let mayLoad = 1 in { } and let mayStore = 1 in { } blocks, similar to how in PPCInstrVSX.td, we will indent these mayLoad/mayStore blocks if there are predicates on the outside.
• Group all loads together in one mayLoad block, and stores in one mayStore block so that we don't need to add as many of these?

[maryammo]

Address review comments and rebase patch to top of main branch

[amyk]

Thanks Maryam. LGTM.

llvm/lib/Target/PowerPC/PPCInstrFuture.td

 //===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the instructions introduced for the Future CPU.
 //
 //===----------------------------------------------------------------------===//
 
 class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
                       string asmstr, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, NoItinerary> {
   bits<5> RT;
   bits<5> RA;
   bits<5> RB;
   bit L;
 
   let Pattern = pattern;
 
   bit RC = 0;    // set by isRecordForm
 
   let Inst{6-10}  = RT;
   let Inst{11-15} = RA;

 }
 
 let Predicates = [IsISAFuture] in {
 defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
                                (ins g8rc:$RA, g8rc:$RB, u1imm:$L),
                                "subfus",  "$RT, $L, $RA, $RB", []>;
 }
 
+let Predicates = [HasVSX, IsISAFuture] in {
+  let mayLoad = 1 in {
+    def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
+                              "lxvrl $XT, $src, $rB", IIC_LdStLoad, []>;
+
+    def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
+                           "lxvrll $XT, $src, $rB", IIC_LdStLoad, []>;
+
+    def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
+                                 (ins memr:$src, g8rc:$rB),
+                                 "lxvprl $XTp, $src, $rB", IIC_LdStLFD, []>;
+
+    def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
+                                  (ins memr:$src, g8rc:$rB),
+                                  "lxvprll $XTp, $src, $rB", IIC_LdStLFD, []>;
+  }
+
+  let mayStore = 1 in {
+    def STXVRL : XX1Form_memOp<31, 653, (outs),
+                               (ins vsrc:$XT, memr:$dst, g8rc:$rB),
+                               "stxvrl $XT, $dst, $rB", IIC_LdStLoad, []>;
+
+    def STXVRLL : XX1Form_memOp<31, 685, (outs),
+                                (ins vsrc:$XT, memr:$dst, g8rc:$rB),
+                                "stxvrll $XT, $dst, $rB", IIC_LdStLoad, []>;
+
+    def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
+                                  (ins vsrprc:$XTp, memr:$src, g8rc:$rB),
+                                  "stxvprl $XTp, $src, $rB", IIC_LdStLFD, []>;
+
+    def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
+                                   (ins vsrprc:$XTp, memr:$src, g8rc:$rB),
+                                   "stxvprll $XTp, $src, $rB", IIC_LdStLFD, []>;
+  }
+}

llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt

 #CHECK: subfus 3, 1, 4, 5
 0x7c 0x64 0x2c 0x90
 
 #CHECK: subfus. 3, 0, 4, 5
 0x7c 0x64 0x28 0x91
 
 #CHECK: subfus. 3, 1, 4, 5
 0x7c 0x64 0x2c 0x91
+
+#CHECK: lxvrl 1, 1, 2
+0x7c 0x21 0x14 0x1a
+
+#CHECK: lxvrll 0, 3, 4
+0x7c 0x03 0x24 0x5a
+
+#CHECK: stxvrl 2, 0, 1
+0x7c 0x40 0x0d 0x1a
+
+#CHECK: stxvrll 3, 1, 5
+0x7c 0x61 0x2d 0x5a
+
+#CHECK: lxvprl 6, 1, 5
+0x7c 0xc1 0x2c 0x9a
+
+#CHECK: lxvprll 6, 2, 1
+0x7c 0xc2 0x0c 0xda
+
+#CHECK: stxvprl 0, 1, 2
+0x7c 0x01 0x15 0x9a
+
+#CHECK: stxvprll 6, 0, 1
+0x7c 0xc0 0x0d 0xda

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt

 #CHECK: subfus 3, 1, 4, 5
 0x90 0x2c 0x64 0x7c
 
 #CHECK: subfus. 3, 0, 4, 5
 0x91 0x28 0x64 0x7c
 
 #CHECK: subfus. 3, 1, 4, 5
 0x91 0x2c 0x64 0x7c
+
+#CHECK: lxvrl 1, 1, 2
+0x1a 0x14 0x21 0x7c
+
+#CHECK: lxvrll 0, 3, 4
+0x5a 0x24 0x03 0x7c
+
+#CHECK: stxvrl 2, 0, 1
+0x1a 0x0d 0x40 0x7c
+
+#CHECK: stxvrll 3, 1, 5
+0x5a 0x2d 0x61 0x7c
+
+#CHECK: lxvprl 6, 1, 5
+0x9a 0x2c 0xc1 0x7c
+
+#CHECK: lxvprll 6, 2, 1
+0xda 0x0c 0xc2 0x7c
+
+#CHECK: stxvprl 0, 1, 2
+0x9a 0x15 0x01 0x7c
+
+#CHECK: stxvprll 6, 0, 1
+0xda 0x0d 0xc0 0x7c

llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s

 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | \
 # RUN:   FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | \
 # RUN:   FileCheck -check-prefix=CHECK-LE %s
 # RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
 # RUN:   FileCheck -check-prefix=CHECK-BE %s
 
 # CHECK-BE: dmxxextfdmr512 1, 2, 34, 0    # encoding: [0xf0,0x82,0x17,0x12]
 # CHECK-LE: dmxxextfdmr512 1, 2, 34, 0    # encoding: [0x12,0x17,0x82,0xf0]
             dmxxextfdmr512 1, 2, 34, 0
 
 # CHECK-BE: dmxxextfdmr512 1, 2, 34, 1    # encoding: [0xf0,0x83,0x17,0x12]
 # CHECK-LE: dmxxextfdmr512 1, 2, 34, 1    # encoding: [0x12,0x17,0x83,0xf0]
             dmxxextfdmr512 1, 2, 34, 1

 
 # CHECK-BE: subfus. 3, 0, 4, 5         # encoding: [0x7c,0x64,0x28,0x91]
 # CHECK-LE: subfus. 3, 0, 4, 5         # encoding: [0x91,0x28,0x64,0x7c]
             subfus. 3, 0, 4, 5
 
 # CHECK-BE: subfus. 3, 1, 4, 5         # encoding: [0x7c,0x64,0x2c,0x91]
 # CHECK-LE: subfus. 3, 1, 4, 5         # encoding: [0x91,0x2c,0x64,0x7c]
             subfus. 3, 1, 4, 5
+
+# CHECK-BE: lxvrl 1, 1, 2                 # encoding: [0x7c,0x21,0x14,0x1a]
+# CHECK-LE: lxvrl 1, 1, 2                 # encoding: [0x1a,0x14,0x21,0x7c]
+            lxvrl 1, 1, 2
+
+# CHECK-BE: lxvrll 0, 3, 4                # encoding: [0x7c,0x03,0x24,0x5a]
+# CHECK-LE: lxvrll 0, 3, 4                # encoding: [0x5a,0x24,0x03,0x7c]
+            lxvrll 0, 3, 4
+
+# CHECK-BE: stxvrl 2, 0, 1                # encoding: [0x7c,0x40,0x0d,0x1a]
+# CHECK-LE: stxvrl 2, 0, 1                # encoding: [0x1a,0x0d,0x40,0x7c]
+            stxvrl 2, 0, 1
+
+# CHECK-BE: stxvrll 3, 1, 5               # encoding: [0x7c,0x61,0x2d,0x5a]
+# CHECK-LE: stxvrll 3, 1, 5               # encoding: [0x5a,0x2d,0x61,0x7c]
+            stxvrll 3, 1, 5
+
+# CHECK-BE: lxvprl 6, 1, 5                # encoding: [0x7c,0xc1,0x2c,0x9a]
+# CHECK-LE: lxvprl 6, 1, 5                # encoding: [0x9a,0x2c,0xc1,0x7c]
+            lxvprl 6, 1, 5
+
+# CHECK-BE: lxvprll 6, 2, 1               # encoding: [0x7c,0xc2,0x0c,0xda]
+# CHECK-LE: lxvprll 6, 2, 1               # encoding: [0xda,0x0c,0xc2,0x7c]
+            lxvprll 6, 2, 1
+
+# CHECK-BE: stxvprl 0, 1, 2               # encoding: [0x7c,0x01,0x15,0x9a]
+# CHECK-LE: stxvprl 0, 1, 2               # encoding: [0x9a,0x15,0x01,0x7c]
+            stxvprl 0, 1, 2
+
+# CHECK-BE: stxvprll 6, 0, 1              # encoding: [0x7c,0xc0,0x0d,0xda]
+# CHECK-LE: stxvprll 6, 0, 1              # encoding: [0xda,0x0d,0xc0,0x7c]
+            stxvprll 6, 0, 1