[RISCV] Add a LocalStackSlotAllocation test

[jrtc27]

llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll

1–2

RV32? update_llc_test_checks.py?

[StephenFan]

Add RV32 run line.

[craig.topper]

LGTM

llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll

+
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+
+; This test case test the LocalStackSlotAllocation pass that use a base register 
+; for the frame index that its offset is out-of-range (for RISC-V. the immediate
+; is 12 bits for the load store instruction (excludes vector load / store))
+; TODO: Enable LocalStackSlotAllocation pass.
+define void @use_frame_base_reg() {
+; CHECK-LABEL: use_frame_base_reg
+; CHECK:       # %bb.0
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1712
+; CHECK-NEXT:     sub sp, sp, a0
+; CHECK-NEXT:     .cfi_def_cfa_offset 100016
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1708
+; CHECK-NEXT:     add a0, sp, a0
+; CHECK-NEXT:     lb a0, 0(a0)
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1704
+; CHECK-NEXT:     add a0, sp, a0
+; CHECK-NEXT:     lb a0, 0(a0)
+; CHECK-NEXT:     lui a0, 24
+; CHECK-NEXT:     addiw a0, a0, 1712
+; CHECK-NEXT:     add sp, sp, a0
+; CHECK-NEXT:     ret
+  %va = alloca i8, align 4
+  %va1 = alloca i8, align 4
+  %large = alloca [ 100000 x i8 ]
+  %argp.cur = load volatile i8, i8* %va, align 4
+  %argp.next = load volatile i8, i8* %va1, align 4
+  ret void
+}