[LLDB] Move MIPS64/PPC64 and misc. to optional GetRegisterInfo

[DavidSpickett]

Summary

Depends on D134536

[DavidSpickett]

Remove stray newline in riscv.

lldb/source/Core/EmulateInstruction.cpp

 //===-- EmulateInstruction.cpp --------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
bool EmulateInstruction::ReadRegister(const RegisterInfo *reg_info,
   if (m_read_reg_callback != nullptr)
     return m_read_reg_callback(this, m_baton, reg_info, reg_value);
   return false;
 }
 
 bool EmulateInstruction::ReadRegister(lldb::RegisterKind reg_kind,
                                       uint32_t reg_num,
                                       RegisterValue &reg_value) {
-  RegisterInfo reg_info;
-  if (GetRegisterInfo(reg_kind, reg_num, reg_info))
-    return ReadRegister(&reg_info, reg_value);
+  llvm::Optional<RegisterInfo> reg_info = GetRegisterInfo(reg_kind, reg_num);
+  if (reg_info)
+    return ReadRegister(&(*reg_info), reg_value);
   return false;
 }
 
 uint64_t EmulateInstruction::ReadRegisterUnsigned(lldb::RegisterKind reg_kind,
                                                   uint32_t reg_num,
                                                   uint64_t fail_value,
                                                   bool *success_ptr) {
   RegisterValue reg_value;
if (m_write_reg_callback != nullptr)
     return m_write_reg_callback(this, m_baton, context, reg_info, reg_value);
   return false;
 }
 
 bool EmulateInstruction::WriteRegister(const Context &context,
                                        lldb::RegisterKind reg_kind,
                                        uint32_t reg_num,
                                        const RegisterValue &reg_value) {
-  RegisterInfo reg_info;
-  if (GetRegisterInfo(reg_kind, reg_num, reg_info))
-    return WriteRegister(context, &reg_info, reg_value);
+  llvm::Optional<RegisterInfo> reg_info = GetRegisterInfo(reg_kind, reg_num);
+  if (reg_info)
+    return WriteRegister(context, &(*reg_info), reg_value);
   return false;
 }
 
 bool EmulateInstruction::WriteRegisterUnsigned(const Context &context,
                                                lldb::RegisterKind reg_kind,
                                                uint32_t reg_num,
                                                uint64_t uint_value) {
-  RegisterInfo reg_info;
-  if (GetRegisterInfo(reg_kind, reg_num, reg_info)) {
+  llvm::Optional<RegisterInfo> reg_info = GetRegisterInfo(reg_kind, reg_num);
+  if (reg_info) {
     RegisterValue reg_value;
-    if (reg_value.SetUInt(uint_value, reg_info.byte_size))
-      return WriteRegister(context, &reg_info, reg_value);
+    if (reg_value.SetUInt(uint_value, reg_info->byte_size))
+      return WriteRegister(context, &(*reg_info), reg_value);
   }
   return false;
 }
 
 bool EmulateInstruction::WriteRegisterUnsigned(const Context &context,
                                                const RegisterInfo *reg_info,
                                                uint64_t uint_value) {
   if (reg_info != nullptr) {

 bool EmulateInstruction::GetRegisterInfo(lldb::RegisterKind reg_kind,
                                          uint32_t reg_num,
                                          RegisterInfo &reg_info) {
   llvm::Optional<RegisterInfo> info = GetRegisterInfo(reg_kind, reg_num);
   if (info)
     reg_info = *info;
   return info.has_value();
 }
 No newline at end of file

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

 //===-- EmulateInstructionMIPS64.cpp --------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
if (dst == dwarf_sp_mips64) {
        * operation is 64-bit modulo arithmetic that does not trap on overflow.
        * It is appropriate for arithmetic which is not signed, such as address
        * arithmetic, or integer arithmetic environments that ignore overflow,
        * such as “C” language arithmetic.
        *
        * Assume 2's complement and rely on unsigned overflow here.
        */
       uint64_t result = src_opd_val + imm;
-      RegisterInfo reg_info_sp;
-
-      if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
-        context.SetRegisterPlusOffset(reg_info_sp, imm);
+      llvm::Optional<RegisterInfo> reg_info_sp =
+          GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64);
+      if (reg_info_sp)
+        context.SetRegisterPlusOffset(*reg_info_sp, imm);
 
       /* We are allocating bytes on stack */
       context.type = eContextAdjustStackPointer;
 
       WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips64,
                             result);
       return true;
     }
 
     imm += src_opd_val;
     context.SetImmediateSigned(imm);
     context.type = eContextImmediate;
 
     if (!WriteRegisterUnsigned(context, eRegisterKindDWARF,
                                dwarf_zero_mips64 + dst, imm))
       return false;
   }
 
   return true;
 }
 
 bool EmulateInstructionMIPS64::Emulate_SD(llvm::MCInst &insn) {
   uint64_t address;
-  RegisterInfo reg_info_base;
-  RegisterInfo reg_info_src;
   bool success = false;
   uint32_t imm16 = insn.getOperand(2).getImm();
   uint64_t imm = SignedBits(imm16, 15, 0);
   uint32_t src, base;
   Context bad_vaddr_context;
 
   src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
   base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
 
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base,
-                       reg_info_base) ||
-      !GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src,
-                       reg_info_src))
+  llvm::Optional<RegisterInfo> reg_info_base =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base);
+  llvm::Optional<RegisterInfo> reg_info_src =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src);
+  if (!reg_info_base || !reg_info_src)
     return false;
 
   /* read SP */
   address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + base,
                                  0, &success);
   if (!success)
     return false;
 
   /* destination address */
   address = address + imm;
 
   /* We look for sp based non-volatile register stores */
   if (nonvolatile_reg_p(src)) {
     Context context;
     RegisterValue data_src;
     context.type = eContextPushRegisterOnStack;
-    context.SetRegisterToRegisterPlusOffset(reg_info_src, reg_info_base, 0);
+    context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
 
     uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
     Status error;
 
-    if (!ReadRegister(&reg_info_base, data_src))
+    if (!ReadRegister(&(*reg_info_base), data_src))
       return false;
 
-    if (data_src.GetAsMemoryData(&reg_info_src, buffer, reg_info_src.byte_size,
-                                 eByteOrderLittle, error) == 0)
+    if (data_src.GetAsMemoryData(&(*reg_info_src), buffer,
+                                 reg_info_src->byte_size, eByteOrderLittle,
+                                 error) == 0)
       return false;
 
-    if (!WriteMemory(context, address, buffer, reg_info_src.byte_size))
+    if (!WriteMemory(context, address, buffer, reg_info_src->byte_size))
       return false;
   }
 
   /* Set the bad_vaddr register with base address used in the instruction */
   bad_vaddr_context.type = eContextInvalid;
   WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64,
                         address);
 
   return true;
 }
 
 bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
   bool success = false;
   uint32_t src, base;
   int64_t imm, address;
   Context bad_vaddr_context;
 
   src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
   base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
   imm = insn.getOperand(2).getImm();
 
-  RegisterInfo reg_info_base;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base,
-                       reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + base))
     return false;
 
   /* read base register */
   address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips64 + base,
                                  0, &success);
   if (!success)
     return false;
 
   /* destination address */
   address = address + imm;
 
   /* Set the bad_vaddr register with base address used in the instruction */
   bad_vaddr_context.type = eContextInvalid;
   WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips64,
                         address);
 
   if (nonvolatile_reg_p(src)) {
     RegisterValue data_src;
-    RegisterInfo reg_info_src;
-
-    if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src,
-                         reg_info_src))
+    llvm::Optional<RegisterInfo> reg_info_src =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips64 + src);
+    if (!reg_info_src)
       return false;
 
     Context context;
     context.type = eContextRegisterLoad;
 
-    return WriteRegister(context, &reg_info_src, data_src);
+    return WriteRegister(context, &(*reg_info_src), data_src);
   }
 
   return false;
 }
 
 bool EmulateInstructionMIPS64::Emulate_LUI(llvm::MCInst &insn) {
   // LUI rt, immediate
   // GPR[rt] <- sign_extend(immediate << 16)
if (dst == dwarf_sp_mips64) {
 
     if (op_name.equals_insensitive("DSUBU") ||
         op_name.equals_insensitive("SUBU"))
       result = src_opd_val - rt_opd_val;
     else
       result = src_opd_val + rt_opd_val;
 
     Context context;
-    RegisterInfo reg_info_sp;
-    if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64, reg_info_sp))
-      context.SetRegisterPlusOffset(reg_info_sp, rt_opd_val);
+    llvm::Optional<RegisterInfo> reg_info_sp =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips64);
+    if (reg_info_sp)
+      context.SetRegisterPlusOffset(*reg_info_sp, rt_opd_val);
 
     /* We are allocating bytes on stack */
     context.type = eContextAdjustStackPointer;
 
     WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips64, result);
 
     return true;
   } else if (src == dwarf_sp_mips64) {
bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) {
   int64_t imm, address;
   Context bad_vaddr_context;
 
   uint32_t num_operands = insn.getNumOperands();
   base =
       m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
   imm = insn.getOperand(num_operands - 1).getImm();
 
-  RegisterInfo reg_info_base;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
     return false;
 
   /* read base register */
   address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + base, 0,
                                  &success);
   if (!success)
     return false;
 
bool EmulateInstructionMIPS64::Emulate_LDST_Reg(llvm::MCInst &insn) {
   Context bad_vaddr_context;
 
   uint32_t num_operands = insn.getNumOperands();
   base =
       m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
   index =
       m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());
 
-  RegisterInfo reg_info_base, reg_info_index;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
     return false;
 
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index,
-                       reg_info_index))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index))
     return false;
 
   /* read base register */
   address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + base, 0,
                                  &success);
   if (!success)
     return false;
 

lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp

 //===-- EmulateInstructionPPC64.cpp ---------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
bool EmulateInstructionPPC64::EmulateLD(uint32_t opcode) {
   // For now, tracking only loads from 0(r1) to r1 (0(r1) is the ABI defined
   // location to save previous SP)
   if (ra != gpr_r1_ppc64le || rt != gpr_r1_ppc64le || ids != 0)
     return false;
 
   Log *log = GetLog(LLDBLog::Unwind);
   LLDB_LOG(log, "EmulateLD: {0:X+8}: ld r{1}, {2}(r{3})", m_addr, rt, ids, ra);
 
-  RegisterInfo r1_info;
-  if (!GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le, r1_info))
+  llvm::Optional<RegisterInfo> r1_info =
+      GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le);
+  if (!r1_info)
     return false;
 
   // restore SP
   Context ctx;
   ctx.type = eContextRestoreStackPointer;
-  ctx.SetRegisterToRegisterPlusOffset(r1_info, r1_info, 0);
+  ctx.SetRegisterToRegisterPlusOffset(*r1_info, *r1_info, 0);
 
   WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_ppc64le, 0);
   LLDB_LOG(log, "EmulateLD: success!");
   return true;
 }
 
 bool EmulateInstructionPPC64::EmulateSTD(uint32_t opcode) {
   uint32_t rs = Bits32(opcode, 25, 21);
if (rs == gpr_r0_ppc64le) {
     uint64_t lr =
         ReadRegisterUnsigned(eRegisterKindLLDB, gpr_lr_ppc64le, 0, &success);
     if (!success || lr != rs_val)
       return false;
     rs_num = gpr_lr_ppc64le;
   }
 
   // set context
-  RegisterInfo rs_info;
-  if (!GetRegisterInfo(eRegisterKindLLDB, rs_num, rs_info))
+  llvm::Optional<RegisterInfo> rs_info =
+      GetRegisterInfo(eRegisterKindLLDB, rs_num);
+  if (!rs_info)
     return false;
-  RegisterInfo ra_info;
-  if (!GetRegisterInfo(eRegisterKindLLDB, ra, ra_info))
+  llvm::Optional<RegisterInfo> ra_info = GetRegisterInfo(eRegisterKindLLDB, ra);
+  if (!ra_info)
     return false;
 
   Context ctx;
   ctx.type = eContextPushRegisterOnStack;
-  ctx.SetRegisterToRegisterPlusOffset(rs_info, ra_info, ids);
+  ctx.SetRegisterToRegisterPlusOffset(*rs_info, *ra_info, ids);
 
   // store
   uint64_t ra_val = ReadRegisterUnsigned(eRegisterKindLLDB, ra, 0, &success);
   if (!success)
     return false;
 
   lldb::addr_t addr = ra_val + ids;
   WriteMemory(ctx, addr, &rs_val, sizeof(rs_val));
bool EmulateInstructionPPC64::EmulateOR(uint32_t opcode) {
   if (m_fp != LLDB_INVALID_REGNUM || rs != rb ||
       (ra != gpr_r30_ppc64le && ra != gpr_r31_ppc64le) || rb != gpr_r1_ppc64le)
     return false;
 
   Log *log = GetLog(LLDBLog::Unwind);
   LLDB_LOG(log, "EmulateOR: {0:X+8}: mr r{1}, r{2}", m_addr, ra, rb);
 
   // set context
-  RegisterInfo ra_info;
-  if (!GetRegisterInfo(eRegisterKindLLDB, ra, ra_info))
+  llvm::Optional<RegisterInfo> ra_info = GetRegisterInfo(eRegisterKindLLDB, ra);
+  if (!ra_info)
     return false;
 
   Context ctx;
   ctx.type = eContextSetFramePointer;
-  ctx.SetRegister(ra_info);
+  ctx.SetRegister(*ra_info);
 
   // move
   bool success;
   uint64_t rb_val = ReadRegisterUnsigned(eRegisterKindLLDB, rb, 0, &success);
   if (!success)
     return false;
   WriteRegisterUnsigned(ctx, eRegisterKindLLDB, ra, rb_val);
   m_fp = ra;
bool EmulateInstructionPPC64::EmulateADDI(uint32_t opcode) {
   if (rt != gpr_r1_ppc64le || ra != gpr_r1_ppc64le)
     return false;
 
   int32_t si_val = llvm::SignExtend32<16>(si);
   Log *log = GetLog(LLDBLog::Unwind);
   LLDB_LOG(log, "EmulateADDI: {0:X+8}: addi r1, r1, {1}", m_addr, si_val);
 
   // set context
-  RegisterInfo r1_info;
-  if (!GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le, r1_info))
+  llvm::Optional<RegisterInfo> r1_info =
+      GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le);
+  if (!r1_info)
     return false;
 
   Context ctx;
   ctx.type = eContextRestoreStackPointer;
-  ctx.SetRegisterToRegisterPlusOffset(r1_info, r1_info, 0);
+  ctx.SetRegisterToRegisterPlusOffset(*r1_info, *r1_info, 0);
 
   // adjust SP
   bool success;
   uint64_t r1 =
       ReadRegisterUnsigned(eRegisterKindLLDB, gpr_r1_ppc64le, 0, &success);
   if (!success)
     return false;
   WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_ppc64le, r1 + si_val);
   LLDB_LOG(log, "EmulateADDI: success!");
   return true;
 }

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

 //===-- EmulateInstructionRISCV.cpp ---------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
EmulateInstructionRISCV::GetRegisterInfo(lldb::RegisterKind reg_kind,
 
   const RegisterInfo *array =
       RegisterInfoPOSIX_riscv64::GetRegisterInfoPtr(m_arch);
   const uint32_t length =
       RegisterInfoPOSIX_riscv64::GetRegisterInfoCount(m_arch);
 
   if (reg_index >= length || reg_kind != eRegisterKindLLDB)
     return {};
-
   return array[reg_index];
 }
 
 bool EmulateInstructionRISCV::SetTargetTriple(const ArchSpec &arch) {
   return SupportsThisArch(arch);
 }
 
 bool EmulateInstructionRISCV::TestEmulation(Stream *out_stream, ArchSpec &arch,

lldb/source/Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.cpp

 //===-- UnwindAssemblyInstEmulation.cpp -----------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
if (disasm_sp) {
 
       m_range_ptr = ⦥
       m_unwind_plan_ptr = &unwind_plan;
 
       const uint32_t addr_byte_size = m_arch.GetAddressByteSize();
       const bool show_address = true;
       const bool show_bytes = true;
       const bool show_control_flow_kind = true;
-      m_inst_emulator_up->GetRegisterInfo(unwind_plan.GetRegisterKind(),
-                                          unwind_plan.GetInitialCFARegister(),
-                                          m_cfa_reg_info);
-
+      m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+          unwind_plan.GetRegisterKind(), unwind_plan.GetInitialCFARegister());
       m_fp_is_cfa = false;
       m_register_values.clear();
       m_pushed_regs.clear();
 
       // Initialize the CFA with a known value. In the 32 bit case it will be
       // 0x80000000, and in the 64 bit case 0x8000000000000000. We use the
       // address byte size to be safe for any future address sizes
       m_initial_sp = (1ull << ((addr_byte_size * 8) - 1));
if (disasm_sp) {
         m_curr_row.reset(newrow);
 
         // Add the initial state to the save list with offset 0.
         saved_unwind_states.insert({0, {last_row, m_register_values}});
 
         // cache the stack pointer register number (in whatever register
         // numbering this UnwindPlan uses) for quick reference during
         // instruction parsing.
-        RegisterInfo sp_reg_info;
-        m_inst_emulator_up->GetRegisterInfo(
-            eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP, sp_reg_info);
+        RegisterInfo sp_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+            eRegisterKindGeneric, LLDB_REGNUM_GENERIC_SP);
 
         // The architecture dependent condition code of the last processed
         // instruction.
         EmulateInstruction::InstructionCondition last_condition =
             EmulateInstruction::UnconditionalCondition;
         lldb::addr_t condition_block_start_offset = 0;
 
         for (size_t idx = 0; idx < num_instructions; ++idx) {
if (disasm_sp) {
               // new m_curr_row.
               if (sp_reg_info.name &&
                   m_curr_row->GetCFAValue().IsRegisterPlusOffset()) {
                 uint32_t row_cfa_regnum =
                     m_curr_row->GetCFAValue().GetRegisterNumber();
                 lldb::RegisterKind row_kind =
                     m_unwind_plan_ptr->GetRegisterKind();
                 // set m_cfa_reg_info to the row's CFA reg.
-                m_inst_emulator_up->GetRegisterInfo(row_kind, row_cfa_regnum,
-                                                    m_cfa_reg_info);
+                m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+                    row_kind, row_cfa_regnum);
                 // set m_fp_is_cfa.
                 if (sp_reg_info.kinds[row_kind] == row_cfa_regnum)
                   m_fp_is_cfa = false;
                 else
                   m_fp_is_cfa = true;
               }
             }
 
if (disasm_sp) {
                 // new m_curr_row.
                 if (sp_reg_info.name &&
                     m_curr_row->GetCFAValue().IsRegisterPlusOffset()) {
                   uint32_t row_cfa_regnum =
                       m_curr_row->GetCFAValue().GetRegisterNumber();
                   lldb::RegisterKind row_kind =
                       m_unwind_plan_ptr->GetRegisterKind();
                   // set m_cfa_reg_info to the row's CFA reg.
-                  m_inst_emulator_up->GetRegisterInfo(row_kind, row_cfa_regnum,
-                                                      m_cfa_reg_info);
+                  m_cfa_reg_info = *m_inst_emulator_up->GetRegisterInfo(
+                      row_kind, row_cfa_regnum);
                   // set m_fp_is_cfa.
                   if (sp_reg_info.kinds[row_kind] == row_cfa_regnum)
                     m_fp_is_cfa = false;
                   else
                     m_fp_is_cfa = true;
                 }
                 bool replace_existing =
                     true; // The last instruction might already
if (reg_num != LLDB_INVALID_REGNUM &&
           m_curr_row->SetRegisterLocationToSame(reg_num,
                                                 false /*must_replace*/);
           m_curr_row_modified = true;
 
           // FP has been restored to its original value, we are back
           // to using SP to calculate the CFA.
           if (m_fp_is_cfa) {
             m_fp_is_cfa = false;
-            RegisterInfo sp_reg_info;
             lldb::RegisterKind sp_reg_kind = eRegisterKindGeneric;
             uint32_t sp_reg_num = LLDB_REGNUM_GENERIC_SP;
-            m_inst_emulator_up->GetRegisterInfo(sp_reg_kind, sp_reg_num,
-                                                sp_reg_info);
+            RegisterInfo sp_reg_info =
+                *m_inst_emulator_up->GetRegisterInfo(sp_reg_kind, sp_reg_num);
             RegisterValue sp_reg_val;
             if (GetRegisterValue(sp_reg_info, sp_reg_val)) {
               m_cfa_reg_info = sp_reg_info;
               const uint32_t cfa_reg_num =
                   sp_reg_info.kinds[m_unwind_plan_ptr->GetRegisterKind()];
               assert(cfa_reg_num != LLDB_INVALID_REGNUM);
               m_curr_row->GetCFAValue().SetIsRegisterPlusOffset(
                   cfa_reg_num, m_initial_sp - sp_reg_val.GetAsUInt64());