[LLDB][MIPS] Move instruction emulation to optional GetRegisterInfo

[DavidSpickett]

Summary

Depends on D134538

lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

if (dst == src) {
     const int64_t src_opd_val = ReadRegisterUnsigned(
         eRegisterKindDWARF, dwarf_zero_mips + src, 0, &success);
     if (!success)
       return false;
 
     /* Check if this is daddiu sp, sp, imm16 */
     if (dst == dwarf_sp_mips) {
       uint64_t result = src_opd_val + imm;
-      RegisterInfo reg_info_sp;
-
-      if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
-        context.SetRegisterPlusOffset(reg_info_sp, imm);
+      llvm::Optional<RegisterInfo> reg_info_sp =
+          GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
+      if (reg_info_sp)
+        context.SetRegisterPlusOffset(*reg_info_sp, imm);
 
       /* We are allocating bytes on stack */
       context.type = eContextAdjustStackPointer;
 
       WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
       return true;
     }
 

 bool EmulateInstructionMIPS::Emulate_SW(llvm::MCInst &insn) {
   bool success = false;
   uint32_t imm16 = insn.getOperand(2).getImm();
   uint32_t imm = SignedBits(imm16, 15, 0);
   uint32_t src, base;
   int32_t address;
   Context bad_vaddr_context;
 
-  RegisterInfo reg_info_base;
-
   src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
   base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
 
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  llvm::Optional<RegisterInfo> reg_info_base =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base);
+  if (!reg_info_base)
     return false;
 
   /* read base register */
   address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
                                           dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;
 
   /* destination address */
   address = address + imm;
 
   /* Set the bad_vaddr register with base address used in the instruction */
   bad_vaddr_context.type = eContextInvalid;
   WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
                         address);
 
   /* We look for sp based non-volatile register stores */
   if (nonvolatile_reg_p(src)) {
-
-    RegisterInfo reg_info_src;
-
-    if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src,
-                         reg_info_src))
+    llvm::Optional<RegisterInfo> reg_info_src =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
+    if (!reg_info_src)
       return false;
 
     Context context;
     RegisterValue data_src;
     context.type = eContextPushRegisterOnStack;
-    context.SetRegisterToRegisterPlusOffset(reg_info_src, reg_info_base, 0);
+    context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
 
     uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
     Status error;
 
-    if (!ReadRegister(&reg_info_base, data_src))
+    if (!ReadRegister(&(*reg_info_base), data_src))
       return false;
 
-    if (data_src.GetAsMemoryData(&reg_info_src, buffer, reg_info_src.byte_size,
-                                 eByteOrderLittle, error) == 0)
+    if (data_src.GetAsMemoryData(&(*reg_info_src), buffer,
+                                 reg_info_src->byte_size, eByteOrderLittle,
+                                 error) == 0)
       return false;
 
-    if (!WriteMemory(context, address, buffer, reg_info_src.byte_size))
+    if (!WriteMemory(context, address, buffer, reg_info_src->byte_size))
       return false;
 
     return true;
   }
 
   return false;
 }
 
 bool EmulateInstructionMIPS::Emulate_LW(llvm::MCInst &insn) {
   bool success = false;
   uint32_t src, base;
   int32_t imm, address;
   Context bad_vaddr_context;
 
   src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
   base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
   imm = insn.getOperand(2).getImm();
 
-  RegisterInfo reg_info_base;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  if (GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
     return false;
 
   /* read base register */
   address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
                                           dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;
 
   /* destination address */
   address = address + imm;
 
   /* Set the bad_vaddr register with base address used in the instruction */
   bad_vaddr_context.type = eContextInvalid;
   WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
                         address);
 
   if (nonvolatile_reg_p(src)) {
     RegisterValue data_src;
-    RegisterInfo reg_info_src;
-
-    if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src,
-                         reg_info_src))
+    llvm::Optional<RegisterInfo> reg_info_src =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
+    if (!reg_info_src)
       return false;
 
     Context context;
     context.type = eContextPopRegisterOffStack;
     context.SetAddress(address);
 
-    return WriteRegister(context, &reg_info_src, data_src);
+    return WriteRegister(context, &(*reg_info_src), data_src);
   }
 
   return false;
 }
 
 bool EmulateInstructionMIPS::Emulate_SUBU_ADDU(llvm::MCInst &insn) {
   // SUBU sp, <src>, <rt>
   // ADDU sp, <src>, <rt>
if (!success)
       return false;
 
     if (op_name.equals_insensitive("SUBU"))
       result = src_opd_val - rt_opd_val;
     else
       result = src_opd_val + rt_opd_val;
 
     Context context;
-    RegisterInfo reg_info_sp;
-    if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
-      context.SetRegisterPlusOffset(reg_info_sp, rt_opd_val);
+    llvm::Optional<RegisterInfo> reg_info_sp =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
+    if (reg_info_sp)
+      context.SetRegisterPlusOffset(*reg_info_sp, rt_opd_val);
 
     /* We are allocating bytes on stack */
     context.type = eContextAdjustStackPointer;
 
     WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
 
     return true;
   } else if (src == dwarf_sp_mips) {
bool EmulateInstructionMIPS::Emulate_ADDIUSP(llvm::MCInst &insn) {
   uint64_t src_opd_val =
       ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_sp_mips, 0, &success);
   if (!success)
     return false;
 
   result = src_opd_val + imm9;
 
   Context context;
-  RegisterInfo reg_info_sp;
-  if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
-    context.SetRegisterPlusOffset(reg_info_sp, imm9);
+  llvm::Optional<RegisterInfo> reg_info_sp =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
+  if (reg_info_sp)
+    context.SetRegisterPlusOffset(*reg_info_sp, imm9);
 
   // We are adjusting the stack.
   context.type = eContextAdjustStackPointer;
 
   WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
   return true;
 }
 
if (base == dwarf_sp_mips) {
     uint64_t src_opd_val = ReadRegisterUnsigned(
         eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
     if (!success)
       return false;
 
     result = src_opd_val + imm4;
 
     Context context;
-    RegisterInfo reg_info_sp;
-    if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
-      context.SetRegisterPlusOffset(reg_info_sp, imm4);
+    llvm::Optional<RegisterInfo> reg_info_sp =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
+    if (reg_info_sp)
+      context.SetRegisterPlusOffset(*reg_info_sp, imm4);
 
     // We are adjusting the stack.
     context.type = eContextAdjustStackPointer;
 
     WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips, result);
   }
 
   return true;
 }
 
 bool EmulateInstructionMIPS::Emulate_SWSP(llvm::MCInst &insn) {
   bool success = false;
   uint32_t imm5 = insn.getOperand(2).getImm();
   uint32_t src, base;
   Context bad_vaddr_context;
   uint32_t address;
 
   src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
   base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
 
-  RegisterInfo reg_info_base;
-
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  llvm::Optional<RegisterInfo> reg_info_base =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base);
+  if (!reg_info_base)
     return false;
 
   // read base register
   address = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_zero_mips + base, 0,
                                  &success);
   if (!success)
     return false;
 
   // destination address
   address = address + imm5;
 
   // We use bad_vaddr_context to store base address which is used by H/W
   // watchpoint Set the bad_vaddr register with base address used in the
   // instruction
   bad_vaddr_context.type = eContextInvalid;
   WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
                         address);
 
   // We look for sp based non-volatile register stores.
   if (base == dwarf_sp_mips && nonvolatile_reg_p(src)) {
     RegisterInfo reg_info_src = {};
     Context context;
     RegisterValue data_src;
     context.type = eContextPushRegisterOnStack;
-    context.SetRegisterToRegisterPlusOffset(reg_info_src, reg_info_base, 0);
+    context.SetRegisterToRegisterPlusOffset(reg_info_src, *reg_info_base, 0);
 
     uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
     Status error;
 
-    if (!ReadRegister(&reg_info_base, data_src))
+    if (!ReadRegister(&(*reg_info_base), data_src))
       return false;
 
     if (data_src.GetAsMemoryData(&reg_info_src, buffer, reg_info_src.byte_size,
                                  eByteOrderLittle, error) == 0)
       return false;
 
     if (!WriteMemory(context, address, buffer, reg_info_src.byte_size))
       return false;
bool EmulateInstructionMIPS::Emulate_SWM16_32(llvm::MCInst &insn) {
   // We are looking for sp based stores so if base is not a stack pointer then
   // don't proceed.
   if (base != dwarf_sp_mips)
     return false;
 
   // offset is always the last operand.
   uint32_t offset = insn.getOperand(num_operands - 1).getImm();
 
-  RegisterInfo reg_info_base;
-  RegisterInfo reg_info_src;
-
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  llvm::Optional<RegisterInfo> reg_info_base =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base);
+  if (!reg_info_base)
     return false;
 
   // read SP
   uint32_t base_address = ReadRegisterUnsigned(
       eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;
 
/*
         This check is required for SWP instruction because source operand could
        be any register.
         SWM16 and SWM32 instruction always has saved registers as source
        operands.
     */
     if (!nonvolatile_reg_p(src))
       return false;
 
-    if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src,
-                         reg_info_src))
+    llvm::Optional<RegisterInfo> reg_info_src =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
+    if (!reg_info_src)
       return false;
 
     Context context;
     RegisterValue data_src;
     context.type = eContextPushRegisterOnStack;
-    context.SetRegisterToRegisterPlusOffset(reg_info_src, reg_info_base, 0);
+    context.SetRegisterToRegisterPlusOffset(*reg_info_src, *reg_info_base, 0);
 
     uint8_t buffer[RegisterValue::kMaxRegisterByteSize];
     Status error;
 
-    if (!ReadRegister(&reg_info_base, data_src))
+    if (!ReadRegister(&(*reg_info_base), data_src))
       return false;
 
-    if (data_src.GetAsMemoryData(&reg_info_src, buffer, reg_info_src.byte_size,
-                                 eByteOrderLittle, error) == 0)
+    if (data_src.GetAsMemoryData(&(*reg_info_src), buffer,
+                                 reg_info_src->byte_size, eByteOrderLittle,
+                                 error) == 0)
       return false;
 
-    if (!WriteMemory(context, base_address, buffer, reg_info_src.byte_size))
+    if (!WriteMemory(context, base_address, buffer, reg_info_src->byte_size))
       return false;
 
     // Stack address for next register
-    base_address = base_address + reg_info_src.byte_size;
+    base_address = base_address + reg_info_src->byte_size;
   }
   return true;
 }
 
 bool EmulateInstructionMIPS::Emulate_LWSP(llvm::MCInst &insn) {
   bool success = false;
   uint32_t src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg());
   uint32_t base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg());
   uint32_t imm5 = insn.getOperand(2).getImm();
   Context bad_vaddr_context;
 
-  RegisterInfo reg_info_base;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
     return false;
 
   // read base register
   uint32_t base_address = ReadRegisterUnsigned(
       eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;
 
   base_address = base_address + imm5;
 
   // We use bad_vaddr_context to store base address which is used by H/W
   // watchpoint Set the bad_vaddr register with base address used in the
   // instruction
   bad_vaddr_context.type = eContextInvalid;
   WriteRegisterUnsigned(bad_vaddr_context, eRegisterKindDWARF, dwarf_bad_mips,
                         base_address);
 
   if (base == dwarf_sp_mips && nonvolatile_reg_p(src)) {
     RegisterValue data_src;
-    RegisterInfo reg_info_src;
-
-    if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src,
-                         reg_info_src))
+    llvm::Optional<RegisterInfo> reg_info_src =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + src);
+    if (!reg_info_src)
       return false;
 
     Context context;
     context.type = eContextPopRegisterOffStack;
     context.SetAddress(base_address);
 
-    return WriteRegister(context, &reg_info_src, data_src);
+    return WriteRegister(context, &(*reg_info_src), data_src);
   }
 
   return false;
 }
 
 /* Emulate LWM16, LWM32 and LWP instructions.
 
    LWM16 always has stack pointer as a base register (but it is still available
bool EmulateInstructionMIPS::Emulate_LWM16_32(llvm::MCInst &insn) {
   uint32_t base_address = ReadRegisterUnsigned(
       eRegisterKindDWARF, dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;
 
   base_address = base_address + imm;
 
   RegisterValue data_dst;
-  RegisterInfo reg_info_dst;
 
   // Total no of registers to be re-stored are num_operands-2.
   for (uint32_t i = 0; i < num_operands - 2; i++) {
     // Get the register number to be re-stored.
     dst = m_reg_info->getEncodingValue(insn.getOperand(i).getReg());
 
     /*
         Record only non-volatile loads.
         This check is required for LWP instruction because destination operand
        could be any register.
         LWM16 and LWM32 instruction always has saved registers as destination
        operands.
     */
     if (!nonvolatile_reg_p(dst))
       return false;
 
-    if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + dst,
-                         reg_info_dst))
+    llvm::Optional<RegisterInfo> reg_info_dst =
+        GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + dst);
+    if (!reg_info_dst)
       return false;
 
     Context context;
     context.type = eContextPopRegisterOffStack;
     context.SetAddress(base_address + (i * 4));
 
-    if (!WriteRegister(context, &reg_info_dst, data_dst))
+    if (!WriteRegister(context, &(*reg_info_dst), data_dst))
       return false;
   }
 
   return true;
 }
 
 bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) {
   bool success = false;
bool EmulateInstructionMIPS::Emulate_JRADDIUSP(llvm::MCInst &insn) {
 
   Context context;
 
   // Update the PC
   if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips,
                              ra_val))
     return false;
 
-  RegisterInfo reg_info_sp;
-  if (GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips, reg_info_sp))
-    context.SetRegisterPlusOffset(reg_info_sp, imm5);
+  llvm::Optional<RegisterInfo> reg_info_sp =
+      GetRegisterInfo(eRegisterKindDWARF, dwarf_sp_mips);
+  if (reg_info_sp)
+    context.SetRegisterPlusOffset(*reg_info_sp, imm5);
 
   // We are adjusting stack
   context.type = eContextAdjustStackPointer;
 
   // update SP
   return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_sp_mips,
                                result);
 }
bool EmulateInstructionMIPS::Emulate_LDST_Imm(llvm::MCInst &insn) {
   int32_t imm, address;
   Context bad_vaddr_context;
 
   uint32_t num_operands = insn.getNumOperands();
   base =
       m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
   imm = insn.getOperand(num_operands - 1).getImm();
 
-  RegisterInfo reg_info_base;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
     return false;
 
   /* read base register */
   address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
                                           dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;
 
bool EmulateInstructionMIPS::Emulate_LDST_Reg(llvm::MCInst &insn) {
   Context bad_vaddr_context;
 
   uint32_t num_operands = insn.getNumOperands();
   base =
       m_reg_info->getEncodingValue(insn.getOperand(num_operands - 2).getReg());
   index =
       m_reg_info->getEncodingValue(insn.getOperand(num_operands - 1).getReg());
 
-  RegisterInfo reg_info_base, reg_info_index;
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base,
-                       reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + base))
     return false;
 
-  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index,
-                       reg_info_index))
+  if (!GetRegisterInfo(eRegisterKindDWARF, dwarf_zero_mips + index))
     return false;
 
   /* read base register */
   address = (int32_t)ReadRegisterUnsigned(eRegisterKindDWARF,
                                           dwarf_zero_mips + base, 0, &success);
   if (!success)
     return false;