[LLDB] Add an llvm::Optional version of GetRegisterInfo

[DavidSpickett]

Summary

We have some 500 ish uses of the bool plus ref version
so changing them all at once isn't a great idea.

This adds an overload that doesn't take a RegisterInfo&
and returns an optional.

Once I'm done switching all the existing callers I'll
remove the original function.

Benefits of optional over bool plus ref:

• The intent of the function is clear from the prototype.
• It's harder to forget to check if the return is valid, and if you do you'll get an assert.
• You don't hide ununsed variables, which happens because passing by ref marks a variable used.
• You can't forget to reset the RegisterInfo in between calls.

[DavidSpickett]

@clayborg As promised on https://reviews.llvm.org/D134041.

The strategy is:

• Make the original function concrete and have it call the optional version.
• Derived classes implement the optional version.
• One by one (or rather, manageable patch by manageable patch) switch the callers to the optional version.
• Remove the original function.

I've stacked the changes to do that onto this one, lldb is buildable and passes tests at all points. ARM is by far the largest, even if it is fairly mechanical changes.

You'll see some dodgy stuff like &(*info) because some APIs want a RegisterInfo*, but that's another rabbit hole I do want to look at but not here.

[DavidSpickett]

I appreciate this is a lot of churn for code that likely "just works" (or in reality, "isn't used very often") but with the recent riscv changes I'd like to modernise this area where possible. If this is too much at least I know to look for smaller opportunities in future.

lldb/include/lldb/Core/EmulateInstruction.h

public:
 
   virtual InstructionCondition GetInstructionCondition() {
     return UnconditionalCondition;
   }
 
   virtual bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                              OptionValueDictionary *test_data) = 0;
 
-  virtual bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                               RegisterInfo &reg_info) = 0;
+  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
+                       RegisterInfo &reg_info);
+
+  virtual llvm::Optional<RegisterInfo>
+  GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) = 0;
 
   // Optional overrides
   virtual bool SetInstruction(const Opcode &insn_opcode,
                               const Address &inst_addr, Target *target);
 
   virtual bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan);
 
   static const char *TranslateRegister(lldb::RegisterKind reg_kind,

lldb/source/Core/EmulateInstruction.cpp

if (reg_ctx && GetBestRegisterKindAndNumber(&reg_info, reg_kind, reg_num))
     return reg_ctx->ConvertRegisterKindToRegisterNumber(reg_kind, reg_num);
   return LLDB_INVALID_REGNUM;
 }
 
 bool EmulateInstruction::CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) {
   unwind_plan.Clear();
   return false;
 }
+
+bool EmulateInstruction::GetRegisterInfo(lldb::RegisterKind reg_kind,
+                                         uint32_t reg_num,
+                                         RegisterInfo &reg_info) {
+  llvm::Optional<RegisterInfo> info = GetRegisterInfo(reg_kind, reg_num);
+  if (info)
+    reg_info = *info;
+  return info.has_value();
+}
 No newline at end of file

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h

public:
 
   bool EvaluateInstruction(uint32_t evaluate_options) override;
 
   InstructionCondition GetInstructionCondition() override;
 
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
 
-  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                       RegisterInfo &reg_info) override;
+  using EmulateInstruction::GetRegisterInfo;
+  llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
+                                               uint32_t reg_num) override;
 
   bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override;
 
   uint32_t ArchVersion();
 
   bool ConditionPassed(const uint32_t opcode);
 
   uint32_t CurrentCond(const uint32_t opcode);

lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp

 #define APSR_V Bit32(m_opcode_cpsr, CPSR_V_POS)
 
 #define AlignPC(pc_val) (pc_val & 0xFFFFFFFC)
 
 //
 // ITSession implementation
 //
 
-static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo &reg_info) {
+static llvm::Optional<RegisterInfo> GetARMDWARFRegisterInfo(unsigned reg_num) {
+  RegisterInfo reg_info;
   ::memset(&reg_info, 0, sizeof(RegisterInfo));
   ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
 
   if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
     reg_info.byte_size = 16;
     reg_info.format = eFormatVectorOfUInt8;
     reg_info.encoding = eEncodingVector;
   }
static llvm::Optional<RegisterInfo> GetARMDWARFRegisterInfo(unsigned reg_num) {
   case dwarf_q14:
     reg_info.name = "q14";
     break;
   case dwarf_q15:
     reg_info.name = "q15";
     break;
 
   default:
-    return false;
+    return {};
   }
-  return true;
+  return reg_info;
 }
 
 // A8.6.50
 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
 static uint32_t CountITSize(uint32_t ITMask) {
   // First count the trailing zeros of the IT mask.
   uint32_t TZ = llvm::countTrailingZeros(ITMask);
   if (TZ > 3) {
if (!success)
     return false;
 
   if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_r0 + n, data))
     return false;
 
   return true;
 }
 
-bool EmulateInstructionARM::GetRegisterInfo(lldb::RegisterKind reg_kind,
-                                            uint32_t reg_num,
-                                            RegisterInfo &reg_info) {
+llvm::Optional<RegisterInfo>
+EmulateInstructionARM::GetRegisterInfo(lldb::RegisterKind reg_kind,
+                                       uint32_t reg_num) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_pc;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_sp;
       break;
     case LLDB_REGNUM_GENERIC_FP:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_r7;
       break;
     case LLDB_REGNUM_GENERIC_RA:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_lr;
       break;
     case LLDB_REGNUM_GENERIC_FLAGS:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_cpsr;
       break;
     default:
-      return false;
+      return {};
     }
   }
 
   if (reg_kind == eRegisterKindDWARF)
-    return GetARMDWARFRegisterInfo(reg_num, reg_info);
-  return false;
+    return GetARMDWARFRegisterInfo(reg_num);
+  return {};
 }
 
 uint32_t EmulateInstructionARM::GetFramePointerRegisterNumber() const {
   if (m_arch.GetTriple().isAndroid())
     return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
   bool is_apple = false;
   if (m_arch.GetTriple().getVendor() == llvm::Triple::Apple)
     is_apple = true;

lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.h

public:
   bool EvaluateInstruction(uint32_t evaluate_options) override;
 
   bool TestEmulation(lldb_private::Stream *out_stream,
                      lldb_private::ArchSpec &arch,
                      lldb_private::OptionValueDictionary *test_data) override {
     return false;
   }
 
-  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                       lldb_private::RegisterInfo &reg_info) override;
+  using EmulateInstruction::GetRegisterInfo;
+
+  llvm::Optional<lldb_private::RegisterInfo>
+  GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override;
 
   bool
   CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override;
 
   enum AddrMode { AddrMode_OFF, AddrMode_PRE, AddrMode_POST };
 
   enum BranchType {
     BranchType_CALL,

lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp

 
 #include "Plugins/Process/Utility/InstructionUtils.h"
 
 using namespace lldb;
 using namespace lldb_private;
 
 LLDB_PLUGIN_DEFINE_ADV(EmulateInstructionARM64, InstructionARM64)
 
-static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo &reg_info) {
+static llvm::Optional<RegisterInfo> LLDBTableGetRegisterInfo(uint32_t reg_num) {
   if (reg_num >= std::size(g_register_infos_arm64_le))
-    return false;
-  reg_info = g_register_infos_arm64_le[reg_num];
-  return true;
+    return {};
+  return g_register_infos_arm64_le[reg_num];
 }
 
 #define No_VFP 0
 #define VFPv1 (1u << 1)
 #define VFPv2 (1u << 2)
 #define VFPv3 (1u << 3)
 #define AdvancedSIMD (1u << 4)
 
bool EmulateInstructionARM64::SetTargetTriple(const ArchSpec &arch) {
   if (arch.GetTriple().getArch() == llvm::Triple::arm)
     return true;
   else if (arch.GetTriple().getArch() == llvm::Triple::thumb)
     return true;
 
   return false;
 }
 
-bool EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind,
-                                              uint32_t reg_num,
-                                              RegisterInfo &reg_info) {
+llvm::Optional<RegisterInfo>
+EmulateInstructionARM64::GetRegisterInfo(RegisterKind reg_kind,
+                                         uint32_t reg_num) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_pc_arm64;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_sp_arm64;
       break;
     case LLDB_REGNUM_GENERIC_FP:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_fp_arm64;
       break;
     case LLDB_REGNUM_GENERIC_RA:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_lr_arm64;
       break;
     case LLDB_REGNUM_GENERIC_FLAGS:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_cpsr_arm64;
       break;
 
     default:
-      return false;
+      return {};
     }
   }
 
   if (reg_kind == eRegisterKindLLDB)
-    return LLDBTableGetRegisterInfo(reg_num, reg_info);
-  return false;
+    return LLDBTableGetRegisterInfo(reg_num);
+  return {};
 }
 
 EmulateInstructionARM64::Opcode *
 EmulateInstructionARM64::GetOpcodeForInstruction(const uint32_t opcode) {
   static EmulateInstructionARM64::Opcode g_opcodes[] = {
       // Prologue instructions
 
       // push register(s)

lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.h

bool SetInstruction(const lldb_private::Opcode &insn_opcode,
                       lldb_private::Target *target) override;
 
   bool TestEmulation(lldb_private::Stream *out_stream,
                      lldb_private::ArchSpec &arch,
                      lldb_private::OptionValueDictionary *test_data) override {
     return false;
   }
 
-  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                       lldb_private::RegisterInfo &reg_info) override;
+  using EmulateInstruction::GetRegisterInfo;
+
+  llvm::Optional<lldb_private::RegisterInfo>
+  GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override;
 
   bool
   CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override;
 
 protected:
   typedef struct {
     const char *op_name;
     bool (EmulateInstructionMIPS::*callback)(llvm::MCInst &insn);

lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp

const char *EmulateInstructionMIPS::GetRegisterName(unsigned reg_num,
   case dwarf_mir_mips:
     return "mir";
   case dwarf_config5_mips:
     return "config5";
   }
   return nullptr;
 }
 
-bool EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,
-                                             uint32_t reg_num,
-                                             RegisterInfo &reg_info) {
+llvm::Optional<RegisterInfo>
+EmulateInstructionMIPS::GetRegisterInfo(RegisterKind reg_kind,
+                                        uint32_t reg_num) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_pc_mips;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_sp_mips;
       break;
     case LLDB_REGNUM_GENERIC_FP:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_r30_mips;
       break;
     case LLDB_REGNUM_GENERIC_RA:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_ra_mips;
       break;
     case LLDB_REGNUM_GENERIC_FLAGS:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_sr_mips;
       break;
     default:
-      return false;
+      return {};
     }
   }
 
   if (reg_kind == eRegisterKindDWARF) {
+    RegisterInfo reg_info;
     ::memset(&reg_info, 0, sizeof(RegisterInfo));
     ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
 
     if (reg_num == dwarf_sr_mips || reg_num == dwarf_fcsr_mips ||
         reg_num == dwarf_fir_mips || reg_num == dwarf_mcsr_mips ||
         reg_num == dwarf_mir_mips || reg_num == dwarf_config5_mips) {
       reg_info.byte_size = 4;
       reg_info.format = eFormatHex;
       reg_info.encoding = eEncodingUint;
     } else if ((int)reg_num >= dwarf_zero_mips &&
                (int)reg_num <= dwarf_f31_mips) {
       reg_info.byte_size = 4;
       reg_info.format = eFormatHex;
       reg_info.encoding = eEncodingUint;
     } else if ((int)reg_num >= dwarf_w0_mips &&
                (int)reg_num <= dwarf_w31_mips) {
       reg_info.byte_size = 16;
       reg_info.format = eFormatVectorOfUInt8;
       reg_info.encoding = eEncodingVector;
     } else {
-      return false;
+      return {};
     }
 
     reg_info.name = GetRegisterName(reg_num, false);
     reg_info.alt_name = GetRegisterName(reg_num, true);
     reg_info.kinds[eRegisterKindDWARF] = reg_num;
 
     switch (reg_num) {
     case dwarf_r30_mips:
case dwarf_pc_mips:
       reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
       break;
     case dwarf_sr_mips:
       reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
       break;
     default:
       break;
     }
-    return true;
+    return reg_info;
   }
-  return false;
+  return {};
 }
 
 EmulateInstructionMIPS::MipsOpcode *
 EmulateInstructionMIPS::GetOpcodeForInstruction(llvm::StringRef name) {
   static EmulateInstructionMIPS::MipsOpcode g_opcodes[] = {
       // Prologue/Epilogue instructions
       {"ADDiu", &EmulateInstructionMIPS::Emulate_ADDiu,
        "ADDIU rt, rs, immediate"},

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.h

public:
   bool EvaluateInstruction(uint32_t evaluate_options) override;
 
   bool TestEmulation(lldb_private::Stream *out_stream,
                      lldb_private::ArchSpec &arch,
                      lldb_private::OptionValueDictionary *test_data) override {
     return false;
   }
 
-  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                       lldb_private::RegisterInfo &reg_info) override;
+  using EmulateInstruction::GetRegisterInfo;
+
+  llvm::Optional<lldb_private::RegisterInfo>
+  GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num) override;
 
   bool
   CreateFunctionEntryUnwind(lldb_private::UnwindPlan &unwind_plan) override;
 
 protected:
   typedef struct {
     const char *op_name;
     bool (EmulateInstructionMIPS64::*callback)(llvm::MCInst &insn);

lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp

const char *EmulateInstructionMIPS64::GetRegisterName(unsigned reg_num,
   case dwarf_mir_mips64:
     return "mir";
   case dwarf_config5_mips64:
     return "config5";
   }
   return nullptr;
 }
 
-bool EmulateInstructionMIPS64::GetRegisterInfo(RegisterKind reg_kind,
-                                               uint32_t reg_num,
-                                               RegisterInfo &reg_info) {
+llvm::Optional<RegisterInfo>
+EmulateInstructionMIPS64::GetRegisterInfo(RegisterKind reg_kind,
+                                          uint32_t reg_num) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_pc_mips64;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_sp_mips64;
       break;
     case LLDB_REGNUM_GENERIC_FP:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_r30_mips64;
       break;
     case LLDB_REGNUM_GENERIC_RA:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_ra_mips64;
       break;
     case LLDB_REGNUM_GENERIC_FLAGS:
       reg_kind = eRegisterKindDWARF;
       reg_num = dwarf_sr_mips64;
       break;
     default:
-      return false;
+      return {};
     }
   }
 
   if (reg_kind == eRegisterKindDWARF) {
+    RegisterInfo reg_info;
     ::memset(&reg_info, 0, sizeof(RegisterInfo));
     ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
 
     if (reg_num == dwarf_sr_mips64 || reg_num == dwarf_fcsr_mips64 ||
         reg_num == dwarf_fir_mips64 || reg_num == dwarf_mcsr_mips64 ||
         reg_num == dwarf_mir_mips64 || reg_num == dwarf_config5_mips64) {
       reg_info.byte_size = 4;
       reg_info.format = eFormatHex;
       reg_info.encoding = eEncodingUint;
     } else if ((int)reg_num >= dwarf_zero_mips64 &&
                (int)reg_num <= dwarf_f31_mips64) {
       reg_info.byte_size = 8;
       reg_info.format = eFormatHex;
       reg_info.encoding = eEncodingUint;
     } else if ((int)reg_num >= dwarf_w0_mips64 &&
                (int)reg_num <= dwarf_w31_mips64) {
       reg_info.byte_size = 16;
       reg_info.format = eFormatVectorOfUInt8;
       reg_info.encoding = eEncodingVector;
     } else {
-      return false;
+      return {};
     }
 
     reg_info.name = GetRegisterName(reg_num, false);
     reg_info.alt_name = GetRegisterName(reg_num, true);
     reg_info.kinds[eRegisterKindDWARF] = reg_num;
 
     switch (reg_num) {
     case dwarf_r30_mips64:
case dwarf_pc_mips64:
       reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
       break;
     case dwarf_sr_mips64:
       reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
       break;
     default:
       break;
     }
-    return true;
+    return reg_info;
   }
-  return false;
+  return {};
 }
 
 EmulateInstructionMIPS64::MipsOpcode *
 EmulateInstructionMIPS64::GetOpcodeForInstruction(llvm::StringRef op_name) {
   static EmulateInstructionMIPS64::MipsOpcode g_opcodes[] = {
       // Prologue/Epilogue instructions
       {"DADDiu", &EmulateInstructionMIPS64::Emulate_DADDiu,
        "DADDIU rt, rs, immediate"},

lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.h

public:
 
   bool EvaluateInstruction(uint32_t evaluate_options) override;
 
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override {
     return false;
   }
 
-  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                       RegisterInfo &reg_info) override;
+  using EmulateInstruction::GetRegisterInfo;
+
+  llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
+                                               uint32_t reg_num) override;
 
   bool CreateFunctionEntryUnwind(UnwindPlan &unwind_plan) override;
 
 private:
   struct Opcode {
     uint32_t mask;
     uint32_t value;
     bool (EmulateInstructionPPC64::*callback)(uint32_t opcode);

lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp

EmulateInstructionPPC64::CreateInstance(const ArchSpec &arch,
 
   return nullptr;
 }
 
 bool EmulateInstructionPPC64::SetTargetTriple(const ArchSpec &arch) {
   return arch.GetTriple().isPPC64();
 }
 
-static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo &reg_info) {
+static llvm::Optional<RegisterInfo> LLDBTableGetRegisterInfo(uint32_t reg_num) {
   if (reg_num >= std::size(g_register_infos_ppc64le))
-    return false;
-  reg_info = g_register_infos_ppc64le[reg_num];
-  return true;
+    return {};
+  return g_register_infos_ppc64le[reg_num];
 }
 
-bool EmulateInstructionPPC64::GetRegisterInfo(RegisterKind reg_kind,
-                                              uint32_t reg_num,
-                                              RegisterInfo &reg_info) {
+llvm::Optional<RegisterInfo>
+EmulateInstructionPPC64::GetRegisterInfo(RegisterKind reg_kind,
+                                         uint32_t reg_num) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_pc_ppc64le;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_r1_ppc64le;
       break;
     case LLDB_REGNUM_GENERIC_RA:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_lr_ppc64le;
       break;
     case LLDB_REGNUM_GENERIC_FLAGS:
       reg_kind = eRegisterKindLLDB;
       reg_num = gpr_cr_ppc64le;
       break;
 
     default:
-      return false;
+      return {};
     }
   }
 
   if (reg_kind == eRegisterKindLLDB)
-    return LLDBTableGetRegisterInfo(reg_num, reg_info);
-  return false;
+    return LLDBTableGetRegisterInfo(reg_num);
+  return {};
 }
 
 bool EmulateInstructionPPC64::ReadInstruction() {
   bool success = false;
   m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
                                 LLDB_INVALID_ADDRESS, &success);
   if (success) {
     Context ctx;

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.h

bool SupportsEmulatingInstructionsOfType(InstructionType inst_type) override {
     return SupportsThisInstructionType(inst_type);
   }
 
   bool SetTargetTriple(const ArchSpec &arch) override;
   bool ReadInstruction() override;
   bool EvaluateInstruction(uint32_t options) override;
   bool TestEmulation(Stream *out_stream, ArchSpec &arch,
                      OptionValueDictionary *test_data) override;
-  bool GetRegisterInfo(lldb::RegisterKind reg_kind, uint32_t reg_num,
-                       RegisterInfo &reg_info) override;
+  using EmulateInstruction::GetRegisterInfo;
+
+  llvm::Optional<RegisterInfo> GetRegisterInfo(lldb::RegisterKind reg_kind,
+                                               uint32_t reg_num) override;
 
   lldb::addr_t ReadPC(bool &success);
   bool WritePC(lldb::addr_t pc);
 
   const InstrPattern *Decode(uint32_t inst);
   bool DecodeAndExecute(uint32_t inst, bool ignore_cond);
 
   template <typename T>

lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp

 bool EmulateInstructionRISCV::WritePC(lldb::addr_t pc) {
   EmulateInstruction::Context ctx;
   ctx.type = eContextAdvancePC;
   ctx.SetNoArgs();
   return WriteRegisterUnsigned(ctx, eRegisterKindGeneric,
                                LLDB_REGNUM_GENERIC_PC, pc);
 }
 
-bool EmulateInstructionRISCV::GetRegisterInfo(lldb::RegisterKind reg_kind,
-                                              uint32_t reg_index,
-                                              RegisterInfo &reg_info) {
+llvm::Optional<RegisterInfo>
+EmulateInstructionRISCV::GetRegisterInfo(lldb::RegisterKind reg_kind,
+                                         uint32_t reg_index) {
   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_index) {
     case LLDB_REGNUM_GENERIC_PC:
       reg_kind = eRegisterKindLLDB;
       reg_index = gpr_pc_riscv;
       break;
     case LLDB_REGNUM_GENERIC_SP:
       reg_kind = eRegisterKindLLDB;
EmulateInstructionRISCV::GetRegisterInfo(lldb::RegisterKind reg_kind,
   }
 
   const RegisterInfo *array =
       RegisterInfoPOSIX_riscv64::GetRegisterInfoPtr(m_arch);
   const uint32_t length =
       RegisterInfoPOSIX_riscv64::GetRegisterInfoCount(m_arch);
 
   if (reg_index >= length || reg_kind != eRegisterKindLLDB)
-    return false;
+    return {};
 
-  reg_info = array[reg_index];
-  return true;
+  return array[reg_index];
 }
 
 bool EmulateInstructionRISCV::SetTargetTriple(const ArchSpec &arch) {
   return SupportsThisArch(arch);
 }
 
 bool EmulateInstructionRISCV::TestEmulation(Stream *out_stream, ArchSpec &arch,
                                             OptionValueDictionary *test_data) {