[PowerPC] Improve kill flag computation and add verification after MI peephole

[nemanjai]

Summary

The MI Peephole pass has grown to include a large number of transformations over the years. Many of the transformations require re-computation of kill flags but don't do a good job of re-computing them. This causes us to have very common failures when the compiler is built with expensive checks. Over time, we added and augmented a function that is supposed to go and fix up kill flags after each transformation but we keep missing cases.
This patch does the following:

• Removes the function to re-compute kill flags
• Adds LiveVariables to compute and maintain kill flags while transforming code
• Adds re-computation of kill flags for the post-RA peepholes for each block that contains a transformed instruction

[amyk]

Is it just me or is this patch not clean? It appears there is a LIT failure in CodeGen/PowerPC/sext_elimination.mir and I am getting some test-suite build failures.

[nemanjai]

In D133103#3807274, @amyk wrote:

Is it just me or is this patch not clean? It appears there is a LIT failure in CodeGen/PowerPC/sext_elimination.mir and I am getting some test-suite build failures.

Interesting. I was not seeing failures, but something may have changed between my revision and yours. I'll have a look.

[amyk]

Some initial general comments for this patch:

• The description doesn't exactly clarify how the flags are recomputed for pre/post-RA. Can the description be clarified a bit more?
• The improvement of the LLVM_DEBUG messages and general code clean up could be a separate patch. Can this stuff be separated out?

[amyk]

Just had a couple comments I wanted to submit prior to the rebase of this patch.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3714

Nit: unrelated whitespace change.

3732

Isn't this an unrelated change, as well?

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

502

We're accessing the register both in the cases when we're removing it from RegsToUpdate and when we're re-running LiveVariables.
It might make sense to pull out MO.isReg() into a separate variable.

1941

Nit: unrelated whitespace change.

[amyk]

A few more submitted comments that I realized I had left on the review.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

3719

We should clarify that for MI, we're actually adding both the defs and the uses.

3723

It would be good to have a more descriptive name for UpdateRegs. Perhaps RegsToUpdate.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

472

Since you're adding a significant amount of code to a deeply nested block, consider flipping this condition to an early exit to reduce the nesting.

[nemanjai]

Address review comments

• Commit the addition of LLVM_DEBUG messages as a separate NFC patch
• Provide some helper functions
• Remove unrelated changes
• Some general cleanup

[nemanjai]

Ping.

[nemanjai]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

20

s/in after/after

[lei]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

4854–4855

this should be removed as well?

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

133

nit: I knnow you have doc above, but it would be good if we can add a note here about valid usage of this new function. When it should be used etc..

153

nit: seems prev code list all required first and then preserved?

1148

Why was this removed?

1287

nit: add doc as to why we are doing this?

1802

Is this change on purpose to fix a previous bug? Seems unrelated.

[amyk]

Some additional comments and questions I thought of after our previous review/discussion.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

839

Do we need to addRegToUpdate() here?

1049

Do we need to addRegToUpdate() here?

1941

Nit: Not sure if you missed this before, but this change seems unrelated.

llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir

2

Potentially silly question, but because we're adding livevars here explicitly, does this mean we are not running the live variables pass by default when we are adding live variables to PPCMIPeephole?

[kamaub]

Some comments from the llvm-on-power team:

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

471–472

From the use of the variable, it seems more consistent for this to be a Smallset instead of a Smallvector, additionally, is 2 enough? We check the MI and the DefMI for Regs to update, a bigger set size may be more optimal.

498

Please add a comment explaining why this is needed.

499

if (RegsToUpdate.empty())
  return;

I think this is more appropriate to the coding guidelines.

501

1. Please DeMorganize this into an early exit condition.
2. Please add a comment explaining why this needs to be a definition of a register.

[kamaub]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

899

Should there be a call to recomputeLVForDyingInstr() as well since this ConvReg1 is a reg of RoundInstr which is being eraseFromParent() on line 847 and cannot be marked ToErase inside the lambda?

1790

We add this compare's operands to the RegsToUpdate unconditionally earlier, and now in this code path it is deleted meaning that we could end up attempting to recompute the LV for its VRegs and could hit errors.
If this is the case I think being inside a function means recomputeLVForDyingInstr() would have to become a static function in order to catch this corner case =?

[kamaub]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1259

Do we need to track the registers in this instruction

[stefanp]

Overall I think that this patch makes sense to me. A few minor things:

1. I think that there are some changes that are nice improvements but aren't really part of the kill flags fix. This is already a fairly large patch and removing these little fixes might make the patch clearer and easier to read. They can be made before or after with a (or several) NFC change(s).
2. I know this is an older patch and I apologize for taking so long to look at it. When I tried to rebase this patch to the Top of main I realized that I had to add a couple more addRegToUpdate in order to get it working. This isn't an issue with the patch it's just that new changes to PPCMIPeephole will require additions or addRegToUpdate.
3. Is there any way to provide an error or warning for the future when more peephole optimizations are added and for whatever reason the developer forgets to call addRegToUpdate? There may not be a way to do this and that's fine. I'm more curious.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

183

If you made this function a private member of PPCMIPeephole then you wouldn't have to pass in RegsToUpdate since that SmallSet is already a private member of PPCMIPeephole. It would just save constantly having to repeat the first parameter that is always the same.

Of course if you did change this you would also have to make convertUnprimedAccPHIs a private member which I'm not sure is worth it... But anyway, maybe this is work for the future.

1196

nit:
Adding ToErase here is a good idea but maybe it should be a separate cleanup patch.
I don't think it has anything to do with the kill flag computation.

1288

Don't we guarantee that RegsToUpdate has only virtual registers?

static void addRegToUpdateWithLine(SmallSet<Register, 16> &RegsToUpdate,
                                   Register Reg, int Line) {
  if (!Register::isVirtualRegister(Reg))
    return;
...

Maybe I'm missing something but I feel like we don't need to check && Register::isVirtualRegister(Reg).

What you may be able to do is add an assert to make sure that what I'm saying is actually true all the time.

1802

I'm also curious about this. I can't figure out why this else was added.
Should Simplified only be true if !IsPartiallyRedudant?

llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir

780

This looks like a fix for this test case that isn't related to the kill flags fix. Maybe a separate NFC patch?

[stefanp]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1196

Nope. I was wrong. You do need to add this here as part of this patch.
Please disregard my previous comment.

1211

Note:
Checked that what would happen if we ended up with OrigOp1Reg == PPC::NoRegister here and it should be fine.

Register::isVirtualRegister(PPC::NoRegister) returns false and so we cannot add PPC::NoRegister to the list.

1941

nit: Whitespace

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

20

nit:
Unrelated cleanup.

[amyk]

Realized I had another unsubmitted comment. I looked again and I do not have any other comments/questions for now aside from the ones that the others have asked about.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1781–1788

Why do we not need to add addRegToUpdate() here when we finally eliminate the compare instruction?

[nemanjai]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

183

I think it is not unreasonable to make these two functions members. Their functionality is part of the pass so it makes sense for them to be members.
The alternative solution would be to make RegsToUpdate a static member and access it from the free functions. However, that has the very undesirable effect of making the pass not thread-safe which matters at least for LTO builds.

502

The call to MO.getReg() in the if statement is safe because of short circuiting of the call to MO.isReg().

839

I think so. Thanks for catching this.

899

No, because ConvReg1 is not defined by RoundInstr.

1049

Actually no because we have actually added a new definition of the register that MI originally defined in the exact same place. The original MI will be deleted and the live range of the register it defined doesn't change.

1148

I don't remember. I have put it back now.

1259

This is currently broken, so we can't really perform this optimization safely.

1288

Oh, good point. The check is redundant.

1781–1788

Because we've added all the register operands of CMPI1 and CMPI2 starting on line 1663.

1790

Actually, we don't need to because there is only one user of the register it defines and that user is BI2 which just had that use replaced so the only definition from CMPI2 is going to be a dead register. We don't try to recompute live variables for dead registers. I've added a comment to explain this.

1802

Hmm, I don't actually remember, but it definitely looks wrong. Removed it.

llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir

2

Very good catch. This was a remnant of the initial implementation that simply added the livevars to the pipeline. I have removed it now.

[nemanjai]

Rebase on top of some new additions to the pass and address numerous review comments.

[stefanp]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

388

nit: spacing

441

We are adding RegMBB.first but what about RegMBB.second and AccReg? This is a new instruction so I assume that all of these registers now may have a different live range.

1943

There are two instructions that are erased here and I don't think all of the required registers are added to the update list.
I managed to get a reduced test case that I think shows this issue:

define hidden void @testCaller() local_unnamed_addr align 2 {
entry:
  br label %exit

exit: ; preds = %entry
  br label %cond.end.i.i

cond.end.i.i:                                     ; preds = %if.end116, %exit
  %CurrentState.0566 = phi i32 [ %CurrentState.2, %if.end116 ], [ -1, %exit ]
  %0 = load i32, ptr poison, align 8
  br label %while.body5.i

while.cond12.preheader.i:                         ; preds = %while.body5.i
  br i1 poison, label %if.end116, label %for.cond99.preheader

while.body5.i:                                    ; preds = %while.body5.i, %cond.end.i.i
  %Test.012.i = phi i32 [ 0, %cond.end.i.i ], [ %dec10.i, %while.body5.i ]
  %dec10.i = add nsw i32 %Test.012.i, -1
  %cmp4.i = icmp slt i32 0, %dec10.i
  br i1 %cmp4.i, label %while.body5.i, label %while.cond12.preheader.i

for.cond99.preheader:                             ; preds = %while.cond12.preheader.i
  %1 = load ptr, ptr poison, align 8
  %conv103 = sext i32 %0 to i64
  %arrayidx.i426 = getelementptr inbounds i32, ptr %1, i64 %conv103
  store i32 0, ptr %arrayidx.i426, align 4
  store i32 %CurrentState.0566, ptr poison, align 8
  br label %if.end116

if.end116:                                        ; preds = %for.cond99.preheader, %while.cond12.preheader.i
  %CurrentState.2 = phi i32 [ %0, %while.cond12.preheader.i ], [ poison, %for.cond99.preheader ]
  call fastcc void @callee()
  br label %cond.end.i.i
}
declare dso_local fastcc void @callee() unnamed_addr align 2

Compile with:

llc --mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -debug-only=ppc-mi-peepholes bugpoint-reduced-simplified.ll

I see the following output:

Combining pair:   %2:g8rc = EXTSW_32_64 %1:gprc
  %12:g8rc = RLDICR killed %2:g8rc, 2, 61
TO:   %12:g8rc = EXTSWSLI_32_64 %1:gprc, 2
Adding register: 1 on line 1944 for re-computation of kill flags
Deleting instruction:   %12:g8rc = RLDICR killed %2:g8rc, 2, 61
...
*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
- function:    testCaller
- basic block: %bb.2 while.cond12.preheader.i (0x119473888)
Virtual register %2 is not needed live through the block.

*** Bad machine code: LiveVariables: Block should not be in AliveBlocks ***
- function:    testCaller
- basic block: %bb.3 while.body5.i (0x119473988)
Virtual register %2 is not needed live through the block.
LLVM ERROR: Found 2 machine code errors.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

4814

A question I had: Does this function also require a call to recomputeLivenessFlags after PostRA?

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

134

Typo:

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

4814

We have an early exit on line 4757 for post-ra.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

388

Weird. I could have sworn I ran clang-format on this. I'll fix it. Thanks for noticing.

441

RegMBB.second is a MachineBasicBlock so we can't add it to the list of registers. The newly created registers won't be created with kill flags, so we don't need to recompute them and the result reg for the first PHI (Dst) is still defined in the exact same place, so it shouldn't need its kill flags recomputed.

1943

Ah, I see. Good catch. I think I'll just add the result register of SrcMI to the set and leave the SrcMI alone (DCE is run immediately after this pass to remove dead instructions).

[nemanjai]

Address comments

• Run clang-format
• Resolve issue with shift-extend peephole

[stefanp]

LGTM.
Thank you for cleaning up this pass!

[arsenm]

Kill flags should be removed. You should switch to reverse liveness which does not rely on accurate kill flags

[arsenm]

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

425

This should use enterBasicBlockEnd and walk backwards through the block

[nemanjai]

In D133103#4512023, @arsenm wrote:

Kill flags should be removed. You should switch to reverse liveness which does not rely on accurate kill flags

I'm not sure I follow. Are you suggesting that we remove all kill flags in this pass? We're really only fixing them up to appease the verifier rather than because anything in the PPC back end relies on the flags.

[nemanjai]

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

425

This will be done in a follow-up patch.

llvm/lib/Target/PowerPC/PPCInstrInfo.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H
 
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "PPCRegisterInfo.h"
+#include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 
 #define GET_INSTRINFO_HEADER
 #include "PPCGenInstrInfo.inc"
 
 namespace llvm {
 
 // Instructions that have an immediate form might be convertible to that
public:
 
   // Return true if the register is zero-extended from 32 to 64 bits.
   bool isZeroExtended(const unsigned Reg,
                       const MachineRegisterInfo *MRI) const {
     return isSignOrZeroExtended(Reg, 0, MRI).second;
   }
 
   bool convertToImmediateForm(MachineInstr &MI,
+                              SmallSet<Register, 4> &RegsToUpdate,
                               MachineInstr **KilledDef = nullptr) const;
   bool foldFrameOffset(MachineInstr &MI) const;
   bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const;
   bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
   bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
   bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
                                     unsigned &XFormOpcode,
                                     int64_t &OffsetOfImmInstr,
                                     ImmInstrInfo &III) const;
   bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
                              MachineInstr *&ADDIMI, int64_t &OffsetAddi,
                              int64_t OffsetImm) const;
 
-  /// Fixup killed/dead flag for register \p RegNo between instructions [\p
-  /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate
-  /// register killed/dead flags semantics, this function can be called to fix
-  /// up. Before calling this function,
-  /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
-  /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
-  ///    and possible definition for \p RegNo is \p StartMI or \p EndMI. For
-  ///    pre-RA cases, definition may be \p StartMI through COPY, \p StartMI
-  ///    will be adjust to true definition.
-  /// 3. We can do accurate fixup for the case when all instructions between
-  ///    [\p StartMI, \p EndMI] are in same basic block.
-  /// 4. For the case when \p StartMI and \p EndMI are not in same basic block,
-  ///    we conservatively clear kill flag for all uses of \p RegNo for pre-RA
-  ///    and for post-RA, we give an assertion as without reaching definition
-  ///    analysis post-RA, \p StartMI and \p EndMI are hard to keep right.
-  void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
-                         unsigned RegNo) const;
   void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const;
   void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo,
                                   int64_t Imm) const;
 
   bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
                        bool PostRA) const;
 
   // In PostRA phase, try to find instruction defines \p Reg before \p MI.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

 #include "PPCInstrBuilder.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineCombinerPattern.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const {
   LLVM_DEBUG(SrcMI->dump());
 
   const MCInstrDesc &NewDesc = get(NewOpC);
   SrcMI->setDesc(NewDesc);
   MachineInstrBuilder(*SrcMI->getParent()->getParent(), SrcMI)
       .addReg(CRReg, RegState::ImplicitDefine);
   SrcMI->clearRegisterDeads(CRReg);
 
-  // Fix up killed/dead flag for SrcReg after transformation.
-  if (SrcRegHasOtherUse || CmpMI.getOperand(1).isKill())
-    fixupIsDeadOrKill(SrcMI, &CmpMI, SrcReg);
-
   assert(SrcMI->definesRegister(PPC::CR0) &&
          "Record-form instruction does not define cr0?");
 
   LLVM_DEBUG(dbgs() << "with: ");
   LLVM_DEBUG(SrcMI->dump());
   LLVM_DEBUG(dbgs() << "Delete dead instruction: ");
   LLVM_DEBUG(CmpMI.dump());
   return true;

 ArrayRef<unsigned> PPCInstrInfo::getStoreOpcodesForSpillArray() const {
   return {StoreSpillOpcodesArray[getSpillTarget()], SOK_LastOpcodeSpill};
 }
 
 ArrayRef<unsigned> PPCInstrInfo::getLoadOpcodesForSpillArray() const {
   return {LoadSpillOpcodesArray[getSpillTarget()], SOK_LastOpcodeSpill};
 }
 
-void PPCInstrInfo::fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI,
-                                     unsigned RegNo) const {
-  // Conservatively clear kill flag for the register if the instructions are in
-  // different basic blocks and in SSA form, because the kill flag may no longer
-  // be right. There is no need to bother with dead flags since defs with no
-  // uses will be handled by DCE.
-  MachineRegisterInfo &MRI = StartMI->getParent()->getParent()->getRegInfo();
-  if (MRI.isSSA() && (StartMI->getParent() != EndMI->getParent())) {
-    MRI.clearKillFlags(RegNo);
-    return;
-  }
-
-  // Instructions between [StartMI, EndMI] should be in same basic block.
-  assert((StartMI->getParent() == EndMI->getParent()) &&
-         "Instructions are not in same basic block");
-
-  // If before RA, StartMI may be def through COPY, we need to adjust it to the
-  // real def. See function getForwardingDefMI.
-  if (MRI.isSSA()) {
-    bool Reads, Writes;
-    std::tie(Reads, Writes) = StartMI->readsWritesVirtualRegister(RegNo);
-    if (!Reads && !Writes) {
-      assert(Register::isVirtualRegister(RegNo) &&
-             "Must be a virtual register");
-      // Get real def and ignore copies.
-      StartMI = MRI.getVRegDef(RegNo);
-    }
-  }
-
-  bool IsKillSet = false;
-
-  auto clearOperandKillInfo = [=] (MachineInstr &MI, unsigned Index) {
-    MachineOperand &MO = MI.getOperand(Index);
-    if (MO.isReg() && MO.isUse() && MO.isKill() &&
-        getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
-      MO.setIsKill(false);
-  };
-
-  // Set killed flag for EndMI.
-  // No need to do anything if EndMI defines RegNo.
-  int UseIndex =
-      EndMI->findRegisterUseOperandIdx(RegNo, false, &getRegisterInfo());
-  if (UseIndex != -1) {
-    EndMI->getOperand(UseIndex).setIsKill(true);
-    IsKillSet = true;
-    // Clear killed flag for other EndMI operands related to RegNo. In some
-    // upexpected cases, killed may be set multiple times for same register
-    // operand in same MI.
-    for (int i = 0, e = EndMI->getNumOperands(); i != e; ++i)
-      if (i != UseIndex)
-        clearOperandKillInfo(*EndMI, i);
-  }
-
-  // Walking the inst in reverse order (EndMI -> StartMI].
-  MachineBasicBlock::reverse_iterator It = *EndMI;
-  MachineBasicBlock::reverse_iterator E = EndMI->getParent()->rend();
-  // EndMI has been handled above, skip it here.
-  It++;
-  MachineOperand *MO = nullptr;
-  for (; It != E; ++It) {
-    // Skip insturctions which could not be a def/use of RegNo.
-    if (It->isDebugInstr() || It->isPosition())
-      continue;
-
-    // Clear killed flag for all It operands related to RegNo. In some
-    // upexpected cases, killed may be set multiple times for same register
-    // operand in same MI.
-    for (int i = 0, e = It->getNumOperands(); i != e; ++i)
-        clearOperandKillInfo(*It, i);
-
-    // If killed is not set, set killed for its last use or set dead for its def
-    // if no use found.
-    if (!IsKillSet) {
-      if ((MO = It->findRegisterUseOperand(RegNo, false, &getRegisterInfo()))) {
-        // Use found, set it killed.
-        IsKillSet = true;
-        MO->setIsKill(true);
-        continue;
-      } else if ((MO = It->findRegisterDefOperand(RegNo, false, true,
-                                                  &getRegisterInfo()))) {
-        // No use found, set dead for its def.
-        assert(&*It == StartMI && "No new def between StartMI and EndMI.");
-        MO->setIsDead(true);
-        break;
-      }
-    }
-
-    if ((&*It) == StartMI)
-      break;
-  }
-  // Ensure RegMo liveness is killed after EndMI.
-  assert((IsKillSet || (MO && MO->isDead())) &&
-         "RegNo should be killed or dead");
-}
-
 // This opt tries to convert the following imm form to an index form to save an
 // add for stack variables.
 // Return false if no such pattern found.
 //
 // ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
 // ADD instr:  ToBeDeletedReg = ADD ToBeChangedReg(killed), ScaleReg
 // Imm instr:  Reg            = op OffsetImm, ToBeDeletedReg(killed)
 //
if (isInt<16>(OffsetAddi + OffsetImm))
     return true;
   return false;
 }
 
 // If this instruction has an immediate form and one of its operands is a
 // result of a load-immediate or an add-immediate, convert it to
 // the immediate form if the constant is in range.
 bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
+                                          SmallSet<Register, 4> &RegsToUpdate,
                                           MachineInstr **KilledDef) const {
   MachineFunction *MF = MI.getParent()->getParent();
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   bool PostRA = !MRI->isSSA();
   bool SeenIntermediateUse = true;
   unsigned ForwardingOperand = ~0U;
   MachineInstr *DefMI = getForwardingDefMI(MI, ForwardingOperand,
                                            SeenIntermediateUse);
   if (!DefMI)
     return false;
   assert(ForwardingOperand < MI.getNumOperands() &&
          "The forwarding operand needs to be valid at this point");
   bool IsForwardingOperandKilled = MI.getOperand(ForwardingOperand).isKill();
   bool KillFwdDefMI = !SeenIntermediateUse && IsForwardingOperandKilled;
   if (KilledDef && KillFwdDefMI)
     *KilledDef = DefMI;
 
+  // Conservatively add defs from DefMI and defs/uses from MI to the set of
+  // registers that need their kill flags updated.
+  for (const MachineOperand &MO : DefMI->operands())
+    if (MO.isReg() && MO.isDef())
+      RegsToUpdate.insert(MO.getReg());
+  for (const MachineOperand &MO : MI.operands())
+    if (MO.isReg())
+      RegsToUpdate.insert(MO.getReg());
+
   // If this is a imm instruction and its register operands is produced by ADDI,
   // put the imm into imm inst directly.
   if (RI.getMappedIdxOpcForImmOpc(MI.getOpcode()) !=
           PPC::INSTRUCTION_LIST_END &&
       transformToNewImmFormFedByAdd(MI, *DefMI, ForwardingOperand))
     return true;
 
   ImmInstrInfo III;
   bool IsVFReg = MI.getOperand(0).isReg()
                      ? PPC::isVFRegister(MI.getOperand(0).getReg())
                      : false;
   bool HasImmForm = instrHasImmForm(MI.getOpcode(), IsVFReg, III, PostRA);
   // If this is a reg+reg instruction that has a reg+imm form,
bool PPCInstrInfo::simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
   MachineFunction *MF = MI.getParent()->getParent();
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   bool PostRA = !MRI->isSSA();
 
   int64_t Immediate = DefMI.getOperand(1).getImm();
   // Sign-extend to 64-bits.
   int64_t SExtImm = SignExtend64<16>(Immediate);
 
-  bool IsForwardingOperandKilled = MI.getOperand(OpNoForForwarding).isKill();
-  Register ForwardingOperandReg = MI.getOperand(OpNoForForwarding).getReg();
-
   bool ReplaceWithLI = false;
   bool Is64BitLI = false;
   int64_t NewImm = 0;
   bool SetCR = false;
   unsigned Opc = MI.getOpcode();
   switch (Opc) {
   default:
     return false;
if (ReplaceWithLI) {
     LII.Is64Bit = Is64BitLI;
     LII.SetCR = SetCR;
     // If we're setting the CR, the original load-immediate must be kept (as an
     // operand to ANDI_rec/ANDI8_rec).
     if (KilledDef && SetCR)
       *KilledDef = nullptr;
     replaceInstrWithLI(MI, LII);
 
-    // Fixup killed/dead flag after transformation.
-    // Pattern:
-    // ForwardingOperandReg = LI imm1
-    // y = op2 imm2, ForwardingOperandReg(killed)
-    if (IsForwardingOperandKilled)
-      fixupIsDeadOrKill(&DefMI, &MI, ForwardingOperandReg);
+    if (PostRA)
+      recomputeLivenessFlags(*MI.getParent());
 
     LLVM_DEBUG(dbgs() << "With:\n");
     LLVM_DEBUG(MI.dump());
     return true;
   }
   return false;
 }
 
bool PPCInstrInfo::transformToNewImmFormFedByAdd(
   // Check Imm.
   // Set ImmBase from imm instruction as base and get new Imm inside
   // isImmElgibleForForwarding.
   int64_t ImmBase = ImmOperandMI.getImm();
   int64_t Imm = 0;
   if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm, ImmBase))
     return false;
 
-  // Get killed info in case fixup needed after transformation.
-  unsigned ForwardKilledOperandReg = ~0U;
-  if (MI.getOperand(III.OpNoForForwarding).isKill())
-    ForwardKilledOperandReg = MI.getOperand(III.OpNoForForwarding).getReg();
-
   // Do the transform
   LLVM_DEBUG(dbgs() << "Replacing existing reg+imm instruction:\n");
   LLVM_DEBUG(MI.dump());
   LLVM_DEBUG(dbgs() << "Fed by:\n");
   LLVM_DEBUG(DefMI.dump());
 
   MI.getOperand(III.OpNoForForwarding).setReg(RegMO->getReg());
-  if (RegMO->isKill()) {
-    MI.getOperand(III.OpNoForForwarding).setIsKill(true);
-    // Clear the killed flag in RegMO. Doing this here can handle some cases
-    // that DefMI and MI are not in same basic block.
-    RegMO->setIsKill(false);
-  }
   MI.getOperand(III.ImmOpNo).setImm(Imm);
 
-  // FIXME: fix kill/dead flag if MI and DefMI are not in same basic block.
-  if (DefMI.getParent() == MI.getParent()) {
-    // Check if reg is killed between MI and DefMI.
-    auto IsKilledFor = [&](unsigned Reg) {
-      MachineBasicBlock::const_reverse_iterator It = MI;
-      MachineBasicBlock::const_reverse_iterator E = DefMI;
-      It++;
-      for (; It != E; ++It) {
-        if (It->killsRegister(Reg))
-          return true;
-      }
-      return false;
-    };
-
-    // Update kill flag
-    if (RegMO->isKill() || IsKilledFor(RegMO->getReg()))
-      fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
-    if (ForwardKilledOperandReg != ~0U)
-      fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
-  }
-
   LLVM_DEBUG(dbgs() << "With:\n");
   LLVM_DEBUG(MI.dump());
   return true;
 }
 
 // If an X-Form instruction is fed by an add-immediate and one of its operands
 // is the literal zero, attempt to forward the source of the add-immediate to
 // the corresponding D-Form instruction with the displacement coming from
 // the immediate being added.
 bool PPCInstrInfo::transformToImmFormFedByAdd(
     MachineInstr &MI, const ImmInstrInfo &III, unsigned OpNoForForwarding,
if (!isImmElgibleForForwarding(*ImmMO, DefMI, III, Imm))
     return false;
 
   bool IsFwdFeederRegKilled = false;
   bool SeenIntermediateUse = false;
   // Check if the RegMO can be forwarded to MI.
   if (!isRegElgibleForForwarding(*RegMO, DefMI, MI, KillDefMI,
                                  IsFwdFeederRegKilled, SeenIntermediateUse))
     return false;
 
-  // Get killed info in case fixup needed after transformation.
-  unsigned ForwardKilledOperandReg = ~0U;
   MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   bool PostRA = !MRI.isSSA();
-  if (PostRA && MI.getOperand(OpNoForForwarding).isKill())
-    ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
 
   // We know that, the MI and DefMI both meet the pattern, and
   // the Imm also meet the requirement with the new Imm-form.
   // It is safe to do the transformation now.
   LLVM_DEBUG(dbgs() << "Replacing indexed instruction:\n");
   LLVM_DEBUG(MI.dump());
   LLVM_DEBUG(dbgs() << "Fed by:\n");
   LLVM_DEBUG(DefMI.dump());
else {
     // Now add the rest back.
     for (auto &MO : MOps)
       MI.addOperand(MO);
   }
 
   // Update the opcode.
   MI.setDesc(get(III.ImmOpcode));
 
-  // Fix up killed/dead flag after transformation.
-  // Pattern 1:
-  // x = ADD KilledFwdFeederReg, imm
-  // n = opn KilledFwdFeederReg(killed), regn
-  // y = XOP 0, x
-  // Pattern 2:
-  // x = ADD reg(killed), imm
-  // y = XOP 0, x
-  if (IsFwdFeederRegKilled || RegMO->isKill())
-    fixupIsDeadOrKill(&DefMI, &MI, RegMO->getReg());
-  // Pattern 3:
-  // ForwardKilledOperandReg = ADD reg, imm
-  // y = XOP 0, ForwardKilledOperandReg(killed)
-  if (ForwardKilledOperandReg != ~0U)
-    fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
-
+  if (PostRA)
+    recomputeLivenessFlags(*MI.getParent());
   LLVM_DEBUG(dbgs() << "With:\n");
   LLVM_DEBUG(MI.dump());
 
   return true;
 }
 
 bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI,
                                              const ImmInstrInfo &III,
if (PostRA && III.ZeroIsSpecialOrig != III.ZeroIsSpecialNew) {
     if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) &&
         ConstantOpNo != III.ZeroIsSpecialNew)
       return false;
     if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) &&
         ConstantOpNo != PosForOrigZero)
       return false;
   }
 
-  // Get killed info in case fixup needed after transformation.
-  unsigned ForwardKilledOperandReg = ~0U;
-  if (PostRA && MI.getOperand(ConstantOpNo).isKill())
-    ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
-
   unsigned Opc = MI.getOpcode();
   bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec ||
                         Opc == PPC::SRW || Opc == PPC::SRW_rec ||
                         Opc == PPC::SLW8 || Opc == PPC::SLW8_rec ||
                         Opc == PPC::SRW8 || Opc == PPC::SRW8_rec;
   bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec ||
                         Opc == PPC::SRD || Opc == PPC::SRD_rec;
   bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec ||
if (III.ZeroIsSpecialNew) {
         const TargetRegisterClass *NewRC =
           MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?
           &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass;
         MRI.setRegClass(RegToModify, NewRC);
       }
     }
   }
 
-  // Fix up killed/dead flag after transformation.
-  // Pattern:
-  // ForwardKilledOperandReg = LI imm
-  // y = XOP reg, ForwardKilledOperandReg(killed)
-  if (ForwardKilledOperandReg != ~0U)
-    fixupIsDeadOrKill(&DefMI, &MI, ForwardKilledOperandReg);
+  if (PostRA)
+    recomputeLivenessFlags(*MI.getParent());
 
   LLVM_DEBUG(dbgs() << "With: ");
   LLVM_DEBUG(MI.dump());
   LLVM_DEBUG(dbgs() << "\n");
   return true;
 }
 
 const TargetRegisterClass *

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

 // the SSA phases, following VSX swap removal.  A pass of dead code
 // elimination follows this one for quick clean-up of any dead
 // instructions introduced here.  Although we could do this as callbacks
 // from the generic peephole pass, this would have a couple of bad
 // effects:  it might remove optimization opportunities for VSX swap
 // removal, and it would miss cleanups made possible following VSX
 // swap removal.
 //
+// NOTE: We run the verifier after this pass in Asserts/Debug builds so it
+//       is important to keep the code valid after transformations.
+//       Common causes of errors stem from violating the contract specified
+//       by kill flags. Whenever a transformation changes the live range of
+//       a register, that register should be added to the work list using
+//       addRegToUpdate(RegsToUpdate, <Reg>). Furthermore, if a transformation
+//       is changing the definition of a register (i.e. removing the single
+//       definition of the original vreg), it needs to provide a dummy
+//       definition of that register using addDummyDef(<MBB>, <Reg>).
 //===---------------------------------------------------------------------===//
 
 #include "MCTargetDesc/PPCMCTargetDesc.h"
 #include "MCTargetDesc/PPCPredicates.h"
 #include "PPC.h"
 #include "PPCInstrBuilder.h"
 #include "PPCInstrInfo.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/LiveVariables.h"
 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachinePostDominators.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/InitializePasses.h"

 namespace {
 
 struct PPCMIPeephole : public MachineFunctionPass {
 
   static char ID;
   const PPCInstrInfo *TII;
   MachineFunction *MF;
   MachineRegisterInfo *MRI;
+  LiveVariables *LV;
 
   PPCMIPeephole() : MachineFunctionPass(ID) {
     initializePPCMIPeepholePass(*PassRegistry::getPassRegistry());
   }
 
 private:
   MachineDominatorTree *MDT;
   MachinePostDominatorTree *MPDT;
   MachineBlockFrequencyInfo *MBFI;
   uint64_t EntryFreq;
+  SmallSet<Register, 16> RegsToUpdate;
 
   // Initialize class variables.
   void initialize(MachineFunction &MFParm);
 
   // Perform peepholes.
   bool simplifyCode();
 
   // Perform peepholes.
   bool eliminateRedundantCompare();
   bool eliminateRedundantTOCSaves(std::map<MachineInstr *, bool> &TOCSaves);
   bool combineSEXTAndSHL(MachineInstr &MI, MachineInstr *&ToErase);
-  bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI);
+  bool emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
+                                       MachineInstr *&ToErase);
   void UpdateTOCSaves(std::map<MachineInstr *, bool> &TOCSaves,
                       MachineInstr *MI);
 
+  // A number of transformations will eliminate the definition of a register
+  // as all of its uses will be removed. However, this leaves a register
+  // without a definition for LiveVariables. Such transformations should
+  // use this function to provide a dummy definition of the register that
+  // will simply be removed by DCE.
+  void addDummyDef(MachineBasicBlock &MBB, MachineInstr *At, Register Reg) {
+    BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg);
+  }
+  void addRegToUpdateWithLine(Register Reg, int Line);
+  void convertUnprimedAccPHIs(const PPCInstrInfo *TII, MachineRegisterInfo *MRI,
+                              SmallVectorImpl<MachineInstr *> &PHIs,
+                              Register Dst);
+
 public:
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
+    AU.addRequired<LiveVariables>();
     AU.addRequired<MachineDominatorTree>();
     AU.addRequired<MachinePostDominatorTree>();
     AU.addRequired<MachineBlockFrequencyInfo>();
+    AU.addPreserved<LiveVariables>();
     AU.addPreserved<MachineDominatorTree>();
     AU.addPreserved<MachinePostDominatorTree>();
     AU.addPreserved<MachineBlockFrequencyInfo>();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
   // Main entry point for this pass.
   bool runOnMachineFunction(MachineFunction &MF) override {
     initialize(MF);
     // At this point, TOC pointer should not be used in a function that uses
     // PC-Relative addressing.
     assert((MF.getRegInfo().use_empty(PPC::X2) ||
             !MF.getSubtarget<PPCSubtarget>().isUsingPCRelativeCalls()) &&
            "TOC pointer used in a function using PC-Relative addressing!");
     if (skipFunction(MF.getFunction()))
       return false;
-    return simplifyCode();
+    bool Changed = simplifyCode();
+#ifndef NDEBUG
+    if (Changed)
+      MF.verify(this, "Error in PowerPC MI Peephole optimization, compile with "
+                      "-mllvm -disable-ppc-peephole");
+#endif
+    return Changed;
   }
 };
 
+#define addRegToUpdate(R) addRegToUpdateWithLine(R, __LINE__)
+void PPCMIPeephole::addRegToUpdateWithLine(Register Reg, int Line) {
+  if (!Register::isVirtualRegister(Reg))
+    return;
+  if (RegsToUpdate.insert(Reg).second)
+    LLVM_DEBUG(dbgs() << "Adding register: " << Register::virtReg2Index(Reg)
+                      << " on line " << Line
+                      << " for re-computation of kill flags\n");
+}
+
 // Initialize class variables.
 void PPCMIPeephole::initialize(MachineFunction &MFParm) {
   MF = &MFParm;
   MRI = &MF->getRegInfo();
   MDT = &getAnalysis<MachineDominatorTree>();
   MPDT = &getAnalysis<MachinePostDominatorTree>();
   MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
+  LV = &getAnalysis<LiveVariables>();
   EntryFreq = MBFI->getEntryFreq();
   TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
+  RegsToUpdate.clear();
   LLVM_DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n");
   LLVM_DEBUG(MF->dump());
 }
 
 static MachineInstr *getVRegDefOrNull(MachineOperand *Op,
                                       MachineRegisterInfo *MRI) {
   assert(Op && "Invalid Operand!");
   if (!Op->isReg())
static bool collectUnprimedAccPHIs(MachineRegisterInfo *MRI,
   }
   return true;
 }
 
 // This function changes the unprimed accumulator PHI nodes in the PHIs list to
 // primed accumulator PHI nodes. The list is traversed in reverse order to
 // change all the PHI operands of a PHI node before changing the node itself.
 // We keep a map to associate each changed PHI node to its non-changed form.
-static void convertUnprimedAccPHIs(const PPCInstrInfo *TII,
-                                   MachineRegisterInfo *MRI,
-                                   SmallVectorImpl<MachineInstr *> &PHIs,
-                                   Register Dst) {
+void PPCMIPeephole::convertUnprimedAccPHIs(
+    const PPCInstrInfo *TII, MachineRegisterInfo *MRI,
+    SmallVectorImpl<MachineInstr *> &PHIs, Register Dst) {
   DenseMap<MachineInstr *, MachineInstr *> ChangedPHIMap;
   for (MachineInstr *PHI : llvm::reverse(PHIs)) {
     SmallVector<std::pair<MachineOperand, MachineOperand>, 4> PHIOps;
     // We check if the current PHI node can be changed by looking at its
     // operands. If all the operands are either copies from primed
     // accumulators, implicit definitions or other unprimed accumulator
     // PHI nodes, we change it.
     for (unsigned PHIOp = 1, NumOps = PHI->getNumOperands(); PHIOp != NumOps;
for (MachineInstr *PHI : llvm::reverse(PHIs)) {
     // will be the destination register of the original copy (of the PHI def).
     // For all other PHI's in the list, we need to create another primed
     // accumulator virtual register as the PHI will no longer define the
     // unprimed accumulator.
     if (PHI != PHIs[0])
       AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass);
     MachineInstrBuilder NewPHI = BuildMI(
         *PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg);
-    for (auto RegMBB : PHIOps)
+    for (auto RegMBB : PHIOps) {
       NewPHI.add(RegMBB.first).add(RegMBB.second);
+      if (MRI->isSSA())
+        addRegToUpdate(RegMBB.first.getReg());
+    }
     ChangedPHIMap[PHI] = NewPHI.getInstr();
     LLVM_DEBUG(dbgs() << "Converting PHI: ");
     LLVM_DEBUG(PHI->dump());
     LLVM_DEBUG(dbgs() << "To: ");
     LLVM_DEBUG(NewPHI.getInstr()->dump());
   }
 }
 
if (ConvertRegReg) {
     bool SomethingChanged = false;
     do {
       NumFixedPointIterations++;
       SomethingChanged = false;
       for (MachineBasicBlock &MBB : *MF) {
         for (MachineInstr &MI : MBB) {
           if (MI.isDebugInstr())
             continue;
 
-          if (TII->convertToImmediateForm(MI)) {
-            // We don't erase anything in case the def has other uses. Let DCE
-            // remove it if it can be removed.
-            LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
-            LLVM_DEBUG(MI.dump());
-            NumConvertedToImmediateForm++;
-            SomethingChanged = true;
-            Simplified = true;
-            continue;
-          }
-        }
-      }
+          SmallSet<Register, 4> RRToRIRegsToUpdate;
+          if (!TII->convertToImmediateForm(MI, RRToRIRegsToUpdate))
+            continue;
+          for (Register R : RRToRIRegsToUpdate)
+            addRegToUpdate(R);
+          // The updated instruction may now have new register operands.
+          // Conservatively add them to recompute the flags as well.
+          for (const MachineOperand &MO : MI.operands())
+            if (MO.isReg())
+              addRegToUpdate(MO.getReg());
     } while (SomethingChanged && FixedPointRegToImm);
   }
 
+  // Since we are deleting this instruction, we need to run LiveVariables
+  // on any of its definitions that are marked as needing an update since
+  // we can't run LiveVariables on a deleted register. This only needs
+  // to be done for defs since uses will have their own defining
+  // instructions so we won't be running LiveVariables on a deleted reg.
+  auto recomputeLVForDyingInstr = [&]() {
+    if (RegsToUpdate.empty())
+      return;
+    for (MachineOperand &MO : ToErase->operands()) {
+      if (!MO.isReg() || !MO.isDef() || !RegsToUpdate.count(MO.getReg()))
+        continue;
+      Register RegToUpdate = MO.getReg();
+      RegsToUpdate.erase(RegToUpdate);
+      // If some transformation has introduced an additional definition of
+      // this register (breaking SSA), we can safely convert this def to
+      // a def of an invalid register as the instruction is going away.
+      if (!MRI->getUniqueVRegDef(RegToUpdate))
+        MO.setReg(PPC::NoRegister);
+      LV->recomputeForSingleDefVirtReg(RegToUpdate);
+    }
+  };
+
   for (MachineBasicBlock &MBB : *MF) {
     for (MachineInstr &MI : MBB) {
 
       // If the previous instruction was marked for elimination,
       // remove it now.
       if (ToErase) {
         LLVM_DEBUG(dbgs() << "Deleting instruction: ");
         LLVM_DEBUG(ToErase->dump());
+        recomputeLVForDyingInstr();
         ToErase->eraseFromParent();
         ToErase = nullptr;
       }
       // If a conditional trap instruction got optimized to an
       // unconditional trap, eliminate all the instructions after
       // the trap.
       if (EnableTrapOptimization && TrapOpt) {
         ToErase = &MI;
for (MachineInstr &MI : MBB) {
       case PPC::LI:
       case PPC::LI8: {
         // If we are materializing a zero, look for any use operands for which
         // zero means immediate zero. All such operands can be replaced with
         // PPC::ZERO.
         if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != 0)
           break;
         Register MIDestReg = MI.getOperand(0).getReg();
+        bool Folded = false;
         for (MachineInstr& UseMI : MRI->use_instructions(MIDestReg))
-          Simplified |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
+          Folded |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
         if (MRI->use_nodbg_empty(MIDestReg)) {
           ++NumLoadImmZeroFoldedAndRemoved;
           ToErase = &MI;
         }
+        if (Folded)
+          addRegToUpdate(MIDestReg);
+        Simplified |= Folded;
         break;
       }
       case PPC::STW:
       case PPC::STD: {
         MachineFrameInfo &MFI = MF->getFrameInfo();
         if (MFI.hasVarSizedObjects() ||
             (!MF->getSubtarget<PPCSubtarget>().isELFv2ABI() &&
              !MF->getSubtarget<PPCSubtarget>().isAIXABI()))
for (MachineInstr &MI : MBB) {
         if ((Immed == 0 || Immed == 3) &&
             (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) {
           LLVM_DEBUG(dbgs() << "Optimizing load-and-splat/splat "
                                "to load-and-splat/copy: ");
           LLVM_DEBUG(MI.dump());
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .add(MI.getOperand(1));
+          addRegToUpdate(MI.getOperand(1).getReg());
           ToErase = &MI;
           Simplified = true;
         }
 
         // If this is a splat or a swap fed by another splat, we
         // can replace it with a copy.
         if (DefOpc == PPC::XXPERMDI) {
           Register DefReg1 = DefMI->getOperand(1).getReg();
for (MachineInstr &MI : MBB) {
 
           if (DefImmed == 0 || DefImmed == 3) {
             LLVM_DEBUG(dbgs() << "Optimizing splat/swap or splat/splat "
                                  "to splat/copy: ");
             LLVM_DEBUG(MI.dump());
             BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                     MI.getOperand(0).getReg())
                 .add(MI.getOperand(1));
+            addRegToUpdate(MI.getOperand(1).getReg());
             ToErase = &MI;
             Simplified = true;
           }
 
           // If this is a splat fed by a swap, we can simplify modify
           // the splat to splat the other value from the swap's input
           // parameter.
           else if ((Immed == 0 || Immed == 3) && DefImmed == 2) {
             LLVM_DEBUG(dbgs() << "Optimizing swap/splat => splat: ");
             LLVM_DEBUG(MI.dump());
+            addRegToUpdate(MI.getOperand(1).getReg());
+            addRegToUpdate(MI.getOperand(2).getReg());
             MI.getOperand(1).setReg(DefReg1);
             MI.getOperand(2).setReg(DefReg2);
             MI.getOperand(3).setImm(3 - Immed);
+            addRegToUpdate(DefReg1);
+            addRegToUpdate(DefReg2);
             Simplified = true;
           }
 
           // If this is a swap fed by a swap, we can replace it
           // with a copy from the first swap's input.
           else if (Immed == 2 && DefImmed == 2) {
             LLVM_DEBUG(dbgs() << "Optimizing swap/swap => copy: ");
             LLVM_DEBUG(MI.dump());
+            addRegToUpdate(MI.getOperand(1).getReg());
             BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                     MI.getOperand(0).getReg())
                 .add(DefMI->getOperand(1));
+            addRegToUpdate(DefMI->getOperand(0).getReg());
+            addRegToUpdate(DefMI->getOperand(1).getReg());
             ToErase = &MI;
             Simplified = true;
           }
         } else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
                    DefOpc == PPC::XXPERMDIs &&
                    (DefMI->getOperand(2).getImm() == 0 ||
                     DefMI->getOperand(2).getImm() == 3)) {
           ToErase = &MI;
           Simplified = true;
           // Swap of a splat, convert to copy.
           if (Immed == 2) {
             LLVM_DEBUG(dbgs() << "Optimizing swap(splat) => copy(splat): ");
             LLVM_DEBUG(MI.dump());
             BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                     MI.getOperand(0).getReg())
                 .add(MI.getOperand(1));
+            addRegToUpdate(MI.getOperand(1).getReg());
             break;
           }
           // Splat fed by another splat - switch the output of the first
           // and remove the second.
           DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
           LLVM_DEBUG(MI.dump());
         } else if (Immed == 2 &&
                    (DefOpc == PPC::VSPLTB || DefOpc == PPC::VSPLTH ||
                     DefOpc == PPC::VSPLTW || DefOpc == PPC::XXSPLTW ||
                     DefOpc == PPC::VSPLTISB || DefOpc == PPC::VSPLTISH ||
                     DefOpc == PPC::VSPLTISW)) {
           // Swap of various vector splats, convert to copy.
           ToErase = &MI;
           Simplified = true;
           LLVM_DEBUG(dbgs() << "Optimizing swap(vsplt(is)?[b|h|w]|xxspltw) => "
                                "copy(vsplt(is)?[b|h|w]|xxspltw): ");
           LLVM_DEBUG(MI.dump());
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .add(MI.getOperand(1));
+          addRegToUpdate(MI.getOperand(1).getReg());
         } else if ((Immed == 0 || Immed == 3 || Immed == 2) &&
                    TII->isLoadFromConstantPool(DefMI)) {
           const Constant *C = TII->getConstantFromConstantPool(DefMI);
           if (C && C->getType()->isVectorTy() && C->getSplatValue()) {
             ToErase = &MI;
             Simplified = true;
             LLVM_DEBUG(dbgs()
                        << "Optimizing swap(splat pattern from constant-pool) "
                           "=> copy(splat pattern from constant-pool): ");
             LLVM_DEBUG(MI.dump());
             BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                     MI.getOperand(0).getReg())
                 .add(MI.getOperand(1));
+            addRegToUpdate(MI.getOperand(1).getReg());
           }
         }
         break;
       }
       case PPC::VSPLTB:
       case PPC::VSPLTH:
       case PPC::XXSPLTW: {
         unsigned MyOpcode = MI.getOpcode();
for (MachineInstr &MI : MBB) {
         // If the instruction[s] that feed this splat have already splat
         // the value, this splat is redundant.
         if (AlreadySplat) {
           LLVM_DEBUG(dbgs() << "Changing redundant splat to a copy: ");
           LLVM_DEBUG(MI.dump());
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .add(MI.getOperand(OpNo));
+          addRegToUpdate(MI.getOperand(OpNo).getReg());
           ToErase = &MI;
           Simplified = true;
         }
         // Splat fed by a shift. Usually when we align value to splat into
         // vector element zero.
         if (DefOpcode == PPC::XXSLDWI) {
           Register ShiftRes = DefMI->getOperand(0).getReg();
           Register ShiftOp1 = DefMI->getOperand(1).getReg();
           Register ShiftOp2 = DefMI->getOperand(2).getReg();
           unsigned ShiftImm = DefMI->getOperand(3).getImm();
           unsigned SplatImm =
               MI.getOperand(MyOpcode == PPC::XXSPLTW ? 2 : 1).getImm();
           if (ShiftOp1 == ShiftOp2) {
             unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
             if (MRI->hasOneNonDBGUse(ShiftRes)) {
               LLVM_DEBUG(dbgs() << "Removing redundant shift: ");
               LLVM_DEBUG(DefMI->dump());
               ToErase = DefMI;
             }
             Simplified = true;
             LLVM_DEBUG(dbgs() << "Changing splat immediate from " << SplatImm
                               << " to " << NewElem << " in instruction: ");
             LLVM_DEBUG(MI.dump());
-            MI.getOperand(1).setReg(ShiftOp1);
+            addRegToUpdate(MI.getOperand(OpNo).getReg());
+            addRegToUpdate(ShiftOp1);
+            MI.getOperand(OpNo).setReg(ShiftOp1);
             MI.getOperand(2).setImm(NewElem);
           }
         }
         break;
       }
       case PPC::XVCVDPSP: {
         // If this is a DP->SP conversion fed by an FRSP, the FRSP is redundant.
         Register TrueReg =
for (MachineInstr &MI : MBB) {
                   Use.getOperand(i).setReg(ConvReg1);
               LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n");
               LLVM_DEBUG(RoundInstr->dump());
               LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
               LLVM_DEBUG(MI.dump());
               LLVM_DEBUG(dbgs() << "Through instruction:\n");
               LLVM_DEBUG(DefMI->dump());
               RoundInstr->eraseFromParent();
+              addRegToUpdate(ConvReg1);
             }
           };
 
           // If the input to XVCVDPSP is a vector that was built (even
           // partially) out of FRSP's, the FRSP(s) can safely be removed
           // since this instruction performs the same operation.
           if (P1 != P2) {
             removeFRSPIfPossible(P1);
for (MachineInstr &MI : MBB) {
 
           if (SourceIsXForm && MIIs64Bit)
             Opc = PPC::LHAX8;
           else if (SourceIsXForm && !MIIs64Bit)
             Opc = PPC::LHAX;
           else if (MIIs64Bit)
             Opc = PPC::LHA8;
 
+          addRegToUpdate(NarrowReg);
+          addRegToUpdate(MI.getOperand(0).getReg());
+
+          // We are removing a definition of NarrowReg which will cause
+          // problems in AliveBlocks. Add an implicit def that will be
+          // removed so that AliveBlocks are updated correctly.
+          addDummyDef(MBB, &MI, NarrowReg);
           LLVM_DEBUG(dbgs() << "Zero-extending load\n");
           LLVM_DEBUG(SrcMI->dump());
           LLVM_DEBUG(dbgs() << "and sign-extension\n");
           LLVM_DEBUG(MI.dump());
           LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
           SrcMI->setDesc(TII->get(Opc));
           SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           ToErase = &MI;
for (MachineInstr &MI : MBB) {
           else if (SourceIsXForm && !MIIs64Bit)
             Opc = PPC::LWAX_32;
           else if (MIIs64Bit)
             Opc = PPC::LWA;
 
           if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32))
             break;
 
+          addRegToUpdate(NarrowReg);
+          addRegToUpdate(MI.getOperand(0).getReg());
+
+          // We are removing a definition of NarrowReg which will cause
+          // problems in AliveBlocks. Add an implicit def that will be
+          // removed so that AliveBlocks are updated correctly.
+          addDummyDef(MBB, &MI, NarrowReg);
           LLVM_DEBUG(dbgs() << "Zero-extending load\n");
           LLVM_DEBUG(SrcMI->dump());
           LLVM_DEBUG(dbgs() << "and sign-extension\n");
           LLVM_DEBUG(MI.dump());
           LLVM_DEBUG(dbgs() << "are merged into sign-extending load\n");
           SrcMI->setDesc(TII->get(Opc));
           SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           ToErase = &MI;
           Simplified = true;
           NumEliminatedSExt++;
         } else if (MI.getOpcode() == PPC::EXTSW_32_64 &&
                    TII->isSignExtended(NarrowReg, MRI)) {
           // We can eliminate EXTSW if the input is known to be already
           // sign-extended.
           LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
           Register TmpReg =
               MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass);
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF),
                   TmpReg);
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG),
                   MI.getOperand(0).getReg())
               .addReg(TmpReg)
               .addReg(NarrowReg)
               .addImm(PPC::sub_32);
           ToErase = &MI;
           Simplified = true;
           NumEliminatedSExt++;
         }
         break;
       }
       case PPC::RLDICL: {
         // We can eliminate RLDICL (e.g. for zero-extension)
         // if all bits to clear are already zero in the input.
for (MachineInstr &MI : MBB) {
 
         unsigned KnownZeroCount =
             getKnownLeadingZeroCount(SrcMI->getOperand(0).getReg(), TII, MRI);
         if (MI.getOperand(3).getImm() <= KnownZeroCount) {
           LLVM_DEBUG(dbgs() << "Removing redundant zero-extension\n");
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                   MI.getOperand(0).getReg())
               .addReg(SrcReg);
+          addRegToUpdate(SrcReg);
           ToErase = &MI;
           Simplified = true;
           NumEliminatedZExt++;
         }
         break;
       }
 
       // TODO: Any instruction that has an immediate form fed only by a PHI
for (MachineInstr &MI : MBB) {
         }
 
         // Replace ADD with COPY
         LLVM_DEBUG(dbgs() << "Optimizing ADD to COPY: ");
         LLVM_DEBUG(MI.dump());
         BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
                 MI.getOperand(0).getReg())
             .add(Op1);
+        addRegToUpdate(Op1.getReg());
+        addRegToUpdate(Op2.getReg());
         ToErase = &MI;
         Simplified = true;
         NumOptADDLIs++;
         break;
       }
       case PPC::RLDICR: {
-        Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
+        Simplified |= emitRLDICWhenLoweringJumpTables(MI, ToErase) ||
                       combineSEXTAndSHL(MI, ToErase);
         break;
       }
       case PPC::RLWINM:
       case PPC::RLWINM_rec:
       case PPC::RLWINM8:
       case PPC::RLWINM8_rec: {
+        // We might replace operand 1 of the instruction which will
+        // require we recompute kill flags for it.
+        Register OrigOp1Reg = MI.getOperand(1).isReg()
+                                  ? MI.getOperand(1).getReg()
+                                  : PPC::NoRegister;
         Simplified = TII->combineRLWINM(MI, &ToErase);
-        if (Simplified)
+        if (Simplified) {
+          addRegToUpdate(OrigOp1Reg);
+          if (MI.getOperand(1).isReg())
+            addRegToUpdate(MI.getOperand(1).getReg());
           ++NumRotatesCollapsed;
+        }
         break;
       }
       // We will replace TD/TW/TDI/TWI with an unconditional trap if it will
       // always trap, we will delete the node if it will never trap.
       case PPC::TDI:
       case PPC::TWI:
       case PPC::TD:
       case PPC::TW: {
for (MachineInstr &MI : MBB) {
              ((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) ||
             ((ImmOperand0 & 0x1) &&
              ((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) ||
             ((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) {
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP));
           TrapOpt = true;
         }
         // We will delete the MI if it will never trap.
         ToErase = &MI;
         Simplified = true;
         break;
       }
       }
     }
 
     // If the last instruction was marked for elimination,
     // remove it now.
     if (ToErase) {
+      recomputeLVForDyingInstr();
       ToErase->eraseFromParent();
       ToErase = nullptr;
     }
     // Reset TrapOpt to false at the end of the basic block.
     if (EnableTrapOptimization)
       TrapOpt = false;
   }
 
   // Eliminate all the TOC save instructions which are redundant.
   Simplified |= eliminateRedundantTOCSaves(TOCSaves);
   PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
   if (FI->mustSaveTOC())
     NumTOCSavesInPrologue++;
 
   // We try to eliminate redundant compare instruction.
   Simplified |= eliminateRedundantCompare();
 
+  // If we have made any modifications and added any registers to the set of
+  // registers for which we need to update the kill flags, do so by recomputing
+  // LiveVariables for those registers.
+  for (Register Reg : RegsToUpdate) {
+    if (!MRI->reg_empty(Reg))
+      LV->recomputeForSingleDefVirtReg(Reg);
+  }
   return Simplified;
 }
 
 // helper functions for eliminateRedundantCompare
 static bool isEqOrNe(MachineInstr *BI) {
   PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm();
   unsigned PredCond = PPC::getPredicateCondition(Pred);
   return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE);
else if (CMPI1->getOperand(2).isImm() && CMPI2->getOperand(2).isImm()) {
         continue;
     }
 
     LLVM_DEBUG(dbgs() << "Optimize two pairs of compare and branch:\n");
     LLVM_DEBUG(CMPI1->dump());
     LLVM_DEBUG(BI1->dump());
     LLVM_DEBUG(CMPI2->dump());
     LLVM_DEBUG(BI2->dump());
+    for (const MachineOperand &MO : CMPI1->operands())
+      if (MO.isReg())
+        addRegToUpdate(MO.getReg());
+    for (const MachineOperand &MO : CMPI2->operands())
+      if (MO.isReg())
+        addRegToUpdate(MO.getReg());
 
     // We adjust opcode, predicates and immediate as we determined above.
     if (NewOpCode != 0 && NewOpCode != CMPI1->getOpcode()) {
       CMPI1->setDesc(TII->get(NewOpCode));
     }
     if (NewPredicate1) {
       BI1->getOperand(0).setImm(NewPredicate1);
     }
if (IsPartiallyRedundant) {
           MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg());
           if (Inst->getParent() != &MBB2)
             continue;
 
           assert(Inst->getOpcode() == PPC::PHI &&
                  "We cannot support if an operand comes from this BB.");
           unsigned SrcReg = getIncomingRegForBlock(Inst, MBBtoMoveCmp);
           CMPI2->getOperand(I).setReg(SrcReg);
+          addRegToUpdate(SrcReg);
         }
       }
       auto I = MachineBasicBlock::iterator(MBBtoMoveCmp->getFirstTerminator());
       MBBtoMoveCmp->splice(I, &MBB2, MachineBasicBlock::iterator(CMPI2));
 
       DebugLoc DL = CMPI2->getDebugLoc();
       Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass);
       BuildMI(MBB2, MBB2.begin(), DL,
               TII->get(PPC::PHI), NewVReg)
         .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
         .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
       BI2->getOperand(1).setReg(NewVReg);
+      addRegToUpdate(NewVReg);
     }
     else {
       // We finally eliminate compare instruction in MBB2.
+      // We do not need to treat CMPI2 specially here in terms of re-computing
+      // live variables even though it is being deleted because:
+      // - It defines a register that has a single use (already checked in
+      // eligibleForCompareElimination())
+      // - The only user (BI2) is no longer using it so the register is dead (no
+      // def, no uses)
+      // - We do not attempt to recompute live variables for dead registers
       BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
       CMPI2->eraseFromParent();
     }
-    BI2->getOperand(1).setIsKill(true);
-    BI1->getOperand(1).setIsKill(false);
 
     LLVM_DEBUG(dbgs() << "into a compare and two branches:\n");
     LLVM_DEBUG(CMPI1->dump());
     LLVM_DEBUG(BI1->dump());
     LLVM_DEBUG(BI2->dump());
     if (IsPartiallyRedundant) {
       LLVM_DEBUG(dbgs() << "The following compare is moved into "
                         << printMBBReference(*MBBtoMoveCmp)
                         << " to handle partial redundancy.\n");
       LLVM_DEBUG(CMPI2->dump());
     }
-
     Simplified = true;
   }
 
   return Simplified;
 }
 
 // We miss the opportunity to emit an RLDIC when lowering jump tables
 // since ISEL sees only a single basic block. When selecting, the clear
 // and shift left will be in different blocks.
-bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI) {
+bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
+                                                    MachineInstr *&ToErase) {
   if (MI.getOpcode() != PPC::RLDICR)
     return false;
 
   Register SrcReg = MI.getOperand(1).getReg();
   if (!SrcReg.isVirtual())
     return false;
 
   MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
bool PPCMIPeephole::emitRLDICWhenLoweringJumpTables(MachineInstr &MI,
   LLVM_DEBUG(dbgs() << "Converting pair: ");
   LLVM_DEBUG(SrcMI->dump());
   LLVM_DEBUG(MI.dump());
 
   MI.setDesc(TII->get(PPC::RLDIC));
   MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
   MI.getOperand(2).setImm(NewSH);
   MI.getOperand(3).setImm(NewMB);
-  MI.getOperand(1).setIsKill(SrcMI->getOperand(1).isKill());
-  SrcMI->getOperand(1).setIsKill(false);
+  addRegToUpdate(MI.getOperand(1).getReg());
+  addRegToUpdate(SrcMI->getOperand(0).getReg());
 
   LLVM_DEBUG(dbgs() << "To: ");
   LLVM_DEBUG(MI.dump());
   NumRotatesCollapsed++;
   // If SrcReg has no non-debug use it's safe to delete its def SrcMI.
   if (MRI->use_nodbg_empty(SrcReg)) {
     assert(!SrcMI->hasImplicitDef() &&
            "Not expecting an implicit def with this instr.");
-    SrcMI->eraseFromParent();
+    ToErase = SrcMI;
   }
   return true;
 }
 
 // For case in LLVM IR
 // entry:
 //   %iconv = sext i32 %index to i64
 //   br i1 undef label %true, label %false
MachineInstr *NewInstr =
               MI.getOperand(0).getReg())
           .add(SrcMI->getOperand(1))
           .add(MOpSHMI);
   (void)NewInstr;
 
   LLVM_DEBUG(dbgs() << "TO: ");
   LLVM_DEBUG(NewInstr->dump());
   ++NumEXTSWAndSLDICombined;
   ToErase = &MI;
-  // SrcMI, which is extsw, is of no use now, erase it.
-  SrcMI->eraseFromParent();
+  // SrcMI, which is extsw, is of no use now, but we don't erase it here so we
+  // can recompute its kill flags. We run DCE immediately after this pass
+  // to clean up dead instructions such as this.
+  addRegToUpdate(NewInstr->getOperand(1).getReg());
+  addRegToUpdate(SrcMI->getOperand(0).getReg());
   return true;
 }
 
 } // end default namespace
 
 INITIALIZE_PASS_BEGIN(PPCMIPeephole, DEBUG_TYPE,
                       "PowerPC MI Peephole Optimization", false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineBlockFrequencyInfo)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(LiveVariables)
 INITIALIZE_PASS_END(PPCMIPeephole, DEBUG_TYPE,
                     "PowerPC MI Peephole Optimization", false, false)
 
 char PPCMIPeephole::ID = 0;
 FunctionPass*
 llvm::createPPCMIPeepholePass() { return new PPCMIPeephole(); }

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

 //===----------------------------------------------------------------------===//
 
 #include "PPC.h"
 #include "PPCInstrInfo.h"
 #include "PPCSubtarget.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 
bool runOnMachineFunction(MachineFunction &MF) override {
       // If the user wants to set the DSCR using command-line options,
       // load in the specified value at the start of main.
       if (DSCRValue.getNumOccurrences() > 0 && MF.getName().equals("main") &&
           MF.getFunction().hasExternalLinkage()) {
         DSCRValue = (uint32_t)(DSCRValue & 0x01FFFFFF); // 25-bit DSCR mask
         RegScavenger RS;
         MachineBasicBlock &MBB = MF.front();
         // Find an unused GPR according to register liveness
         RS.enterBasicBlock(MBB);
         unsigned InDSCR = RS.FindUnusedReg(&PPC::GPRCRegClass);
         if (InDSCR) {
           const PPCInstrInfo *TII =
               MF.getSubtarget<PPCSubtarget>().getInstrInfo();
           DebugLoc dl;
           MachineBasicBlock::iterator IP = MBB.begin(); // Insert Point
           // Copy the 32-bit DSCRValue integer into the GPR InDSCR using LIS and
           // ORI, then move to DSCR. If the requested DSCR value is contained
bool runOnMachineFunction(MachineFunction &MF) override {
               NumberOfSelfCopies++;
               LLVM_DEBUG(dbgs() << "Deleting self-copy instruction: ");
               LLVM_DEBUG(MI.dump());
               InstrsToErase.push_back(&MI);
               continue;
             }
           }
           MachineInstr *DefMIToErase = nullptr;
-          if (TII->convertToImmediateForm(MI, &DefMIToErase)) {
+          SmallSet<Register, 4> UpdatedRegs;
+          if (TII->convertToImmediateForm(MI, UpdatedRegs, &DefMIToErase)) {
             Changed = true;
             NumRRConvertedInPreEmit++;
             LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
             LLVM_DEBUG(MI.dump());
             if (DefMIToErase) {
               InstrsToErase.push_back(DefMIToErase);
             }
           }

llvm/test/CodeGen/PowerPC/O3-pipeline.ll

 ; CHECK-NEXT:       Machine Common Subexpression Elimination
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Machine Cycle Info Analysis
 ; CHECK-NEXT:       Machine code sinking
 ; CHECK-NEXT:       Peephole Optimizations
 ; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       PowerPC Reduce CR logical Operation
+; CHECK-NEXT:       Remove unreachable machine basic blocks
+; CHECK-NEXT:       Live Variable Analysis
 ; CHECK-NEXT:       MachineDominator Tree Construction
 ; CHECK-NEXT:       MachinePostDominator Tree Construction
 ; CHECK-NEXT:       Machine Natural Loop Construction
 ; CHECK-NEXT:       Machine Block Frequency Analysis
 ; CHECK-NEXT:       PowerPC MI Peephole Optimization
 ; CHECK-NEXT:       Remove dead machine instructions
 ; CHECK-NEXT:       Remove unreachable machine basic blocks
 ; CHECK-NEXT:       Live Variable Analysis

llvm/test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll

 true:
   %ptr = getelementptr inbounds i64, ptr %base, i64 %iconv
   %value = load i64, ptr %ptr, align 8
   ret i64 %value
 
 false:
   ret i64 %iconv
 }
+
+define hidden void @testCaller(i1 %incond) local_unnamed_addr align 2 nounwind {
+; CHECK-LABEL: testCaller:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mfocrf r12, 32
+; CHECK-NEXT:    stw r12, 8(r1)
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    std r0, 80(r1)
+; CHECK-NEXT:    std r30, 48(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    li r3, -1
+; CHECK-NEXT:    li r30, 0
+; CHECK-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-NEXT:    std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    b .LBB3_2
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB3_1: # %if.end116
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bl callee
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    mr r3, r29
+; CHECK-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-NEXT:    lwz r29, 0(r3)
+; CHECK-NEXT:    li r5, 0
+; CHECK-NEXT:    extsw r4, r29
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-NEXT:    addi r5, r5, -1
+; CHECK-NEXT:    cmpwi r5, 0
+; CHECK-NEXT:    bgt cr0, .LBB3_3
+; CHECK-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-NEXT:    #
+; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ld r5, 0(r3)
+; CHECK-NEXT:    sldi r4, r4, 2
+; CHECK-NEXT:    stw r3, 0(r3)
+; CHECK-NEXT:    stwx r30, r5, r4
+; CHECK-NEXT:    b .LBB3_1
+;
+; CHECK-BE-LABEL: testCaller:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    mfcr r12
+; CHECK-BE-NEXT:    stw r12, 8(r1)
+; CHECK-BE-NEXT:    mflr r0
+; CHECK-BE-NEXT:    stdu r1, -80(r1)
+; CHECK-BE-NEXT:    std r0, 96(r1)
+; CHECK-BE-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    andi. r3, r3, 1
+; CHECK-BE-NEXT:    li r3, -1
+; CHECK-BE-NEXT:    li r30, 0
+; CHECK-BE-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-BE-NEXT:    std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    b .LBB3_2
+; CHECK-BE-NEXT:    .p2align 4
+; CHECK-BE-NEXT:  .LBB3_1: # %if.end116
+; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    bl callee
+; CHECK-BE-NEXT:    nop
+; CHECK-BE-NEXT:    mr r3, r29
+; CHECK-BE-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-BE-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-BE-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-BE-NEXT:    lwz r29, 0(r3)
+; CHECK-BE-NEXT:    li r5, 0
+; CHECK-BE-NEXT:    extsw r4, r29
+; CHECK-BE-NEXT:    .p2align 5
+; CHECK-BE-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-BE-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-BE-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-BE-NEXT:    addi r5, r5, -1
+; CHECK-BE-NEXT:    cmpwi r5, 0
+; CHECK-BE-NEXT:    bgt cr0, .LBB3_3
+; CHECK-BE-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-BE-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    ld r5, 0(r3)
+; CHECK-BE-NEXT:    sldi r4, r4, 2
+; CHECK-BE-NEXT:    stw r3, 0(r3)
+; CHECK-BE-NEXT:    stwx r30, r5, r4
+; CHECK-BE-NEXT:    b .LBB3_1
+;
+; CHECK-P9-LABEL: testCaller:
+; CHECK-P9:       # %bb.0: # %entry
+; CHECK-P9-NEXT:    mfocrf r12, 32
+; CHECK-P9-NEXT:    mflr r0
+; CHECK-P9-NEXT:    stw r12, 8(r1)
+; CHECK-P9-NEXT:    stdu r1, -64(r1)
+; CHECK-P9-NEXT:    andi. r3, r3, 1
+; CHECK-P9-NEXT:    std r0, 80(r1)
+; CHECK-P9-NEXT:    std r30, 48(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT:    li r3, -1
+; CHECK-P9-NEXT:    li r30, 0
+; CHECK-P9-NEXT:    std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-P9-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-P9-NEXT:    b .LBB3_2
+; CHECK-P9-NEXT:    .p2align 4
+; CHECK-P9-NEXT:  .LBB3_1: # %if.end116
+; CHECK-P9-NEXT:    #
+; CHECK-P9-NEXT:    bl callee
+; CHECK-P9-NEXT:    nop
+; CHECK-P9-NEXT:    mr r3, r29
+; CHECK-P9-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-P9-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-P9-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-P9-NEXT:    lwz r29, 0(r3)
+; CHECK-P9-NEXT:    li r4, 0
+; CHECK-P9-NEXT:    .p2align 5
+; CHECK-P9-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-P9-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-P9-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-P9-NEXT:    addi r4, r4, -1
+; CHECK-P9-NEXT:    cmpwi r4, 0
+; CHECK-P9-NEXT:    bgt cr0, .LBB3_3
+; CHECK-P9-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-P9-NEXT:    #
+; CHECK-P9-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-P9-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-P9-NEXT:    #
+; CHECK-P9-NEXT:    ld r4, 0(r3)
+; CHECK-P9-NEXT:    extswsli r5, r29, 2
+; CHECK-P9-NEXT:    stw r3, 0(r3)
+; CHECK-P9-NEXT:    stwx r30, r4, r5
+; CHECK-P9-NEXT:    b .LBB3_1
+;
+; CHECK-P9-BE-LABEL: testCaller:
+; CHECK-P9-BE:       # %bb.0: # %entry
+; CHECK-P9-BE-NEXT:    mfcr r12
+; CHECK-P9-BE-NEXT:    mflr r0
+; CHECK-P9-BE-NEXT:    stw r12, 8(r1)
+; CHECK-P9-BE-NEXT:    stdu r1, -80(r1)
+; CHECK-P9-BE-NEXT:    andi. r3, r3, 1
+; CHECK-P9-BE-NEXT:    std r0, 96(r1)
+; CHECK-P9-BE-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-P9-BE-NEXT:    li r3, -1
+; CHECK-P9-BE-NEXT:    li r30, 0
+; CHECK-P9-BE-NEXT:    std r29, 56(r1) # 8-byte Folded Spill
+; CHECK-P9-BE-NEXT:    crmove 4*cr2+lt, gt
+; CHECK-P9-BE-NEXT:    b .LBB3_2
+; CHECK-P9-BE-NEXT:    .p2align 4
+; CHECK-P9-BE-NEXT:  .LBB3_1: # %if.end116
+; CHECK-P9-BE-NEXT:    #
+; CHECK-P9-BE-NEXT:    bl callee
+; CHECK-P9-BE-NEXT:    nop
+; CHECK-P9-BE-NEXT:    mr r3, r29
+; CHECK-P9-BE-NEXT:  .LBB3_2: # %cond.end.i.i
+; CHECK-P9-BE-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-P9-BE-NEXT:    # Child Loop BB3_3 Depth 2
+; CHECK-P9-BE-NEXT:    lwz r29, 0(r3)
+; CHECK-P9-BE-NEXT:    li r4, 0
+; CHECK-P9-BE-NEXT:    .p2align 5
+; CHECK-P9-BE-NEXT:  .LBB3_3: # %while.body5.i
+; CHECK-P9-BE-NEXT:    # Parent Loop BB3_2 Depth=1
+; CHECK-P9-BE-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-P9-BE-NEXT:    addi r4, r4, -1
+; CHECK-P9-BE-NEXT:    cmpwi r4, 0
+; CHECK-P9-BE-NEXT:    bgt cr0, .LBB3_3
+; CHECK-P9-BE-NEXT:  # %bb.4: # %while.cond12.preheader.i
+; CHECK-P9-BE-NEXT:    #
+; CHECK-P9-BE-NEXT:    bc 12, 4*cr2+lt, .LBB3_1
+; CHECK-P9-BE-NEXT:  # %bb.5: # %for.cond99.preheader
+; CHECK-P9-BE-NEXT:    #
+; CHECK-P9-BE-NEXT:    ld r4, 0(r3)
+; CHECK-P9-BE-NEXT:    extswsli r5, r29, 2
+; CHECK-P9-BE-NEXT:    stw r3, 0(r3)
+; CHECK-P9-BE-NEXT:    stwx r30, r4, r5
+; CHECK-P9-BE-NEXT:    b .LBB3_1
+entry:
+  br label %exit
+
+exit: ; preds = %entry
+  br label %cond.end.i.i
+
+cond.end.i.i:                                     ; preds = %if.end116, %exit
+  %CurrentState.0566 = phi i32 [ %CurrentState.2, %if.end116 ], [ -1, %exit ]
+  %0 = load i32, ptr poison, align 8
+  br label %while.body5.i
+
+while.cond12.preheader.i:                         ; preds = %while.body5.i
+  br i1 %incond, label %if.end116, label %for.cond99.preheader
+
+while.body5.i:                                    ; preds = %while.body5.i, %cond.end.i.i
+  %Test.012.i = phi i32 [ 0, %cond.end.i.i ], [ %dec10.i, %while.body5.i ]
+  %dec10.i = add nsw i32 %Test.012.i, -1
+  %cmp4.i = icmp slt i32 0, %dec10.i
+  br i1 %cmp4.i, label %while.body5.i, label %while.cond12.preheader.i
+
+for.cond99.preheader:                             ; preds = %while.cond12.preheader.i
+  %1 = load ptr, ptr poison, align 8
+  %conv103 = sext i32 %0 to i64
+  %arrayidx.i426 = getelementptr inbounds i32, ptr %1, i64 %conv103
+  store i32 0, ptr %arrayidx.i426, align 4
+  store i32 %CurrentState.0566, ptr poison, align 8
+  br label %if.end116
+
+if.end116:                                        ; preds = %for.cond99.preheader, %while.cond12.preheader.i
+  %CurrentState.2 = phi i32 [ %0, %while.cond12.preheader.i ], [ poison, %for.cond99.preheader ]
+  call fastcc void @callee()
+  br label %cond.end.i.i
+}
+declare dso_local fastcc void @callee() unnamed_addr align 2

llvm/test/CodeGen/PowerPC/convert-ri-addi-to-ri.mir

 # RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \
 # RUN:   -run-pass ppc-mi-peepholes -ppc-convert-rr-to-ri %s -o - | FileCheck %s
 
 ---
 name: foldNewDformStore
 # CHECK: name: foldNewDformStore
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x3
 
     %0:g8rc_and_g8rc_nox0 = COPY $x3
     %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
     %2:g8rc = LI8 0
-    ; CHECK: STD killed %2, 160, %0
+    ; CHECK: STD killed %2, 160, killed %0
     STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: foldNewDformStoreAlignNotMatch
 # CHECK: name: foldNewDformStoreAlignNotMatch
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x3
 
     %0:g8rc_and_g8rc_nox0 = COPY $x3
     %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 141
     %2:g8rc = LI8 0
-    ; CHECK: STD killed %2, 16, %1
+    ; CHECK: STD killed %2, 16, killed %1
     STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: foldNewDformStoreKilledFlag
 # CHECK: name: foldNewDformStoreKilledFlag
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     liveins: $x3
 
     %0:g8rc_and_g8rc_nox0 = COPY $x3
     %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144
     %2:g8rc = LI8 0
-    ; CHECK: STD %1, 0, %0
+    ; CHECK: STD killed %1, 0, %0
     STD %1:g8rc_and_g8rc_nox0, 0, killed %0:g8rc_and_g8rc_nox0
     ; CHECK: STD killed %2, 160, killed %0
     STD killed %2:g8rc, 16, %1:g8rc_and_g8rc_nox0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: foldNewDformPreferLIOperand
 # CHECK: name: foldNewDformPreferLIOperand

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-kill-flag.mir

body: |
   bb.0.entry:
     liveins: $x3, $f1, $x5
     $x3 = LI8 100
     STD $x3, $x5, 100
     ; CHECK: STD killed $x3, $x5, 100
     STFSX killed $f1, killed $x3, $x5
     ; CHECK: STFS killed $f1, 100, $x5
     STD killed $x5, $x5, 100
-    ; CHECK: STD killed $x5, $x5, 100
+    ; CHECK: STD killed $x5, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 # LI + OP -> LI, fixup killed/dead flag for $x3, find last use, set last use as
 # killed.
 name: testKillPassUpLI4
 # CHECK: name: testKillPassUpLI4
body: |
   bb.0.entry:
     liveins: $x3, $f1, $x5
     $x3 = ADDI8 $x5, 100
     STD $x3, $x5, 100
     ; CHECK: STD killed $x3, $x5, 100
     STFSX killed $f1, $zero8, killed $x3
     ; CHECK: STFS killed $f1, 100, $x5
     STD killed $x5, $x5, 100
-    ; CHECK: STD killed $x5, $x5, 100
+    ; CHECK: STD killed $x5, killed $x5, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 # ADD + XFORM -> DFORM, fixup killed/dead flag for register $x5, DFORM
 # instruction uses $x5 and no other kill uses, set it as killed in
 # DFORM instruction.
 name: testKillPassDownADD1
 # CHECK: name: testKillPassDownADD1
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $f1, $x5
     $x3 = ADDI8 killed $x5, 100
     ; CHECK: $x3 = ADDI8 $x5, 100
     STFSX killed $f1, $zero8, $x3
     ; CHECK: STFS killed $f1, 100, killed $x5
     STD killed $x3, $x3, 100
-    ; CHECK: STD killed $x3, $x3, 100
+    ; CHECK: STD killed $x3, killed $x3, 100
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 # ADD + XFORM -> DFORM, fixup killed/dead flag for register $x5, DFORM
 # instruction uses $x5 and there is one kill use, set $x5 as killed in
 # DFORM instruction and clear the other kill use killed flag.
 name: testKillPassDownADD2

 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $x5
     $x3 = ADDI8 $x5, 100
     $x3 = LDX $zero8, killed $x3
     ; CHECK: $x3 = LD 100, $x5
     STD killed $x5, $x5, 100
-    ; CHECK: STD killed $x5, $x5, 100
+    ; CHECK: STD killed $x5, killed $x5, 100
     STD killed $x3, $x3, 200
-    ; CHECK: STD killed $x3, $x3, 200
+    ; CHECK: STD killed $x3, killed $x3, 200
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 # ADD + XFORM -> DFORM, fixup killed/dead flag for both register $x5 and $x3,
 # DFORM instruction uses $x5 and there is one kill use, set $x5 as killed in
 # DFORM instruction and clear the other kill use killed flag. Find last use for
 # $x3, set last use as killed.
 name: testKillPassDownADD4
 # CHECK: name: testKillPassDownADD4
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $f1, $x5
     $x3 = ADDI8 $x5, 100
     STD killed $x5, $x5, 100
     ; CHECK: STD $x5, $x5, 100
     STD $x3, $x3, 200
-    ; CHECK: STD killed $x3, $x3, 200
+    ; CHECK: STD killed $x3, killed $x3, 200
     STFSX killed $f1, $zero8, killed $x3
     ; CHECK: STFS killed $f1, 100, killed $x5
     BLR8 implicit $lr8, implicit $rm
 
 ...

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

 constants:       
 body:             |
   bb.0.entry:
     liveins: $x3
   
     %0 = LI8 234
     %1 = COPY $x3
     %2 = RLWNM8 %1, %0, 20, 27
-    ; CHECK: RLWINM8 %1, 10, 20, 27
+    ; CHECK: RLWINM8 killed %1, 10, 20, 27
     ; CHECK-LATE: rlwinm 3, 3, 10, 20, 27
     $x3 = COPY %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testRLWNM_rec
 # CHECK-ALL: name: testRLWNM_rec
body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI 140
     %4 = RLDCL %0, killed %3, 0
-    ; CHECK: RLDICL %0, 12, 0
+    ; CHECK: RLDICL killed %0, 12, 0
     ; CHECK-LATE: rotldi 3, 3, 12
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testRLDCL_rec
 # CHECK-ALL: name: testRLDCL_rec
body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI 300
     %4 = RLDCR %0, killed %3, 0
-    ; CHECK: RLDICR %0, 44, 0
+    ; CHECK: RLDICR killed %0, 44, 0
     ; CHECK-LATE: rldicr 3, 3, 44, 0
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testRLDCR_rec
 # CHECK-ALL: name: testRLDCR_rec

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 400
     %3 = SRD %0, killed %2
-    ; CHECK: RLDICL %0, 48, 16
+    ; CHECK: RLDICL killed %0, 48, 16
     ; CHECK-LATE: rldicl 3, 3, 48, 16
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testSRD_rec
 # CHECK-ALL: name: testSRD_rec

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI -44
     %3 = SRAD %0, killed %2, implicit-def dead $carry
-    ; CHECK: SRAD %0, killed %2, implicit-def dead $carry
+    ; CHECK: SRAD killed %0, killed %2, implicit-def dead $carry
     ; CHECK-LATE: srad 3, 3, 4
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testSRAD_rec
 # CHECK-ALL: name: testSRAD_rec

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 68
     %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRAD_rec killed %0, killed %2, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: srad. 3, 3, 5
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = LI8 33
     %0 = COPY $x3
     %2 = ADD8 %0, %1
     %3 = ADD8 killed %1, killed %2
-    ; CHECK: ADDI8 %0, 33
+    ; CHECK: ADDI8 killed %0, 33
     ; CHECK: ADDI8 killed %2, 33
     ; CHECK-LATE: addi 3, 3, 33
     ; CHECK-LATE: addi 3, 3, 33
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
 
     %3 = COPY $x6
     %2 = COPY $x5
     %1 = COPY $x4
     %0 = COPY $x3
     %4 = COPY %0.sub_32
     %5 = LI 55
     %6 = ADDC %5, %4, implicit-def $carry
-    ; CHECK: ADDIC %4, 55, implicit-def $carry
+    ; CHECK: ADDIC killed %4, 55, implicit-def $carry
     ; CHECK-LATE: addic 3, 3, 55
     %7 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
     %8 = EXTSW_32_64 %6
     $x3 = COPY %8
     $x4 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
 
 ...
body:             |
   bb.0.entry:
     liveins: $x3, $x4, $x5, $x6
 
     %3 = COPY $x6
     %2 = COPY $x5
     %1 = COPY $x4
     %0 = LI8 777
     %4 = ADDC8 %2, %0, implicit-def $carry
-    ; CHECK: ADDIC8 %2, 777, implicit-def $carry
+    ; CHECK: ADDIC8 killed %2, 777, implicit-def $carry
     ; CHECK-LATE: addic 3, 5, 777
     %5 = ADDE8 %3, %1, implicit-def dead $carry, implicit $carry
     $x3 = COPY %4
     $x4 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = LI 433
     %0 = COPY $x3
     %2 = COPY %0.sub_32
     %3 = ADDC_rec %1, %2, implicit-def $cr0, implicit-def $carry
-    ; CHECK: ADDIC_rec %2, 433, implicit-def $cr0, implicit-def $carry
+    ; CHECK: ADDIC_rec killed %2, 433, implicit-def $cr0, implicit-def dead $carry
     ; CHECK-LATE: addic. 3, 3, 433
     %4 = COPY killed $cr0
     %5 = COPY %4.sub_eq
     %6 = LI8 0
     %7 = LI8 -1
     %8 = ISEL8 %7, %6, %5
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 89
     %2 = CMPDI %0, 87
     %4 = ISEL8 $zero8, %0, %2.sub_gt
-    ; CHECK: ADDI8 %1, 0
+    ; CHECK: ADDI8 killed %1, 0
     %5 = ADD8 killed %4, %1
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testCMPDI_F
 # CHECK-ALL: name: testCMPDI_F

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 87
     %2 = CMPDI %0, 87
     %4 = ISEL8 $zero8, %0, %2.sub_gt
-    ; CHECK: COPY %0
+    ; CHECK: COPY killed %0
     %5 = ADD8 killed %4, %1
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testCMPLD
 # CHECK-ALL: name: testCMPLD

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 65534
     %2 = CMPLDI %0, 65535
     %4 = ISEL8 $zero8, %0, %2.sub_gt
-    ; CHECK: COPY %0
+    ; CHECK: COPY killed %0
     %5 = ADD8 killed %4, %1
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testCMPW
 # CHECK-ALL: name: testCMPW
bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI -3
     %4 = CMPWI %3, 87
     %6 = ISEL $zero, %3, %4.sub_gt
-    ; CHECK: COPY %3
+    ; CHECK: COPY killed %3
     %7 = ADD4 killed %6, killed %2
     %8 = EXTSW_32_64 killed %7
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testCMPLW
bb.0.entry:
     %4 = INSERT_SUBREG %5, killed %3, 1
     %6 = RLDICL killed %4, 0, 32
     %7 = LBZX %0, killed %6 :: (load (s8) from %ir.arrayidx, !tbaa !3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -15
     %12,%17 = LBZUX %0, killed %11 :: (load (s8) from %ir.arrayidx3, !tbaa !3)
-    ; CHECK: LBZU -15, %0
+    ; CHECK: LBZU -15, killed %0
     ; CHECK-LATE: lbzu 5, -15(3)
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
     %16 = RLWINM8 killed %14, 0, 24, 31
     $x3 = COPY %16
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %4 = INSERT_SUBREG %5, killed %3, 1
     %6 = RLDIC killed %4, 1, 31
     %7 = LHZX %0, killed %6 :: (load (s16) from %ir.arrayidx, !tbaa !6)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 31440
     %12,%17 = LHZUX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
-    ; CHECK: LHZU 31440, %0
+    ; CHECK: LHZU 31440, killed %0
     ; CHECK-LATE: lhzu 5, 31440(3)
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
     %16 = RLWINM8 killed %14, 0, 16, 31
     $x3 = COPY %16
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %4 = INSERT_SUBREG %5, killed %3, 1
     %6 = RLDIC killed %4, 1, 31
     %7 = LHZX %0, killed %6 :: (load (s16) from %ir.arrayidx, !tbaa !6)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 882
     %12 = LHZX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
-    ; CHECK: LHZ 882, %0
+    ; CHECK: LHZ 882, killed %0
     ; CHECK-LATE: lhz 3, 882(3)
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
     %16 = RLWINM8 killed %14, 0, 16, 31
     $x3 = COPY %16
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %4 = INSERT_SUBREG %5, killed %3, 1
     %6 = RLDIC %4, 1, 31
     %7 = LHZX %0, killed %6 :: (load (s16) from %ir.arrayidx, !tbaa !6)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 400
     %12,%17 = LHAUX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
-    ; CHECK: LHAU 400, %0
+    ; CHECK: LHAU 400, killed %0
     ; CHECK-LATE: lhau 5, 400(3)
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
     %16 = EXTSH8 killed %14
     $x3 = COPY %16
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %7 = LHAX %0, killed %6 :: (load (s16) from %ir.arrayidx, !tbaa !6)
     ; CHECK: LHA -999, %0
     ; CHECK-LATE: lha 4, -999(3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 999
     %12 = LHAX %0, killed %11 :: (load (s16) from %ir.arrayidx3, !tbaa !6)
-    ; CHECK: LHA 999, %0
+    ; CHECK: LHA 999, killed %0
     ; CHECK-LATE: lha 3, 999(3)
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
     %16 = EXTSH8 killed %14
     $x3 = COPY %16
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %7,%17 = LWZUX %0, killed %6 :: (load (s32) from %ir.arrayidx, !tbaa !8)
     ; CHECK: LWZU 889, %0
     ; CHECK-LATE: lwzu {{[0-9]+}}, 889({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -2
     %12,%18 = LWZUX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !8)
-    ; CHECK: LWZU -2, %0
+    ; CHECK: LWZU -2, killed %0
     ; CHECK-LATE: lwzu {{[0-9]+}}, -2({{[0-9]+}})
     %13 = ADD4 killed %12, killed %7
     %15 = IMPLICIT_DEF
     %14 = INSERT_SUBREG %15, killed %13, 1
     %16 = RLDICL killed %14, 0, 32
     $x3 = COPY %16
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
bb.0.entry:
     %7,%14 = LDUX %0, killed %6 :: (load (s64) from %ir.arrayidx, !tbaa !10)
     ; CHECK: LDU 100, %0
     ; CHECK-LATE: ldu {{[0-9]+}}, 100({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 200
     %12,%15 = LDUX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !10)
-    ; CHECK: LDU 200, %0
+    ; CHECK: LDU 200, killed %0
     ; CHECK-LATE: ldu {{[0-9]+}}, 200({{[0-9]+}})
     %13 = ADD8 killed %12, killed %7
     $x3 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testLDX
bb.0.entry:
     %7 = LDX %0, killed %6 :: (load (s64) from %ir.arrayidx, !tbaa !10)
     ; CHECK: LD 120, %0
     ; CHECK-LATE: ld 4, 120(3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 280
     %12 = LDX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !10)
-    ; CHECK: LD 280, %0
+    ; CHECK: LD 280, killed %0
     ; CHECK-LATE: ld 3, 280(3)
     %13 = ADD8 killed %12, killed %7
     $x3 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testLFDUX
bb.0.entry:
     %7,%14 = LFDUX %0, killed %6 :: (load (s64) from %ir.arrayidx, !tbaa !12)
     ; CHECK: LFDU 440, %0
     ; CHECK-LATE: lfdu {{[0-9]+}}, 440({{[0-9]+}})
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 16
     %12,%15 = LFDUX %0, killed %11 :: (load (s64) from %ir.arrayidx3, !tbaa !12)
-    ; CHECK: LFDU 16, %0
+    ; CHECK: LFDU 16, killed %0
     ; CHECK-LATE: lfdu {{[0-9]+}}, 16({{[0-9]+}})
     %13 = FADD killed %7, killed %12, implicit $rm
     $f1 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $f1
 
 ...
 ---
 name:            testLFDX

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 72
     %3, %4 = LFSUX %0, killed %2 :: (load (s32) from %ir.arrayidx, !tbaa !14)
-    ; CHECK: LFSU 72, %0
+    ; CHECK: LFSU 72, killed %0
     ; CHECK-LATE: lfsu 0, 72(3)
     %5 = FCTIWUZ killed %3, implicit $rm
     %6 = ADDI8 %stack.4, 0
     STFIWX killed %5, $zero8, killed %6
     %7 = LWZ 0, %stack.4 :: (load (s32) from %stack.4)
     %8 = LFS 4, %4 :: (load (s32) from %ir.3, !tbaa !14)
     %10 = FCTIWUZ %8, implicit $rm
     %11 = ADDI8 %stack.1, 0
bb.0.entry:
     %7 = LFSX %0, killed %6 :: (load (s32) from %ir.arrayidx, !tbaa !14)
     ; CHECK: LFS 88, %0
     ; CHECK-LATE: lfs 0, 88(3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -88
     %12 = LFSX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !14)
-    ; CHECK: LFS -88, %0
+    ; CHECK: LFS -88, killed %0
     ; CHECK-LATE: lfs 1, -88(3)
     %13 = FADDS killed %7, killed %12, implicit $rm
     $f1 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $f1
 
 ...
 ---
 name:            testLXSDX
bb.0.entry:
     %7 = LXSDX %0, killed %6, implicit $rm :: (load (s64) from %ir.arrayidx, !tbaa !12)
     ; CHECK: DFLOADf64 100, %0
     ; CHECK-LATE: lfd 0, 100(3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -120
     %12 = LXSDX %0, killed %11, implicit $rm :: (load (s64) from %ir.arrayidx3, !tbaa !12)
-    ; CHECK: DFLOADf64 -120, %0
+    ; CHECK: DFLOADf64 -120, killed %0
     ; CHECK-LATE: lfd 1, -120(3)
     %13 = XSADDDP killed %7, killed %12, implicit $rm
     $f1 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $f1
 
 ...
 ---
 name:            testLXSSPX
bb.0.entry:
     %7 = LXSSPX %0, killed %6 :: (load (s32) from %ir.arrayidx, !tbaa !14)
     ; CHECK: DFLOADf32 96, %0
     ; CHECK-LATE: lfs 0, 96(3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -92
     %12 = LXSSPX %0, killed %11 :: (load (s32) from %ir.arrayidx3, !tbaa !14)
-    ; CHECK: DFLOADf32 -92, %0
+    ; CHECK: DFLOADf32 -92, killed %0
     ; CHECK-LATE: lfs 1, -92(3)
     %13 = XSADDSP killed %7, killed %12
     $f1 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $f1
 
 ...
 ---
 name:            testLXVX
bb.0.entry:
     %7 = LXVX %0, killed %6 :: (load (s128) from %ir.arrayidx, !tbaa !3)
     ; CHECK: LXV 32, %0
     ; CHECK-LATE: lxv 34, 32(3)
     %8 = ADDI %2, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -16
     %12 = LXVX %0, killed %11 :: (load (s128) from %ir.arrayidx3, !tbaa !3)
-    ; CHECK: LXV -16, %0
+    ; CHECK: LXV -16, killed %0
     ; CHECK-LATE: lxv 35, -16(3)
     %13 = VADDUWM killed %12, killed %7
     $v2 = COPY %13
     BLR8 implicit $lr8, implicit $rm, implicit $v2
 
 ...
 ---
 name:            testOR

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI 99
     %3 = COPY %1.sub_32
     %2 = OR %0, %3
-    ; CHECK: ORI %3, 99
+    ; CHECK: ORI killed %3, 99
     ; CHECK-LATE: ori 3, 4, 99
     $x3 = EXTSW_32_64 %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testOR8
 # CHECK-ALL: name: testOR8

 constants:
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 777
     %2 = OR8 %1, %0
-    ; CHECK: ORI8 %1, 777
+    ; CHECK: ORI8 killed %1, 777
     ; CHECK-LATE: ori 3, 4, 777
     $x3 = COPY %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testORI
 # CHECK-ALL: name: testORI
body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI 14
     %4 = RLDCL %0, killed %3, 0
-    ; CHECK: RLDICL %0, 14, 0
+    ; CHECK: RLDICL killed %0, 14, 0
     ; CHECK-LATE: rotldi 3, 3, 14
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testRLDCL_rec
 # CHECK-ALL: name: testRLDCL_rec
body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = COPY %1.sub_32
     %3 = LI 0
     %4 = RLDCR %0, killed %3, 0
-    ; CHECK: RLDICR %0, 0, 0
+    ; CHECK: RLDICR killed %0, 0, 0
     ; CHECK-LATE: rldicr 3, 3, 0, 0
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testRLDCR_rec
 # CHECK-ALL: name: testRLDCR_rec

 constants:
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 -1
     %2 = RLDICL_rec %0, 53, 48, implicit-def $cr0
-    ; CHECK: ANDI8_rec %0, 65535
+    ; CHECK: ANDI8_rec killed %0, 65535
     ; CHECK-LATE: li 3, -1
     ; CHECK-LATE: andi. 3, 3, 65535
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 200
     %2 = RLDICL_rec %0, 61, 3, implicit-def $cr0
     ; CHECK: LI8 25
-    ; CHECK: ANDI8_rec %0, 25
+    ; CHECK: ANDI8_rec killed %0, 25
     ; CHECK-LATE-NOT: andi.
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---

 constants:
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 2
     %2 = RLDICL_rec %0, 32, 32, implicit-def $cr0
-    ; CHECK: ANDI8_rec %0, 0
+    ; CHECK: ANDI8_rec killed %0, 0
     ; CHECK-LATE: li 3, 2
     ; CHECK-LATE: andi. 3, 3, 0
     %3 = COPY killed $cr0
     %4 = ISEL8 %1, %2, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI8 -18
     %3 = RLWINM8_rec %2, 4, 20, 27, implicit-def $cr0
-    ; CHECK: ANDI8_rec %2, 3808
+    ; CHECK: ANDI8_rec killed %2, 3808
     ; CHECK-LATE: li 3, -18
     ; CHECK-LATE: andi. 3, 3, 3808
     %7 = COPY killed $cr0
     %6 = RLDICL killed %3, 0, 32
     %8 = ISEL8 %1, %6, %7.sub_eq
     $x3 = COPY %8
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 13
     %3 = SLD %0, killed %2
-    ; CHECK: RLDICR %0, 13, 50
+    ; CHECK: RLDICR killed %0, 13, 50
     ; CHECK-LATE: sldi 3, 3, 13
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testSLD_rec
 # CHECK-ALL: name: testSLD_rec

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 4
     %3 = SRD %0, killed %2
-    ; CHECK: RLDICL %0, 60, 4
+    ; CHECK: RLDICL killed %0, 60, 4
     ; CHECK-LATE: rldicl 3, 3, 60, 4
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testSRD_rec
 # CHECK-ALL: name: testSRD_rec

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 44
     %3 = SRAD %0, killed %2, implicit-def dead $carry
-    ; CHECK: SRADI %0, 44, implicit-def dead $carry
+    ; CHECK: SRADI killed %0, 44, implicit-def dead $carry
     ; CHECK-LATE: sradi 3, 3, 44
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testSRAD_rec
 # CHECK-ALL: name: testSRAD_rec

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = COPY $x3
     %2 = LI 61
     %3 = SRAD_rec %0, killed %2, implicit-def dead $carry, implicit-def $cr0
-    ; CHECK: SRADI_rec %0, 61, implicit-def dead $carry, implicit-def $cr0
+    ; CHECK: SRADI_rec killed %0, 61, implicit-def dead $carry, implicit-def $cr0
     ; CHECK-LATE: sradi. 3, 3, 61
     %4 = COPY killed $cr0
     %5 = ISEL8 %1, %3, %4.sub_eq
     $x3 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
bb.0.entry:
     %13 = STBUX %3, %0, killed %8 :: (store (s8) into %ir.arrayidx, !tbaa !3)
     ; CHECK: STBU %3, 966, %0
     ; CHECK-LATE: {{[0-9]+}}, 966({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 777
     %14 = STBUX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
-    ; CHECK: STBU %3, 777, %0
+    ; CHECK: STBU killed %3, 777, killed %0
     ; CHECK-LATE: {{[0-9]+}}, 777({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTBX
 # CHECK-ALL: name: testSTBX
 alignment:       16
bb.0.entry:
     STBX %3, %0, killed %8 :: (store (s8) into %ir.arrayidx, !tbaa !3)
     ; CHECK: STB %3, 975, killed %8
     ; CHECK-LATE: stb 4, 975(6)
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = RLDICL killed %10, 0, 32
     STBX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
-    ; CHECK: STB %3, 975, killed %12
+    ; CHECK: STB killed %3, 975, killed %12
     ; CHECK-LATE: stb 4, 975(5)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTHUX
 # CHECK-ALL: name: testSTHUX
 alignment:       16
bb.0.entry:
     %13 = STHUX %3, %0, killed %8 :: (store (s16) into %ir.arrayidx, !tbaa !6)
     ; CHECK: STHU %3, 32000, %0
     ; CHECK-LATE: sthu {{[0-9]+}}, 32000({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 -761
     %14 = STHUX %3, %0, killed %12 :: (store (s16) into %ir.arrayidx3, !tbaa !6)
-    ; CHECK: STHU %3, -761, %0
+    ; CHECK: STHU killed %3, -761, killed %0
     ; CHECK-LATE: sthu {{[0-9]+}}, -761({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTHX
 # CHECK-ALL: name: testSTHX
 alignment:       16
bb.0.entry:
     STHX %3, %0, killed %8 :: (store (s8) into %ir.arrayidx, !tbaa !3)
     ; CHECK: STH %3, 900, %0
     ; CHECK-LATE: sth {{[0-9]+}}, 900({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 -900
     STHX %3, %0, killed %12 :: (store (s8) into %ir.arrayidx3, !tbaa !3)
-    ; CHECK: STH %3, -900, %0
+    ; CHECK: STH killed %3, -900, killed %0
     ; CHECK-LATE: sth {{[0-9]+}}, -900({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTWUX
 # CHECK-ALL: name: testSTWUX
 alignment:       16
bb.0.entry:
     %13 = STWUX %3, %0, killed %8 :: (store (s32) into %ir.arrayidx, !tbaa !8)
     ; CHECK: STWU %3, 111, %0
     ; CHECK-LATE: stwu {{[0-9]+}}, 111({{[0-9]+}})
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 0
     %14 = STWUX %3, %0, killed %12 :: (store (s32) into %ir.arrayidx3, !tbaa !8)
-    ; CHECK: STWU %3, 0, %0
+    ; CHECK: STWU killed %3, 0, killed %0
     ; CHECK-LATE: stwu {{[0-9]+}}, 0({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTWX
 # CHECK-ALL: name: testSTWX
 alignment:       16
bb.0.entry:
     STWX %3, %0, killed %8 :: (store (s32) into %ir.arrayidx, !tbaa !8)
     ; CHECK: STW %3, 2, %0
     ; CHECK-LATE: stw 4, 2(3)
     %9 = ADDI %4, 2
     %11 = IMPLICIT_DEF
     %10 = INSERT_SUBREG %11, killed %9, 1
     %12 = LI8 99
     STWX %3, %0, killed %12 :: (store (s32) into %ir.arrayidx3, !tbaa !8)
-    ; CHECK: STW %3, 99, %0
+    ; CHECK: STW killed %3, 99, killed %0
     ; CHECK-LATE: stw 4, 99(3)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTDUX
 # CHECK-ALL: name: testSTDUX
 alignment:       16
bb.0.entry:
     %12 = STDUX %1, %0, killed %7 :: (store (s64) into %ir.arrayidx, !tbaa !10)
     ; CHECK: STDU %1, 444, %0
     ; CHECK-LATE: stdu {{[0-9]+}}, 444({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -8
     %13 = STDUX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !10)
-    ; CHECK: STDU %1, -8, %0
+    ; CHECK: STDU killed %1, -8, killed %0
     ; CHECK-LATE: stdu {{[0-9]+}}, -8({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTDX
 # CHECK-ALL: name: testSTDX
 alignment:       16
bb.0.entry:
     STDX %1, %0, killed %7 :: (store (s64) into %ir.arrayidx, !tbaa !10)
     ; CHECK: STD %1, 1000, killed %7
     ; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -900
     STDX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !10)
-    ; CHECK: STD %1, 1000, killed %11
+    ; CHECK: STD killed %1, 1000, killed %11
     ; CHECK-LATE: {{[0-9]+}}, 1000({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTFSX
 # CHECK-ALL: name: testSTFSX
 alignment:       16
bb.0.entry:
     STFSX %1, %0, killed %7 :: (store (s32) into %ir.arrayidx, !tbaa !14)
     ; CHECK: STFS %1, 400, %0
     ; CHECK-LATE: stfs 1, 400(3)
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -401
     STFSX %1, %0, killed %11 :: (store (s32) into %ir.arrayidx3, !tbaa !14)
-    ; CHECK: STFS %1, -401, %0
+    ; CHECK: STFS killed %1, -401, killed %0
     ; CHECK-LATE: stfs 1, -401(3)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTFSUX
 # CHECK-ALL: name: testSTFSUX
 alignment:       16
bb.0.entry:
     %12 = STFSUX %1, %0, killed %7 :: (store (s32) into %ir.arrayidx, !tbaa !14)
     ; CHECK: STFSU %1, 111, %0
     ; CHECK-LATE: stfsu {{[0-9]+}}, 111({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 987
     %13 = STFSUX %1, %0, killed %11 :: (store (s32) into %ir.arrayidx3, !tbaa !14)
-    ; CHECK: STFSU %1, 987, %0
+    ; CHECK: STFSU killed %1, 987, killed %0
     ; CHECK-LATE: stfsu {{[0-9]+}}, 987({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTFDX
 # CHECK-ALL: name: testSTFDX
 alignment:       16
bb.0.entry:
     STFDX %1, %0, killed %7 :: (store (s64) into %ir.arrayidx, !tbaa !12)
     ; CHECK: STFD %1, 876, %0
     ; CHECK-LATE: stfd 1, 876(3)
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 -873
     STFDX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !12)
-    ; CHECK: STFD %1, -873, %0
+    ; CHECK: STFD killed %1, -873, killed %0
     ; CHECK-LATE: stfd 1, -873(3)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTFDUX
 # CHECK-ALL: name: testSTFDUX
 alignment:       16
bb.0.entry:
     %12 = STFDUX %1, %0, killed %7 :: (store (s64) into %ir.arrayidx, !tbaa !12)
     ; CHECK: STFDU %1, -9038, %0
     ; CHECK-LATE: stfdu {{[0-9]+}}, -9038({{[0-9]+}})
     %8 = ADDI %3, 2
     %10 = IMPLICIT_DEF
     %9 = INSERT_SUBREG %10, killed %8, 1
     %11 = LI8 6477
     %13 = STFDUX %1, %0, killed %11 :: (store (s64) into %ir.arrayidx3, !tbaa !12)
-    ; CHECK: STFDU %1, 6477, %0
+    ; CHECK: STFDU killed %1, 6477, killed %0
     ; CHECK-LATE: stfdu {{[0-9]+}}, 6477({{[0-9]+}})
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTXSSPX
 # CHECK-ALL: name: testSTXSSPX
 alignment:       16
body:             |
   bb.0.entry:
     liveins: $x3, $f1, $x5
 
     %2 = COPY $x5
     %1 = COPY $f1
     %0 = COPY $x3
     %3 = LI8 444
     STXSSPX %1, %0, killed %3 :: (store (s32) into %ir.arrayidx, !tbaa !14)
-    ; CHECK: DFSTOREf32 %1, 444, %0
+    ; CHECK: DFSTOREf32 killed %1, 444, killed %0
     ; CHECK-LATE: stfs 1, 444(3)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTXSDX
 # CHECK-ALL: name: testSTXSDX
 alignment:       16
body:             |
   bb.0.entry:
     liveins: $x3, $f1, $x5
 
     %2 = COPY $x5
     %1 = COPY $f1
     %0 = COPY $x3
     %3 = LI8 4
     STXSDX %1, %0, killed %3, implicit $rm :: (store (s64) into %ir.arrayidx, !tbaa !12)
-    ; CHECK: DFSTOREf64 %1, 4, %0
+    ; CHECK: DFSTOREf64 killed %1, 4, killed %0
     ; CHECK-LATE: stfd 1, 4(3)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSTXVX
 # CHECK-ALL: name: testSTXVX
 alignment:       16
body:             |
   bb.0.entry:
     liveins: $x3, $v2, $x7
 
     %2 = COPY $x7
     %1 = COPY $v2
     %0 = LI8 16
     %3 = RLDICR %2, 4, 59
     STXVX %1, %0, killed %3 :: (store (s128) into %ir.arrayidx, !tbaa !3)
-    ; CHECK: STXV %1, 16, killed %3
+    ; CHECK: STXV killed %1, 16, killed %3
     ; CHECK-LATE: stxv 34, 16(4)
     BLR8 implicit $lr8, implicit $rm
 
 ...
 ---
 name:            testSUBFC
 # CHECK-ALL: name: testSUBFC
 alignment:       16
bb.0.entry:
     %3 = COPY $x6
     %2 = COPY $x5
     %1 = COPY $x4
     %6 = COPY %3.sub_32
     %7 = COPY %2.sub_32
     %8 = COPY %1.sub_32
     %0 = LI 55
     %4 = SUBFC %7, %0, implicit-def $carry
-    ; CHECK: SUBFIC %7, 55
+    ; CHECK: SUBFIC killed %7, 55
     ; CHECK-LATE: subfic 3, 5, 55
     %5 = SUBFE %6, %8, implicit-def dead $carry, implicit $carry
     $x3 = EXTSW_32_64 %4
     $x4 = EXTSW_32_64 %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
 
 ...
 ---
body:             |
   bb.0.entry:
     liveins: $x3, $x4, $x5, $x6
 
     %3 = COPY $x6
     %2 = COPY $x5
     %1 = COPY $x4
     %0 = LI8 7635
     %4 = SUBFC8 %2, %0, implicit-def $carry
-    ; CHECK: SUBFIC8 %2, 7635
+    ; CHECK: SUBFIC8 killed %2, 7635
     ; CHECK-LATE: subfic 3, 5, 7635
     %5 = SUBFE8 %3, %1, implicit-def dead $carry, implicit $carry
     $x3 = COPY %4
     $x4 = COPY %5
     BLR8 implicit $lr8, implicit $rm, implicit $x3, implicit $x4
 
 ...
 ---

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = LI 10101
     %0 = COPY $x3
     %3 = COPY %0.sub_32
     %2 = XOR %1, %3
-    ; CHECK: XORI %3, 10101
+    ; CHECK: XORI killed %3, 10101
     ; CHECK-LATE: 3, 3, 10101
     $x3 = EXTSW_32_64 %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testXOR8
 # CHECK-ALL: name: testXOR8

 constants:
 body:             |
   bb.0.entry:
     liveins: $x3, $x4
 
     %1 = COPY $x4
     %0 = LI8 5535
     %2 = XOR8 %1, %0
-    ; CHECK: XORI8 %1, 5535
+    ; CHECK: XORI8 killed %1, 5535
     ; CHECK-LATE: xori 3, 4, 5535
     $x3 = COPY %2
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...
 ---
 name:            testXORI
 # CHECK-ALL: name: testXORI

llvm/test/CodeGen/PowerPC/fixup-kill-dead-flag-crash.mir

 name: test2
 #CHECK : name : test2
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $r3
     %0:gprc = COPY $r3
     %1:gprc_and_gprc_nor0 = LI 0
-    ; CHECK: dead %2:gprc = COPY %1
+    ; CHECK-NOT: COPY %1
     %2:gprc = COPY %1:gprc_and_gprc_nor0
     ; CHECK: %3:gprc = LI 1
     %3:gprc = ORI killed %2:gprc, 1
-    ; CHECK: STW killed %3, %0, 100
+    ; CHECK: STW killed %3, killed %0, 100
     STW killed %3:gprc, %0:gprc, 100
     BLR8 implicit $lr8, implicit $rm
 ...

llvm/test/CodeGen/PowerPC/fold-rlwinm.mir

 # RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
 # RUN:   -run-pass ppc-mi-peepholes %s -o - -verify-machineinstrs | FileCheck %s
 
 ---
 name: testFoldRLWINM
 #CHECK: name: testFoldRLWINM
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 31
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMSrcFullMask1
 #CHECK: name: testFoldRLWINMSrcFullMask1
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 0, 31
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 0, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 0, 12
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMSrcFullMask2
 #CHECK: name: testFoldRLWINMSrcFullMask2
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 10, 9 
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 10, 9
     %3:gprc = RLWINM %2:gprc, 19, 10, 1
-    ; CHECK: %3:gprc = RLWINM %1, 14, 10, 1
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 10, 1
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMSrcWrapped
 #CHECK: name: testFoldRLWINMSrcWrapped
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 30, 10
     ; CHECK-NOT: %2:gprc = RLWINM %1, 27, 30, 10 
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM %1, 14, 11, 12
+    ; CHECK: %3:gprc = RLWINM killed %1, 14, 11, 12
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMUserWrapped
 #CHECK: name: testFoldRLWINMUserWrapped
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 10, 5, 31
-    ; CHECK: %2:gprc = RLWINM %1, 10, 5, 31
+    ; CHECK: %2:gprc = RLWINM killed %1, 10, 5, 31
     %3:gprc = RLWINM %2:gprc, 10, 30, 5
-    ; CHECK: %3:gprc = RLWINM %2, 10, 30, 5
+    ; CHECK: %3:gprc = RLWINM killed %2, 10, 30, 5
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMResultWrapped
 #CHECK: name: testFoldRLWINMResultWrapped
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
-    %2:gprc = RLWINM %1:gprc, 10, 20, 10
-    ; CHECK: %2:gprc = RLWINM %1, 10, 20, 10
-    %3:gprc = RLWINM %2:gprc, 10, 0, 31
-    ; CHECK: %3:gprc = RLWINM %2, 10, 0, 31
+    %2:gprc = RLWINM killed %1:gprc, 10, 20, 10
+    ; CHECK: %2:gprc = RLWINM killed %1, 10, 20, 10
+    %3:gprc = RLWINM killed %2:gprc, 10, 0, 31
+    ; CHECK: %3:gprc = RLWINM killed %2, 10, 0, 31
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMMultipleUses
 #CHECK: name: testFoldRLWINMMultipleUses
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM killed %1:gprc, 27, 5, 31
     ; CHECK: %2:gprc = RLWINM %1, 27, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
     ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
     STW %3:gprc, %2:gprc, 100 
-    ; CHECK: STW %3, %2, 100
+    ; CHECK: STW killed %3, killed %2, 100
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMToZero
 #CHECK: name: testFoldRLWINMToZero
 tracksRegLiveness: true
 body: |
   bb.0.entry:

 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 27, 5, 10
     ; CHECK-NOT: RLWINM %1,
     %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
-    ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+    ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMoToZeroSrcCanNotBeDeleted
 #CHECK: name: testFoldRLWINMoToZeroSrcCanNotBeDeleted
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
-    %2:gprc = RLWINM_rec %1:gprc, 27, 5, 10, implicit-def $cr0
-    ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def $cr0
-    %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
-    ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
+    %2:gprc = RLWINM_rec killed %1:gprc, 27, 5, 10, implicit-def $cr0
+    ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def dead $cr0
+    %3:gprc = RLWINM_rec killed %2:gprc, 8, 5, 10, implicit-def $cr0
+    ; CHECK: %3:gprc = ANDI_rec killed %1, 0, implicit-def dead $cr0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMInvalidMask
 #CHECK: name: testFoldRLWINMInvalidMask
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 20, 5, 31
-    ; CHECK: %2:gprc = RLWINM %1, 20, 5, 31
+    ; CHECK: %2:gprc = RLWINM killed %1, 20, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 10, 20
-    ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
+    ; CHECK: %3:gprc = RLWINM killed %2, 19, 10, 20
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMLIWrapMask
 #CHECK: name: testFoldRLWINMLIWrapMask
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:gprc = COPY $x3
     %1:gprc = LI 100
     ; CHECK: %2:gprc = LI 200
     %2:gprc = RLWINM %1:gprc, 1, 3, 2
     STW %2:gprc, %0:gprc, 100
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMAndANDI
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     ; CHECK-LABEL: name: testFoldRLWINMAndANDI
     ; CHECK: liveins: $x3
-    ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
-    ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
-    ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 4, 28, 31
-    ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec [[RLWINM]], 4, implicit-def $cr0
+    ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+    ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 4, 28, 31
+    ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec killed [[RLWINM]], 4, implicit-def dead $cr0
     ; CHECK: BLR8 implicit $lr8, implicit $rm
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 4, 28, 31
     %3:gprc = ANDI_rec %2:gprc, 4, implicit-def $cr0
     BLR8 implicit $lr8, implicit $rm
 ...

llvm/test/CodeGen/PowerPC/mi-peephole.mir

bb.0.entry:
     %0:g8rc = COPY $x3
     %2:g8rc = RLDICL killed %1, 0, 32
     %3:g8rc = RLDICR %2, 2, 61
     $x3 = COPY %3
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
   ; CHECK-LABEL: testRLDIC
   ; CHECK: bb.0.entry:
-  ; CHECK:   %1:g8rc = COPY $x4
-  ; CHECK:   %0:g8rc = COPY $x3
+  ; CHECK:   %1:g8rc = COPY killed $x4
+  ; CHECK:   %0:g8rc = COPY killed $x3
   ; CHECK:   %3:g8rc = RLDIC killed %1, 2, 30
-  ; CHECK:   $x3 = COPY %3
-  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
+  ; CHECK:   $x3 = COPY killed %3
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
 ...

llvm/test/CodeGen/PowerPC/opt-cmp-rec-postra.mir

 # RUN: llc -mtriple=powerpc64le-linux-gnu -stop-after ppc-pre-emit-peephole %s -o - -verify-machineinstrs | FileCheck %s
 
 ---
 name: test1
 # The cmp instr is optimized with the record form.
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
     successors: %bb.1(0x30000000), %bb.2(0x50000000)
     liveins: $x3, $x4
     renamable $x3 = OR8 killed renamable $x3, killed renamable $x4
     renamable $cr0 = CMPDI renamable $x3, 0, implicit killed $x3
     ; CHECK-LABEL: name: test1
-    ; CHECK: renamable $x3 = OR8_rec renamable $x3, killed renamable $x4, implicit-def $cr0
+    ; CHECK: renamable $x3 = OR8_rec killed renamable $x3, killed renamable $x4, implicit-def $cr0
     ; CHECK-NOT: CMPDI
     BCC 68, killed renamable $cr0, %bb.2
 
   bb.1:
     $x3 = LI8 102
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
   bb.2:

llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -O3 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 -run-pass=ppc-mi-peepholes \
 # RUN: -simplify-mir %s -o - | FileCheck %s
 ---
 name:            poc
 alignment:       16
 tracksRegLiveness: true
 body:             |
   ; CHECK-LABEL: name: poc
   ; CHECK: bb.0.entry:
-  ; CHECK:   successors: %bb.1, %bb.2
-  ; CHECK:   liveins: $x3, $x4, $x5, $x6
-  ; CHECK:   [[COPY:%[0-9]+]]:g8rc = COPY $x6
-  ; CHECK:   [[COPY1:%[0-9]+]]:g8rc = COPY $x5
-  ; CHECK:   [[COPY2:%[0-9]+]]:g8rc = COPY $x4
-  ; CHECK:   [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
-  ; CHECK:   [[ANDI8_rec_:%[0-9]+]]:g8rc = ANDI8_rec [[COPY1]], 1, implicit-def $cr0
-  ; CHECK:   [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
-  ; CHECK:   BCn killed [[COPY4]], %bb.2
-  ; CHECK:   B %bb.1
-  ; CHECK: bb.1:
-  ; CHECK:   liveins: $x3
-  ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
-  ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8_rec_]], 2, 61
-  ; CHECK:   $x3 = COPY [[RLDICR]]
-  ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
-  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
-  ; CHECK:   $x3 = COPY [[ADD8_]]
-  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
-  ; CHECK: bb.2:
-  ; CHECK:   [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
-  ; CHECK:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
-  ; CHECK:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
-  ; CHECK:   $x3 = COPY [[INSERT_SUBREG]]
-  ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
+  ; CHECK-NEXT:   successors: %bb.1, %bb.2
+  ; CHECK-NEXT:   liveins: $x3, $x4, $x5, $x6
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc = COPY killed $x6
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:g8rc = COPY killed $x5
+  ; CHECK-NEXT:   dead %2:g8rc = COPY killed $x4
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3
+  ; CHECK-NEXT:   [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY1]], 1, implicit-def dead $cr0, implicit-def $cr0gt
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:crbitrc = COPY killed $cr0gt
+  ; CHECK-NEXT:   BCn killed [[COPY3]], %bb.2
+  ; CHECK-NEXT:   B %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   liveins: $x3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW killed $x3
+  ; CHECK-NEXT:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR killed [[ANDI8_rec]], 2, 61
+  ; CHECK-NEXT:   dead $x3 = COPY killed [[RLDICR]]
+  ; CHECK-NEXT:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR killed [[EXTSW]], 2, 61
+  ; CHECK-NEXT:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 killed [[COPY2]], killed [[RLDICR1]]
+  ; CHECK-NEXT:   $x3 = COPY killed [[ADD8_]]
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG killed [[DEF]], killed [[COPY4]], %subreg.sub_32
+  ; CHECK-NEXT:   $x3 = COPY killed [[INSERT_SUBREG]]
+  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit killed $x3
   bb.0.entry:
     successors: %bb.1, %bb.2
     liveins: $x3, $x4, $x5, $x6
 
     %4:g8rc = COPY $x6
     %3:g8rc = COPY $x5
     %2:g8rc = COPY $x4
     %1:g8rc_and_g8rc_nox0 = COPY $x3

llvm/test/CodeGen/PowerPC/peephole-phi-acc.mir

registers:
   - { id: 47, class: vsrc, preferred-register: '' }
   - { id: 48, class: vsrprc, preferred-register: '' }
   - { id: 49, class: vsrprc, preferred-register: '' }
   - { id: 50, class: vsrc, preferred-register: '' }
   - { id: 51, class: vsrprc, preferred-register: '' }
   - { id: 52, class: vsrprc, preferred-register: '' }
   - { id: 53, class: vsrc, preferred-register: '' }
   - { id: 54, class: vsrprc, preferred-register: '' }
+  - { id: 55, class: crrc, preferred-register: '' }
 liveins:
   - { reg: '$x3', virtual-reg: '%7' }
   - { reg: '$v2', virtual-reg: '%8' }
   - { reg: '$x7', virtual-reg: '%9' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
bb.4.for.body.epil.preheader:
     successors: %bb.5(0x80000000)
 
     %34:gprc = nsw ADDI %0, -1
     %36:g8rc = IMPLICIT_DEF
     %35:g8rc = INSERT_SUBREG %36, killed %34, %subreg.sub_32
     %37:g8rc_and_g8rc_nox0 = RLDICL killed %35, 0, 32
     %38:g8rc = nuw nsw ADDI8 killed %37, 1
     MTCTR8loop killed %38, implicit-def dead $ctr8
+    B %bb.5
 
   bb.5.for.body.epil:
     successors: %bb.3(0x40000000), %bb.5(0x7c000000)
-    ; We check that no phi node is inserted in the block.
+    ; We check that no [u]acc phi node is inserted in the block.
     ; CHECK-LABEL: bb.{{[0-9]}}.for.body.epil:
     ; CHECK-NEXT: successors: %bb.{{[0-9]}}(0x{{[0-9a-f]+}}), %bb.{{[0-9]}}(0x{{[0-9a-f]+}})
-    ; CHECK-NEXT: {{ }}
-    ; CHECK-NEXT: %2:uaccrc = PHI
+    ; CHECK-NOT: uaccrc = PHI
+    ; CHECK-NOT: accrc = PHI
+    ; CHECK: %2:uaccrc = PHI
     ; CHECK-NEXT: %39:vsrc
     %2:uaccrc = PHI %1, %bb.4, %3, %bb.5
     %39:vsrc = COPY %8
     %41:accrc = COPY %2
     %40:accrc = XVF32GERPP %41, %39, %39
     %3:uaccrc = COPY %40
-    %15:crrc = CMPLWI %14, 7
-    BCC 12, killed %15, %bb.5
+    %55:crrc = CMPLWI %14, 7
+    BCC 12, killed %55, %bb.5
     B %bb.3
 
   bb.6.for.cond.cleanup:
     %4:uaccrc = PHI %11, %bb.8, %1, %bb.3
     %43:accrc = COPY %4
     %42:accrc = XXMFACC %43
     %44:vsrc = COPY %42.sub_vsx1
     %46:vsrprc = IMPLICIT_DEF

llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir

bb.0.entry:
     renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5
     STD $x4, $x4, 100
     BLR8 implicit $lr8, implicit $rm
 
   ; CHECK-LABEL: testRedundantLiImplicitReg
   ; CHECK: bb.0.entry:
   ; CHECK:   STW killed $r3, killed $x5, 100
   ; CHECK:   renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
-  ; CHECK:   STD killed $x4, $x4, 100
+  ; CHECK:   STD killed $x4, killed $x4, 100
   ; CHECK:   BLR8 implicit $lr8, implicit $rm

llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir

bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc = COPY $x4
     %0:g8rc = COPY $x3
     %2:gprc_and_gprc_nor0 = COPY %1.sub_32
     %3:gprc = LI -11
     %4:gprc_and_gprc_nor0 = RLWINM_rec %3, 2, 20, 31, implicit-def $cr0
     ; CHECK: LI 4055
-    ; CHECK: ANDI_rec %3, 4055
+    ; CHECK: ANDI_rec killed %3, 4055
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rlwinm.
     %5:crrc = COPY killed $cr0
     %6:gprc = ISEL %4, %2, %5.sub_eq
     %7:g8rc = EXTSW_32_64 killed %6
     $x3 = COPY %7
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 

 body:             |
   bb.0.entry:
     liveins: $x3, $x4
   
     %1:g8rc_and_g8rc_nox0 = COPY $x4
     %0:g8rc = LI8 -11
     %2:g8rc_and_g8rc_nox0  = RLDICL_rec %0, 2, 49, implicit-def $cr0
     ; CHECK: LI8 32727
-    ; CHECK: ANDI8_rec %0, 32727
+    ; CHECK: ANDI8_rec killed %0, 32727
     ; CHECK-LATE-NOT: andi.
     ; CHECK-LATE: rldicl.
     %3:crrc = COPY killed $cr0
     %4:g8rc = ISEL8 %2, %1, %3.sub_eq
     $x3 = COPY %4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
 ...

llvm/test/CodeGen/PowerPC/sext_elimination.mir

frameInfo:
   hasOpaqueSPAdjustment: false
   hasVAStart:      false
   hasMustTailInVarArgFunc: false
 body:             |
   bb.0.entry:
     liveins: $x3
 
     ; CHECK-LABEL: bb.0.entry:
-    ; CHECK: %4:g8rc = EXTSW_32_64 %3
+    ; CHECK: %4:g8rc = EXTSW_32_64 killed %3
     ; CHECK: %5:g8rc = INSERT_SUBREG %15, %1, %subreg.sub_32
-    ; CHECK: %7:g8rc = EXTSW_32_64 %6
+    ; CHECK: %7:g8rc = EXTSW_32_64 killed %6
     ; CHECK: %9:g8rc = INSERT_SUBREG %16, %8, %subreg.sub_32
     ; CHECK: %11:g8rc = INSERT_SUBREG %17, %10, %subreg.sub_32
-    ; CHECK: %14:g8rc = COPY %1
+    ; CHECK: %14:g8rc = COPY killed %13
 
     %0:g8rc_nox0 = COPY $x3
     %1:gprc, %2:g8rc_nox0 = LBZU 0, %0:g8rc_nox0
     %3:gprc = COPY %2:g8rc_nox0
     %4:g8rc = EXTSW_32_64 %3:gprc ; should not be eliminated
     %5:g8rc = EXTSW_32_64 %1:gprc
 
     %6:gprc = ORIS %1:gprc, 32768 ; should not be eliminated