[PowerPC][Peephole] Combine rldicl/rldicr and andi/andis after isel.

[Esme]

Summary

rldicl/rldicr can be eliminated if it's used to clear the high-order or low-order n bits and all bits cleared will be ANDed with 0 by andi/andis.
This patch optimizes such pattern.

[Esme]

1. Add optimizations for ANDIS_rec.
2. Add mir tests.

[qiucf]

LGTM, thanks

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1287

So we should guard this optimization before RA?

1313

A follow up: is it possible to get result 0 for the ANDI if we know RLDICR clears more than andi masks, or for the ANDIS, if we know RLDICL leading 0 count is not smaller than 48? There should be other combinations... And if we are going to handle this case, maybe SHSrc does not need to be 0.

[Esme]

Addressed comments -- handled more cases.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1287

Yes, I do guard it by

if (!TrueReg.isVirtual())
         break;

1313

Good point! In such scenarios we can eliminate ANDI_rec/ANDIS_rec instead of RLDICL/RLDICR and replace RLDICL/RLDICR with their record form RLDICL_rec/RLDICR_rec.

[Esme]

This patch passed Spec CPU2017 and bootstrap test.

[shchenz]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1299

If we know that all bits to AND are already zero, why not we can just delete the RLDICL/RLDICR, and set the operand 2 of ANDI/ANDIS to 0 to indicate that ANDI/ANDIS products 0 result here? To me that would be more simple and later pass may have the opportunity to do more optimizations based on the 0?

[Esme]

Thanks a lot to @shchenz !
Addressed comments.

[shchenz]

LGTM with one nit.

Thanks for improving this.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1299

nit: PatternResultZero & PatternRemoveRotate for Pattern1 and Pattern2?

[Esme]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

1247

JTBC. The patch was committed with addRegToUpdate() after rebasing on https://reviews.llvm.org/D133103.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineInstr &MI : MBB) {
         NumOptADDLIs++;
         break;
       }
       case PPC::RLDICR: {
         Simplified |= emitRLDICWhenLoweringJumpTables(MI, ToErase) ||
                       combineSEXTAndSHL(MI, ToErase);
         break;
       }
+      case PPC::ANDI_rec:
+      case PPC::ANDI8_rec:
+      case PPC::ANDIS_rec:
+      case PPC::ANDIS8_rec: {
+        Register TrueReg =
+            TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
+        if (!TrueReg.isVirtual() || !MRI->hasOneNonDBGUse(TrueReg))
+          break;
+
+        MachineInstr *SrcMI = MRI->getVRegDef(TrueReg);
+        if (!SrcMI)
+          break;
+
+        unsigned SrcOpCode = SrcMI->getOpcode();
+        if (SrcOpCode != PPC::RLDICL && SrcOpCode != PPC::RLDICR)
+          break;
+
+        uint64_t AndImm = MI.getOperand(2).getImm();
+        if (MI.getOpcode() == PPC::ANDIS_rec ||
+            MI.getOpcode() == PPC::ANDIS8_rec)
+          AndImm <<= 16;
+        uint64_t LZeroAndImm = llvm::countl_zero<uint64_t>(AndImm);
+        uint64_t RZeroAndImm = llvm::countr_zero<uint64_t>(AndImm);
+        uint64_t ImmSrc = SrcMI->getOperand(3).getImm();
+
+        // We can transfer `RLDICL/RLDICR + ANDI_rec/ANDIS_rec` to `ANDI_rec 0`
+        // if all bits to AND are already zero in the input.
+        bool PatternResultZero =
+            (SrcOpCode == PPC::RLDICL && (RZeroAndImm + ImmSrc > 63)) ||
+            (SrcOpCode == PPC::RLDICR && LZeroAndImm > ImmSrc);
+
+        // We can eliminate RLDICL/RLDICR if it's used to clear bits and all
+        // bits cleared will be ANDed with 0 by ANDI_rec/ANDIS_rec.
+        bool PatternRemoveRotate =
+            SrcMI->getOperand(2).getImm() == 0 &&
+            ((SrcOpCode == PPC::RLDICL && LZeroAndImm >= ImmSrc) ||
+             (SrcOpCode == PPC::RLDICR && (RZeroAndImm + ImmSrc > 63)));
+
+        if (!PatternResultZero && !PatternRemoveRotate)
+          break;
+
+        LLVM_DEBUG(dbgs() << "Combining pair: ");
+        LLVM_DEBUG(SrcMI->dump());
+        LLVM_DEBUG(MI.dump());
+        if (PatternResultZero)
+          MI.getOperand(2).setImm(0);
+        MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
+        addRegToUpdate(MI.getOperand(1).getReg());
+        LLVM_DEBUG(dbgs() << "To: ");
+        LLVM_DEBUG(MI.dump());
+        Simplified = true;
+        SrcMI->eraseFromParent();
+        break;
+      }
       case PPC::RLWINM:
       case PPC::RLWINM_rec:
       case PPC::RLWINM8:
       case PPC::RLWINM8_rec: {
         // We might replace operand 1 of the instruction which will
         // require we recompute kill flags for it.
         Register OrigOp1Reg = MI.getOperand(1).isReg()
                                   ? MI.getOperand(1).getReg()
for (MachineInstr &MI : MBB) {
         MachineInstr *LiMI1 = getVRegDefOrNull(&MI.getOperand(1), MRI);
         MachineInstr *LiMI2 = getVRegDefOrNull(&MI.getOperand(2), MRI);
         bool IsOperand2Immediate = MI.getOperand(2).isImm();
         // We can only do the optimization if we can get immediates
         // from both operands
         if (!(LiMI1 && (LiMI1->getOpcode() == PPC::LI ||
                         LiMI1->getOpcode() == PPC::LI8)))
           break;
         if (!IsOperand2Immediate &&
             !(LiMI2 && (LiMI2->getOpcode() == PPC::LI ||
                         LiMI2->getOpcode() == PPC::LI8)))
           break;
 
         auto ImmOperand0 = MI.getOperand(0).getImm();
         auto ImmOperand1 = LiMI1->getOperand(1).getImm();
         auto ImmOperand2 = IsOperand2Immediate ? MI.getOperand(2).getImm()
                                                : LiMI2->getOperand(1).getImm();
 
         // We will replace the MI with an unconditional trap if it will always
         // trap.
         if ((ImmOperand0 == 31) ||
             ((ImmOperand0 & 0x10) &&
              ((int64_t)ImmOperand1 < (int64_t)ImmOperand2)) ||
             ((ImmOperand0 & 0x8) &&
              ((int64_t)ImmOperand1 > (int64_t)ImmOperand2)) ||
             ((ImmOperand0 & 0x2) &&
              ((uint64_t)ImmOperand1 < (uint64_t)ImmOperand2)) ||
             ((ImmOperand0 & 0x1) &&
              ((uint64_t)ImmOperand1 > (uint64_t)ImmOperand2)) ||
             ((ImmOperand0 & 0x4) && (ImmOperand1 == ImmOperand2))) {
           BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP));
           TrapOpt = true;
         }
         // We will delete the MI if it will never trap.
         ToErase = &MI;
         Simplified = true;
         break;
       }
       }
     }
 
     // If the last instruction was marked for elimination,
     // remove it now.

llvm/test/CodeGen/PowerPC/fold-rot-and-peephole.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir \
+# RUN:     -verify-machineinstrs -run-pass ppc-mi-peepholes < %s | FileCheck %s
+
+---
+name: fold_RLDICL_ANDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICL_ANDI
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 1, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICL %1:g8rc, 0, 32
+    %3:g8rc = ANDI8_rec killed %2:g8rc, 1, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICL_ANDI2
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICL_ANDI2
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 0, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICL %1:g8rc, 10, 60
+    %3:g8rc = ANDI8_rec killed %2:g8rc, 32, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICR_ANDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICR_ANDI
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 16, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICR %1:g8rc, 0, 60
+    %3:g8rc = ANDI8_rec killed %2:g8rc, 16, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICR_ANDI2
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICR_ANDI2
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDI8_rec:%[0-9]+]]:g8rc = ANDI8_rec killed [[COPY]], 0, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDI8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICR %1:g8rc, 10, 60
+    %3:g8rc = ANDI8_rec killed %2:g8rc, 1, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICL_ANDIS
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICL_ANDIS
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 1, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICL %1:g8rc, 0, 32
+    %3:g8rc = ANDIS8_rec killed %2:g8rc, 1, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICL_ANDIS2
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICL_ANDIS2
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 0, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICL %1:g8rc, 10, 60
+    %3:g8rc = ANDIS8_rec killed %2:g8rc, 16, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICR_ANDIS
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICR_ANDIS
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 16, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICR %1:g8rc, 0, 60
+    %3:g8rc = ANDIS8_rec killed %2:g8rc, 16, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...
+---
+name: fold_RLDICR_ANDIS2
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3
+    ; CHECK-LABEL: name: fold_RLDICR_ANDIS2
+    ; CHECK: liveins: $x3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3
+    ; CHECK-NEXT: [[ANDIS8_rec:%[0-9]+]]:g8rc = ANDIS8_rec killed [[COPY]], 0, implicit-def dead $cr0
+    ; CHECK-NEXT: $x3 = COPY killed [[ANDIS8_rec]]
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $x3
+    %1:g8rc = COPY $x3
+    %2:g8rc = RLDICR %1:g8rc, 10, 32
+    %3:g8rc = ANDIS8_rec killed %2:g8rc, 1, implicit-def dead $cr0
+    $x3 = COPY %3:g8rc
+    BLR8 implicit $lr8, implicit $rm, implicit $x3
+...

llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

 
 
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
 ; CHECK-LABEL: getvelsl:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r3, r5, 32
-; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    andi. r3, r5, 1
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lvsl v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getvelsl:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrldi r3, r5, 32
 ; CHECK-LE-NEXT:    li r4, 1
 ; CHECK-LE-NEXT:    andc r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
 ; CHECK-LE-NEXT:    lvsl v3, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getvelsl:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    andi. 3, 3, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    lvsl 3, 0, 3
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vsl, i32 %i
   ret i64 %vecext
 ; FIXME: add check patterns when variable element extraction is implemented
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
 ; CHECK-LABEL: getvelul:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r3, r5, 32
-; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    andi. r3, r5, 1
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lvsl v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r3, v2
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getvelul:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrldi r3, r5, 32
 ; CHECK-LE-NEXT:    li r4, 1
 ; CHECK-LE-NEXT:    andc r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
 ; CHECK-LE-NEXT:    lvsl v3, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r3, v2
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getvelul:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    andi. 3, 3, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    lvsl 3, 0, 3
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 3, 34
 ; CHECK-AIX-NEXT:    blr
 entry:
   %vecext = extractelement <2 x i64> %vul, i32 %i
entry:
   %vecext = extractelement <2 x double> %vd, i32 1
   ret double %vecext
 }
 
 ; Function Attrs: norecurse nounwind readnone
 define double @getveld(<2 x double> %vd, i32 signext %i) {
 ; CHECK-LABEL: getveld:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r3, r5, 32
-; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    andi. r3, r5, 1
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lvsl v3, 0, r3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    xxlor vs1, v2, v2
 ; CHECK-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-LE-LABEL: getveld:
 ; CHECK-LE:       # %bb.0: # %entry
 ; CHECK-LE-NEXT:    clrldi r3, r5, 32
 ; CHECK-LE-NEXT:    li r4, 1
 ; CHECK-LE-NEXT:    andc r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
 ; CHECK-LE-NEXT:    lvsl v3, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    xxlor vs1, v2, v2
 ; CHECK-LE-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-LE-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: getveld:
 ; CHECK-AIX:       # %bb.0: # %entry
-; CHECK-AIX-NEXT:    clrldi 3, 3, 32
 ; CHECK-AIX-NEXT:    andi. 3, 3, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    lvsl 3, 0, 3
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    xxlor 1, 34, 34
 ; CHECK-AIX-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; CHECK-AIX-NEXT:    blr
 entry: