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Differential D129775

[x86] use zero-extending load of a byte outside of loops too
ClosedPublic

Authored by spatel on Jul 14 2022, 7:09 AM.

Details

Reviewers
craig.topper
pengfei
RKSimon
pcordes
Commits
rGf0dd12ec5c01: [x86] use zero-extending load of a byte outside of loops too (2nd try)
rG9d1ea1774c51: [x86] use zero-extending load of a byte outside of loops too
Summary

This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up.

As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte.

This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers.

There are 200+ test files changed, so the patch is too big to upload to Phab with full context, but all of the test diffs that I scanned are the expected "movb" -> "movzbl".

Diff Detail

Event Timeline

spatel created this revision.Jul 14 2022, 7:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2022, 7:09 AM
Herald added subscribers: jsji, StephenFan, mstorsjo and 3 others. · View Herald Transcript
spatel requested review of this revision.Jul 14 2022, 7:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 14 2022, 7:09 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
RKSimon added inline comments.Jul 14 2022, 8:28 AM
llvm/test/CodeGen/X86/ushl_sat_vec.ll
72

Why did only 1 of these movb get extended?

Harbormaster completed remote builds in B175398: Diff 444631.Jul 14 2022, 9:43 AM
craig.topper added inline comments.Jul 14 2022, 10:02 AM
llvm/test/CodeGen/X86/ushl_sat_vec.ll
72

%ch is live from line 69.

pcordes accepted this revision.Jul 16 2022, 10:02 AM
pcordes added inline comments.
llvm/test/CodeGen/X86/ushl_sat_vec.ll
72

It's possible to still avoid the false dependency by doing movzbl (mem), %ecx first, then movb (mem), %ch.

Reading the full CX/ECX/RCX will still need a merging uop on Intel SnB-family CPUs (which rename high-8 registers separately from the full reg), and unfortunately that merging uop has to issue in a cycle by itself. (So in terms of front-end cost, that extra cost is 4 or 5 uops, not just 1 more. Back-end contention for execution units is rarely a limiting factor for uops that can run on any port). But that merging cost is not paid until later, on the first read.

And on AMD CPUs (and Silvermont-family, like Alder Lake E-cores), there's no later merging cost, writing CH merges on the spot, so it's a nice win vs. movzbl into a temporary; shl $8,%tmp ; or %tmp,%ecx

This revision is now accepted and ready to land.Jul 16 2022, 10:02 AM
pcordes added a comment.Jul 16 2022, 10:06 AM

Oops, I think "accept revision" was stronger than I expected. I just meant "looks good to me" after reading the summary and comments, not that I'd gone through all the code to make sure it correctly did what it intends. Sorry about that.

spatel added a comment.Jul 19 2022, 10:20 AM

Ping - any remaining objections/concerns?
The patch still applies cleanly as of today, but I doubt that will last with so many test diffs. :)

RKSimon added a comment.Jul 19 2022, 10:29 AM

LGTM - although I can't see much Os and Oz test coverage?

spatel added a comment.Jul 19 2022, 10:44 AM
In D129775#3663121, @RKSimon wrote:

LGTM - although I can't see much Os and Oz test coverage?

Yes - I'll add minimal tests to check each of the attribute settings, so it's clear where we've drawn the line.

pcordes added a comment.EditedJul 19 2022, 11:01 AM
In D129775#3663121, @RKSimon wrote:

LGTM - although I can't see much Os and Oz test coverage?

Good point about -Oz / -Os. This would be a code-size regression for -Oz (for common cases that don't end up needing a later movzx if we start with movb).

And since this doesn't fix issue #56498 , it's *always* a code-size regression. We still redundantly do a movzbl %al, %eax after starting with a movzbl load and only doing byte operations on the bottom byte of a register, so it's still correctly zero-extended. e.g. the last test case (zext-logicop-shift-load.ll) shows that.

This is a good first step; fixing that issue to take advantage of cases where byte values are already zero extended can be done later.

If -Oz (and probably -Os) continue to use movb, then later code can't count on byte values being zero-extended to 64-bit. So the byte-load will need to tell the optimizer whether or not it's zero-extending, depending on options. (And ideally an optimization pass could still fold later zero-extension back into an earlier byte or word load, even with -Oz, because spending 1 extra byte in a load to save a multi-byte instruction is worth it for code-size.)

A temporary regression to code-size for -Oz and -Os is probably less important than a speedup for -O2 / -O3. (Assuming we actually do get any net speedup from this change alone!)

This revision was landed with ongoing or failed builds.Jul 19 2022, 1:45 PM
Closed by commit rG9d1ea1774c51: [x86] use zero-extending load of a byte outside of loops too (authored by spatel). · Explain Why
This revision was automatically updated to reflect the committed changes.
spatel added a commit: rG9d1ea1774c51: [x86] use zero-extending load of a byte outside of loops too.
spatel added a reverting change: rG95401b015393: Revert "[x86] use zero-extending load of a byte outside of loops too".Jul 19 2022, 2:37 PM
spatel added a commit: rGf0dd12ec5c01: [x86] use zero-extending load of a byte outside of loops too (2nd try).Jul 19 2022, 6:36 PM

Large Diff

This large diff affects 209 files. Files without inline comments have been collapsed. Expand All Files

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Diff 445934

llvm/lib/Target/X86/X86FixupBWInsts.cpp

llvm/test/CodeGen/X86/2006-01-19-ISelFoldingBug.ll

llvm/test/CodeGen/X86/2006-05-08-InstrSched.ll

llvm/test/CodeGen/X86/2006-11-17-IllegalMove.ll

llvm/test/CodeGen/X86/2007-08-09-IllegalX86-64Asm.ll

llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll

llvm/test/CodeGen/X86/2008-04-24-MemCpyBug.ll

llvm/test/CodeGen/X86/2008-09-11-CoalescerBug2.ll

llvm/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll

llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll

llvm/test/CodeGen/X86/GlobalISel/callingconv.ll

llvm/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll

llvm/test/CodeGen/X86/GlobalISel/memop-scalar.ll

llvm/test/CodeGen/X86/PR40322.ll

llvm/test/CodeGen/X86/abs.ll

llvm/test/CodeGen/X86/add-sub-bool.ll

llvm/test/CodeGen/X86/and-load-fold.ll

llvm/test/CodeGen/X86/and-sink.ll

llvm/test/CodeGen/X86/and-with-overflow.ll

llvm/test/CodeGen/X86/arg-copy-elide.ll

llvm/test/CodeGen/X86/atom-cmpb.ll

llvm/test/CodeGen/X86/atomic-idempotent.ll

llvm/test/CodeGen/X86/atomic-mi.ll

llvm/test/CodeGen/X86/atomic-monotonic.ll

llvm/test/CodeGen/X86/atomic-unordered.ll

llvm/test/CodeGen/X86/avoid-sfb-overlaps.ll

llvm/test/CodeGen/X86/avoid-sfb.ll

llvm/test/CodeGen/X86/avx512-calling-conv.ll

llvm/test/CodeGen/X86/avx512-ext.ll

llvm/test/CodeGen/X86/avx512-extract-subvector-load-store.ll

llvm/test/CodeGen/X86/avx512-insert-extract.ll

llvm/test/CodeGen/X86/avx512-intrinsics-canonical.ll

llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/avx512-intrinsics.ll

llvm/test/CodeGen/X86/avx512-load-store.ll

llvm/test/CodeGen/X86/avx512-load-trunc-store-i1.ll

llvm/test/CodeGen/X86/avx512-mask-op.ll

llvm/test/CodeGen/X86/avx512-select.ll

llvm/test/CodeGen/X86/avx512bf16-vl-intrinsics.ll

llvm/test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/avx512ifma-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512ifmavl-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512vbmi2-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512vbmi2vl-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

llvm/test/CodeGen/X86/bitcast-vector-bool.ll

llvm/test/CodeGen/X86/bitreverse.ll

llvm/test/CodeGen/X86/bmi.ll

llvm/test/CodeGen/X86/bool-math.ll

llvm/test/CodeGen/X86/bool-vector.ll

llvm/test/CodeGen/X86/brcond.ll

llvm/test/CodeGen/X86/bt.ll

llvm/test/CodeGen/X86/btc_bts_btr.ll

llvm/test/CodeGen/X86/byval5.ll

llvm/test/CodeGen/X86/callbr-asm-instr-scheduling.ll

llvm/test/CodeGen/X86/clear-highbits.ll

llvm/test/CodeGen/X86/clear-lowbits.ll

llvm/test/CodeGen/X86/clz.ll

llvm/test/CodeGen/X86/cmov.ll

llvm/test/CodeGen/X86/cmovcmov.ll

llvm/test/CodeGen/X86/combine-andintoload.ll

llvm/test/CodeGen/X86/combine-bswap.ll

llvm/test/CodeGen/X86/const-shift-of-constmasked.ll

llvm/test/CodeGen/X86/copy-eflags.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll

llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll

llvm/test/CodeGen/X86/divide-by-constant.ll

llvm/test/CodeGen/X86/divrem8_ext.ll

llvm/test/CodeGen/X86/emutls.ll

llvm/test/CodeGen/X86/extract-bits.ll

llvm/test/CodeGen/X86/extract-insert.ll

llvm/test/CodeGen/X86/extract-lowbits.ll

llvm/test/CodeGen/X86/extractelement-index.ll

llvm/test/CodeGen/X86/fast-isel-call-bool.ll

llvm/test/CodeGen/X86/fast-isel-i1.ll

llvm/test/CodeGen/X86/fast-isel-sext-zext.ll

llvm/test/CodeGen/X86/fixup-bw-copy.ll

llvm/test/CodeGen/X86/fixup-bw-inst.ll

llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll

llvm/test/CodeGen/X86/fold-and-shift.ll

llvm/test/CodeGen/X86/fp-intrinsics.ll

llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll

llvm/test/CodeGen/X86/fp-strict-scalar-inttofp-fp16.ll

llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

llvm/test/CodeGen/X86/fptosi-sat-scalar.ll

llvm/test/CodeGen/X86/fptoui-sat-scalar.ll

llvm/test/CodeGen/X86/fshl.ll

llvm/test/CodeGen/X86/fshr.ll

llvm/test/CodeGen/X86/funnel-shift-rot.ll

llvm/test/CodeGen/X86/funnel-shift.ll

llvm/test/CodeGen/X86/gpr-to-mask.ll

llvm/test/CodeGen/X86/h-register-addressing-32.ll

llvm/test/CodeGen/X86/h-register-addressing-64.ll

llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

llvm/test/CodeGen/X86/iabs.ll

llvm/test/CodeGen/X86/inc-of-add.ll

llvm/test/CodeGen/X86/insertelement-var-index.ll

llvm/test/CodeGen/X86/isel-sink2.ll

llvm/test/CodeGen/X86/legalize-shift-64.ll

llvm/test/CodeGen/X86/lifetime-alias.ll

llvm/test/CodeGen/X86/load-local-v3i1.ll

llvm/test/CodeGen/X86/load-local-v4i5.ll

llvm/test/CodeGen/X86/load-scalar-as-vector.ll

llvm/test/CodeGen/X86/masked_gather_scatter.ll

llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll

llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll

llvm/test/CodeGen/X86/memcmp-x32.ll

llvm/test/CodeGen/X86/memcmp.ll

llvm/test/CodeGen/X86/memcpy.ll

llvm/test/CodeGen/X86/merge-consecutive-loads-128.ll

llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll

llvm/test/CodeGen/X86/midpoint-int.ll

llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll

llvm/test/CodeGen/X86/movmsk-cmp.ll

llvm/test/CodeGen/X86/musttail-varargs.ll

llvm/test/CodeGen/X86/neg-abs.ll

llvm/test/CodeGen/X86/negate-i1.ll

llvm/test/CodeGen/X86/oddshuffles.ll

llvm/test/CodeGen/X86/or-with-overflow.ll

llvm/test/CodeGen/X86/packed_struct.ll

llvm/test/CodeGen/X86/peephole-na-phys-copy-folding.ll

llvm/test/CodeGen/X86/popcnt.ll

llvm/test/CodeGen/X86/pr12360.ll

llvm/test/CodeGen/X86/pr15267.ll

llvm/test/CodeGen/X86/pr20011.ll

llvm/test/CodeGen/X86/pr22473.ll

llvm/test/CodeGen/X86/pr28824.ll

llvm/test/CodeGen/X86/pr32345.ll

llvm/test/CodeGen/X86/pr34292.ll

llvm/test/CodeGen/X86/pr34381.ll

llvm/test/CodeGen/X86/pr35765.ll

llvm/test/CodeGen/X86/pr38539.ll

llvm/test/CodeGen/X86/pr38743.ll

llvm/test/CodeGen/X86/pr38795.ll

llvm/test/CodeGen/X86/pr39926.ll

llvm/test/CodeGen/X86/pr46527.ll

llvm/test/CodeGen/X86/pr5145.ll

llvm/test/CodeGen/X86/reduce-trunc-shl.ll

llvm/test/CodeGen/X86/rot16.ll

llvm/test/CodeGen/X86/rot32.ll

llvm/test/CodeGen/X86/rotate.ll

llvm/test/CodeGen/X86/rotate4.ll

llvm/test/CodeGen/X86/sadd_sat.ll

llvm/test/CodeGen/X86/sadd_sat_plus.ll

llvm/test/CodeGen/X86/sadd_sat_vec.ll

llvm/test/CodeGen/X86/sdiv_fix.ll

llvm/test/CodeGen/X86/sdiv_fix_sat.ll

llvm/test/CodeGen/X86/select.ll

llvm/test/CodeGen/X86/setcc-combine.ll

llvm/test/CodeGen/X86/setcc.ll

llvm/test/CodeGen/X86/sext-trunc.ll

llvm/test/CodeGen/X86/shift-amount-mod.ll

llvm/test/CodeGen/X86/shift-and.ll

llvm/test/CodeGen/X86/shift-bmi2.ll

llvm/test/CodeGen/X86/shift-by-signext.ll

llvm/test/CodeGen/X86/shift-coalesce.ll

llvm/test/CodeGen/X86/shift-combine.ll

llvm/test/CodeGen/X86/shift-double.ll

llvm/test/CodeGen/X86/shift-i128.ll

llvm/test/CodeGen/X86/shift-mask.ll

llvm/test/CodeGen/X86/smul_fix.ll

llvm/test/CodeGen/X86/smul_fix_sat.ll

llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll

llvm/test/CodeGen/X86/sse-scalar-fp-arith.ll

llvm/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll

llvm/test/CodeGen/X86/sshl_sat.ll

llvm/test/CodeGen/X86/sshl_sat_vec.ll

llvm/test/CodeGen/X86/ssub_sat.ll

llvm/test/CodeGen/X86/ssub_sat_plus.ll

llvm/test/CodeGen/X86/ssub_sat_vec.ll

llvm/test/CodeGen/X86/store-narrow.ll

llvm/test/CodeGen/X86/sttni.ll

llvm/test/CodeGen/X86/sub-of-not.ll

llvm/test/CodeGen/X86/swifterror.ll

llvm/test/CodeGen/X86/tail-opts.ll

llvm/test/CodeGen/X86/tls.ll

llvm/test/CodeGen/X86/trunc-to-bool.ll

llvm/test/CodeGen/X86/uadd_sat.ll

llvm/test/CodeGen/X86/uadd_sat_plus.ll

llvm/test/CodeGen/X86/uadd_sat_vec.ll

llvm/test/CodeGen/X86/udiv_fix.ll

llvm/test/CodeGen/X86/udiv_fix_sat.ll

llvm/test/CodeGen/X86/umul_fix.ll

llvm/test/CodeGen/X86/umul_fix_sat.ll

llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll

llvm/test/CodeGen/X86/unfold-masked-merge-vector-variablemask.ll

llvm/test/CodeGen/X86/urem-power-of-two.ll

llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll

llvm/test/CodeGen/X86/ushl_sat.ll

llvm/test/CodeGen/X86/ushl_sat_vec.ll

Show First 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; ;
; X86-LABEL: vec: ; X86-LABEL: vec:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %ebx
; X86-NEXT: pushl %edi ; X86-NEXT: pushl %edi
; X86-NEXT: pushl %esi ; X86-NEXT: pushl %esi
; X86-NEXT: movb {{[0-9]+}}(%esp), %ch ; X86-NEXT: movb {{[0-9]+}}(%esp), %ch
; X86-NEXT: movb {{[0-9]+}}(%esp), %dl ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
RKSimonUnsubmitted
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ReplyInline Actions

Why did only 1 of these movb get extended?

RKSimon: Why did only 1 of these movb get extended?
craig.topperUnsubmitted
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%ch is live from line 69.

craig.topper: %ch is live from line 69.
pcordesUnsubmitted
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ReplyInline Actions

It's possible to still avoid the false dependency by doing movzbl (mem), %ecx first, then movb (mem), %ch.

Reading the full CX/ECX/RCX will still need a merging uop on Intel SnB-family CPUs (which rename high-8 registers separately from the full reg), and unfortunately that merging uop has to issue in a cycle by itself. (So in terms of front-end cost, that extra cost is 4 or 5 uops, not just 1 more. Back-end contention for execution units is rarely a limiting factor for uops that can run on any port). But that merging cost is not paid until later, on the first read.

And on AMD CPUs (and Silvermont-family, like Alder Lake E-cores), there's no later merging cost, writing CH merges on the spot, so it's a nice win vs. movzbl into a temporary; shl $8,%tmp ; or %tmp,%ecx

pcordes: It's possible to still avoid the false dependency by doing `movzbl (mem), %ecx` first, then…
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-NEXT: movl %ebx, %esi ; X86-NEXT: movl %ebx, %esi
; X86-NEXT: shll %cl, %esi ; X86-NEXT: shll %cl, %esi
; X86-NEXT: movl %esi, %ebp ; X86-NEXT: movl %esi, %ebp
; X86-NEXT: shrl %cl, %ebp ; X86-NEXT: shrl %cl, %ebp
; X86-NEXT: cmpl %ebp, %ebx ; X86-NEXT: cmpl %ebp, %ebx
; X86-NEXT: movl $-1, %ebx ; X86-NEXT: movl $-1, %ebx
; X86-NEXT: cmovnel %ebx, %esi ; X86-NEXT: cmovnel %ebx, %esi
; X86-NEXT: movl %edi, %eax ; X86-NEXT: movl %edi, %eax
; X86-NEXT: movb %dl, %cl ; X86-NEXT: movb %dl, %cl
; X86-NEXT: shll %cl, %eax ; X86-NEXT: shll %cl, %eax
; X86-NEXT: movl %eax, %ebp ; X86-NEXT: movl %eax, %ebp
; X86-NEXT: shrl %cl, %ebp ; X86-NEXT: shrl %cl, %ebp
; X86-NEXT: cmpl %ebp, %edi ; X86-NEXT: cmpl %ebp, %edi
; X86-NEXT: cmovnel %ebx, %eax ; X86-NEXT: cmovnel %ebx, %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: movl %ebp, %edx ; X86-NEXT: movl %ebp, %edx
; X86-NEXT: movb %ch, %cl ; X86-NEXT: movb %ch, %cl
; X86-NEXT: shll %cl, %edx ; X86-NEXT: shll %cl, %edx
; X86-NEXT: movl %edx, %edi ; X86-NEXT: movl %edx, %edi
; X86-NEXT: shrl %cl, %edi ; X86-NEXT: shrl %cl, %edi
; X86-NEXT: cmpl %edi, %ebp ; X86-NEXT: cmpl %edi, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-NEXT: cmovnel %ebx, %edx ; X86-NEXT: cmovnel %ebx, %edx
; X86-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: shll %cl, %ebp ; X86-NEXT: shll %cl, %ebp
; X86-NEXT: movl %ebp, %edi ; X86-NEXT: movl %ebp, %edi
; X86-NEXT: shrl %cl, %edi ; X86-NEXT: shrl %cl, %edi
; X86-NEXT: cmpl %edi, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl %edi, {{[0-9]+}}(%esp)
; X86-NEXT: cmovnel %ebx, %ebp ; X86-NEXT: cmovnel %ebx, %ebp
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl %ebp, 12(%ecx) ; X86-NEXT: movl %ebp, 12(%ecx)
; X86-NEXT: movl %edx, 8(%ecx) ; X86-NEXT: movl %edx, 8(%ecx)
Show All 11 Lines

llvm/test/CodeGen/X86/usub_sat.ll

llvm/test/CodeGen/X86/usub_sat_plus.ll

llvm/test/CodeGen/X86/usub_sat_vec.ll

llvm/test/CodeGen/X86/vec_setcc.ll

llvm/test/CodeGen/X86/vector-sext.ll

llvm/test/CodeGen/X86/volatile-memstores-nooverlapping-load-stores.ll

llvm/test/CodeGen/X86/xchg-nofold.ll

llvm/test/CodeGen/X86/xmulo.ll

llvm/test/CodeGen/X86/xor-icmp.ll

llvm/test/CodeGen/X86/xor-lea.ll

llvm/test/CodeGen/X86/xor-with-overflow.ll

llvm/test/CodeGen/X86/xor.ll

llvm/test/CodeGen/X86/zext-logicop-shift-load.ll