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Differential D127475

[RISCV][NFC] precommit tests for D127474
ClosedPublic

Authored by Pretty-box on Jun 9 2022, 11:18 PM.

Details

Reviewers
benshi001
craig.topper
Commits
rGa0af0496147d: [RISCV][NFC] Add more tests for instruction selection of 'mul'

Diff Detail

Event Timeline

Pretty-box created this revision.Jun 9 2022, 11:18 PM
Herald added subscribers: StephenFan, frasercrmck, luismarques and 19 others. · View Herald TranscriptJun 9 2022, 11:18 PM
Pretty-box requested review of this revision.Jun 9 2022, 11:18 PM
Herald added subscribers: llvm-commits, • pcwang-thead, MaskRay. · View Herald TranscriptJun 9 2022, 11:18 PM
Harbormaster completed remote builds in B169010: Diff 435808.Jun 9 2022, 11:56 PM
craig.topper added a comment.Jun 10 2022, 12:52 PM

Please include [RISCV] in the title. I'd drop the [tests] and include NFC instead.

craig.topper added a child revision: D127474: [SelectionDAG] fold Op0 - (X * MulC) --> Op0 + (X << log2(-MulC)).Jun 10 2022, 12:53 PM
craig.topper mentioned this in D127474: [SelectionDAG] fold Op0 - (X * MulC) --> Op0 + (X << log2(-MulC)).
Pretty-box retitled this revision from [tests] precommit tests for D127474 to [RISCV][NFC] precommit tests for D127474.Jun 12 2022, 6:40 PM
Herald added subscribers: sunshaoce, eopXD, VincentWu and 8 others. · View Herald TranscriptJun 12 2022, 6:40 PM
Pretty-box added a comment.Jun 12 2022, 8:37 PM
In D127475#3574453, @craig.topper wrote:

Please include [RISCV] in the title. I'd drop the [tests] and include NFC instead.

Done.

craig.topper added inline comments.Jun 14 2022, 10:06 AM
llvm/test/CodeGen/RISCV/mul.ll
1584

Should this be mulsub_demand to match muladd_demand above?

Pretty-box updated this revision to Diff 437000.Jun 14 2022, 7:15 PM
craig.topper accepted this revision.Jun 14 2022, 7:16 PM

LGTM

This revision is now accepted and ready to land.Jun 14 2022, 7:16 PM
Harbormaster completed remote builds in B169889: Diff 437000.Jun 14 2022, 8:07 PM
This revision was landed with ongoing or failed builds.Jun 14 2022, 8:48 PM
Closed by commit rGa0af0496147d: [RISCV][NFC] Add more tests for instruction selection of 'mul' (authored by Pretty-box, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGa0af0496147d: [RISCV][NFC] Add more tests for instruction selection of 'mul'.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
52 lines

Diff 437020

llvm/test/CodeGen/RISCV/mul.ll

Show First 20 Lines • Show All 1,574 Lines • ▼ Show 20 Lines
; RV64IM-NEXT: subw a0, a1, a0 ; RV64IM-NEXT: subw a0, a1, a0
; RV64IM-NEXT: andi a0, a0, 15 ; RV64IM-NEXT: andi a0, a0, 15
; RV64IM-NEXT: ret ; RV64IM-NEXT: ret
%m = mul i8 %x, 14 %m = mul i8 %x, 14
%a = add i8 %y, %m %a = add i8 %y, %m
%r = and i8 %a, 15 %r = and i8 %a, 15
ret i8 %r ret i8 %r
} }
define i8 @mulsub_demand(i8 %x, i8 %y) nounwind {
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Should this be mulsub_demand to match muladd_demand above?

craig.topper: Should this be mulsub_demand to match muladd_demand above?
; RV32I-LABEL: mulsub_demand:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: li a1, 14
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: sub a0, s0, a0
; RV32I-NEXT: andi a0, a0, 15
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IM-LABEL: mulsub_demand:
; RV32IM: # %bb.0:
; RV32IM-NEXT: li a2, 14
; RV32IM-NEXT: mul a0, a0, a2
; RV32IM-NEXT: sub a0, a1, a0
; RV32IM-NEXT: andi a0, a0, 15
; RV32IM-NEXT: ret
;
; RV64I-LABEL: mulsub_demand:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: li a1, 14
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: subw a0, s0, a0
; RV64I-NEXT: andi a0, a0, 15
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: mulsub_demand:
; RV64IM: # %bb.0:
; RV64IM-NEXT: li a2, 14
; RV64IM-NEXT: mulw a0, a0, a2
; RV64IM-NEXT: subw a0, a1, a0
; RV64IM-NEXT: andi a0, a0, 15
; RV64IM-NEXT: ret
%m = mul i8 %x, 14
%a = sub i8 %y, %m
%r = and i8 %a, 15
ret i8 %r
}