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[SelectionDAG] fold Op0 - (X * MulC) --> Op0 + (X << log2(-MulC))
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Authored by Pretty-box on Jun 9 2022, 11:11 PM.

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Pretty-box created this revision.Jun 9 2022, 11:11 PM
Pretty-box requested review of this revision.Jun 9 2022, 11:11 PM
craig.topper added inline comments.
llvm/test/CodeGen/RISCV/mul.ll
1584

Please rebase this on top of D127475

craig.topper added inline comments.Jun 10 2022, 12:56 PM
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
2541

Might be better to pass ISD::SUB or ISD::ADD from the caller instead of re-inspecting the opcode.

Pretty-box marked 2 inline comments as done.
spatel accepted this revision.Jun 13 2022, 8:55 AM

LGTM - as noted in 21d7c3bcc646f5db73b, this pattern is probably not common because it's not the canonical IR.

A more interesting case is where the mul is operand 0 of the sub. We would not transform that in IR because it needs a negation, but removing the multiply looks better on several targets (RISCV, AArch64, x86). It's probably a win for any target where multiply is slower than the fastest ALU op, and we're not optimizing strictly for size.

This revision is now accepted and ready to land.Jun 13 2022, 8:55 AM
spatel added inline comments.Jun 13 2022, 8:58 AM
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
2557

Leave off the inner-most braces to be consistent with the existing code.

Pretty-box marked an inline comment as done.
This revision was landed with ongoing or failed builds.Jun 14 2022, 10:50 PM
This revision was automatically updated to reflect the committed changes.