[RISCV] Support (addi (addi globaladdr, C1), C2) in RISCVMergeBaseOffset.

[craig.topper]

Summary

Add with immediates in the range [-4096, -2049] or [2048, 4095] get
convert to two ADDIs. Teach RISCVMergeBaseOffset to recognize this
pattern as well.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

209–223

BTW, shouldn't the preexisting code check the type of the tail ADDI immediate machine operand (that it is MO_Immediate or something like that)? If so, then the same applies to this second ADDI.

[craig.topper]

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

209–223

I think it has to be an immediate because we started from a global address LUI+ADDI pair. Any user of that could only be an ADDI with a real immediate. It couldn't be part of another global address and it couldn't be a frame index.

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

bool RISCVMergeBaseOffsetOpt::detectAndFoldOffset(MachineInstr &HiLUI,
   MachineInstr &Tail = *MRI->use_instr_begin(DestReg);
   switch (Tail.getOpcode()) {
   default:
     LLVM_DEBUG(dbgs() << "Don't know how to get offset from this instr:"
                       << Tail);
     return false;
   case RISCV::ADDI: {
     // Offset is simply an immediate operand.
     int64_t Offset = Tail.getOperand(2).getImm();
+
+    // We might have two ADDIs in a row.
+    Register TailDestReg = Tail.getOperand(0).getReg();
+    if (MRI->hasOneUse(TailDestReg)) {
+      MachineInstr &TailTail = *MRI->use_instr_begin(TailDestReg);
+      if (TailTail.getOpcode() == RISCV::ADDI) {
+        Offset += TailTail.getOperand(2).getImm();
+        DeadInstrs.insert(&Tail);
+        foldOffset(HiLUI, LoADDI, TailTail, Offset);
+        return true;
+      }
+    }
+
     LLVM_DEBUG(dbgs() << "  Offset Instr: " << Tail);
     foldOffset(HiLUI, LoADDI, Tail, Offset);
     return true;
   }
   case RISCV::ADD: {
     // The offset is too large to fit in the immediate field of ADDI.
     // This can be in two forms:
     // 1) LUI hi_Offset followed by:
     //    ADDI lo_offset

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

 ; RV64-NEXT:    lui a0, %hi(bar)
 ; RV64-NEXT:    addi a0, a0, %lo(bar)
 ; RV64-NEXT:    lui a1, 524288
 ; RV64-NEXT:    addi a1, a1, -1365
 ; RV64-NEXT:    add a0, a0, a1
 ; RV64-NEXT:    ret
     ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i64 -2147485013)
 }
+
+define i8* @offset_addi_addi() {
+; CHECK-LABEL: offset_addi_addi:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(bar+3211)
+; CHECK-NEXT:    addi a0, a0, %lo(bar+3211)
+; CHECK-NEXT:    ret
+    ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i64 3211)
+}
+
+define i8* @offset_addi_addi_neg() {
+; CHECK-LABEL: offset_addi_addi_neg:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(bar-4000)
+; CHECK-NEXT:    addi a0, a0, %lo(bar-4000)
+; CHECK-NEXT:    ret
+    ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i64 -4000)
+}