This is an archive of the discontinued LLVM Phabricator instance.

Show First 20 Lines • Show All 2,021 Lines • ▼ Show 20 Lines	let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;		def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;		def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;		def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}		}
}		}

// 15. Vector Reduction Operations		// 15. Vector Reduction Operations
// 15.1. Vector Single-Width Integer Reduction Instructions		// 15.1. Vector Single-Width Integer Reduction Instructions
let MaskedPolicyScheme = NonePolicy,		let UnMaskedPolicyScheme = HasPassthruOperand,
		MaskedPolicyScheme = HasPassthruOperand,
IsPrototypeDefaultTU = true,		IsPrototypeDefaultTU = true,
HasMaskPolicy = false in {		HasMaskPolicy = false in {
defm vredsum : RVVIntReductionBuiltinSet;		defm vredsum : RVVIntReductionBuiltinSet;
defm vredmaxu : RVVUnsignedReductionBuiltin;		defm vredmaxu : RVVUnsignedReductionBuiltin;
defm vredmax : RVVSignedReductionBuiltin;		defm vredmax : RVVSignedReductionBuiltin;
defm vredminu : RVVUnsignedReductionBuiltin;		defm vredminu : RVVUnsignedReductionBuiltin;
defm vredmin : RVVSignedReductionBuiltin;		defm vredmin : RVVSignedReductionBuiltin;
defm vredand : RVVIntReductionBuiltinSet;		defm vredand : RVVIntReductionBuiltinSet;
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clang/lib/Support/RISCVVIntrinsicUtils.cpp

Show First 20 Lines • Show All 931 Lines • ▼ Show 20 Lines	if (!IsMasked) {
DefaultPolicy = Policy::TU;		DefaultPolicy = Policy::TU;
else		else
DefaultPolicy = Policy::TA;		DefaultPolicy = Policy::TA;
}		}
break;		break;
default:		default:
break;		break;
}		}
		bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
if (IsMasked) {		if (IsMasked) {
// If HasMaskedOffOperand, insert result type as first input operand if		// If HasMaskedOffOperand, insert result type as first input operand if
// need.		// need.
if (HasMaskedOffOperand) {		if (HasMaskedOffOperand) {
if (NF == 1 && DefaultPolicy != Policy::TAMA) {		if (NF == 1 && DefaultPolicy != Policy::TAMA) {
NewPrototype.insert(NewPrototype.begin() + 1, NewPrototype[0]);		NewPrototype.insert(NewPrototype.begin() + 1, NewPrototype[0]);
} else if (NF > 1) {		} else if (NF > 1) {
// Convert		// Convert
// (void, op0 address, op1 address, ...)		// (void, op0 address, op1 address, ...)
// to		// to
// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)		// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
PrototypeDescriptor MaskoffType = NewPrototype[1];		PrototypeDescriptor MaskoffType = NewPrototype[1];
MaskoffType.TM &= ~static_cast<uint8_t>(TypeModifier::Pointer);		MaskoffType.TM &= ~static_cast<uint8_t>(TypeModifier::Pointer);
for (unsigned I = 0; I < NF; ++I)		for (unsigned I = 0; I < NF; ++I)
NewPrototype.insert(NewPrototype.begin() + NF + 1, MaskoffType);		NewPrototype.insert(NewPrototype.begin() + NF + 1, MaskoffType);
}		}
}		}
		// Erase passthru operand for TAM
		if (NF == 1 && IsPrototypeDefaultTU && DefaultPolicy == Policy::TAMA &&
		HasPassthruOp && !HasMaskedOffOperand)
		NewPrototype.erase(NewPrototype.begin() + 1);
if (HasMaskedOffOperand && NF > 1) {		if (HasMaskedOffOperand && NF > 1) {
// Convert		// Convert
// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)		// (void, op0 address, op1 address, ..., maskedoff0, maskedoff1, ...)
// to		// to
// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,		// (void, op0 address, op1 address, ..., mask, maskedoff0, maskedoff1,
// ...)		// ...)
NewPrototype.insert(NewPrototype.begin() + NF + 1,		NewPrototype.insert(NewPrototype.begin() + NF + 1,
PrototypeDescriptor::Mask);		PrototypeDescriptor::Mask);
} else {		} else {
// If IsMasked, insert PrototypeDescriptor:Mask as first input operand.		// If IsMasked, insert PrototypeDescriptor:Mask as first input operand.
NewPrototype.insert(NewPrototype.begin() + 1, PrototypeDescriptor::Mask);		NewPrototype.insert(NewPrototype.begin() + 1, PrototypeDescriptor::Mask);
}		}
} else if (NF == 1) {		} else if (NF == 1) {
bool HasPassthruOp = DefaultScheme == PolicyScheme::HasPassthruOperand;
if (DefaultPolicy == Policy::TU && HasPassthruOp && !IsPrototypeDefaultTU)		if (DefaultPolicy == Policy::TU && HasPassthruOp && !IsPrototypeDefaultTU)
NewPrototype.insert(NewPrototype.begin(), NewPrototype[0]);		NewPrototype.insert(NewPrototype.begin(), NewPrototype[0]);
else if (DefaultPolicy == Policy::TA && HasPassthruOp &&		else if (DefaultPolicy == Policy::TA && HasPassthruOp &&
IsPrototypeDefaultTU)		IsPrototypeDefaultTU)
NewPrototype.erase(NewPrototype.begin() + 1);		NewPrototype.erase(NewPrototype.begin() + 1);
if (DefaultScheme == PolicyScheme::HasPassthruOperandAtIdx1) {		if (DefaultScheme == PolicyScheme::HasPassthruOperandAtIdx1) {
if (DefaultPolicy == Policy::TU && !IsPrototypeDefaultTU) {		if (DefaultPolicy == Policy::TU && !IsPrototypeDefaultTU) {
// Insert undisturbed output to index 1		// Insert undisturbed output to index 1
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c

	Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 8 x double> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 8 x double> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	//			//
	vfloat64m1_t test_vfredmax_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,			vfloat64m1_t test_vfredmax_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
	vfloat64m8_t vector,			vfloat64m8_t vector,
	vfloat64m1_t scalar, size_t vl) {			vfloat64m1_t scalar, size_t vl) {
	return vfredmax(mask, dst, vector, scalar, vl);			return vfredmax(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c

	Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 8 x double> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 8 x double> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	//			//
	vfloat64m1_t test_vfredmin_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,			vfloat64m1_t test_vfredmin_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
	vfloat64m8_t vector,			vfloat64m8_t vector,
	vfloat64m1_t scalar, size_t vl) {			vfloat64m1_t scalar, size_t vl) {
	return vfredmin(mask, dst, vector, scalar, vl);			return vfredmin(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c

	Show First 20 Lines • Show All 386 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 8 x double> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 8 x double> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	//			//
	vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,			vfloat64m1_t test_vfredosum_vs_f64m8_f64m1_m(vbool8_t mask, vfloat64m1_t dst,
	vfloat64m8_t vector,			vfloat64m8_t vector,
	vfloat64m1_t scalar, size_t vl) {			vfloat64m1_t scalar, size_t vl) {
	return vfredosum(mask, dst, vector, scalar, vl);			return vfredosum(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c

	Show First 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 16 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.]], <vscale x 16 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
	//			//
	vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst,			vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst,
	vfloat32m8_t vector,			vfloat32m8_t vector,
	vfloat64m1_t scalar, size_t vl) {			vfloat64m1_t scalar, size_t vl) {
	return vfwredosum(mask, dst, vector, scalar, vl);			return vfwredosum(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tu (vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_ta (vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tum (vbool64_t mask, vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tam (vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tu(vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_ta(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredand_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredand_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredand(mask, dst, vector, scalar, vl);			return vredand(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredmaxu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredmaxu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredmaxu(mask, dst, vector, scalar, vl);			return vredmaxu(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredminu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredminu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredminu(mask, dst, vector, scalar, vl);			return vredminu(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector, vuint64m1_t scalar,			vuint64m8_t vector, vuint64m1_t scalar,
	size_t vl) {			size_t vl) {
	return vredor(mask, dst, vector, scalar, vl);			return vredor(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredsum_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredsum_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredsum(mask, dst, vector, scalar, vl);			return vredsum(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredxor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredxor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredxor(mask, dst, vector, scalar, vl);			return vredxor(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c

	Show First 20 Lines • Show All 753 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 16 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 16 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vwredsumu_vs_u32m8_u64m1_m(vbool4_t mask, vuint64m1_t dst,			vuint64m1_t test_vwredsumu_vs_u32m8_u64m1_m(vbool4_t mask, vuint64m1_t dst,
	vuint32m8_t vector,			vuint32m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vwredsumu(mask, dst, vector, scalar, vl);			return vwredsumu(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tu(vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tu(vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_ta(vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_ta(vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tum(vbool64_t mask, vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tum(vbool64_t mask, vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tam(vbool64_t mask, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c

	Show First 20 Lines • Show All 297 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vfredmax_vs_f16m8_f16m1_m(			// CHECK-RV64-LABEL: @test_vfredmax_vs_f16m8_f16m1_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 4 x half> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 4 x half> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
	//			//
	vfloat16m1_t test_vfredmax_vs_f16m8_f16m1_m (vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {			vfloat16m1_t test_vfredmax_vs_f16m8_f16m1_m (vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
	return vfredmax_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl);			return vfredmax_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_vs_f32mf2_f32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_vs_f32mf2_f32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_vs_f32mf2_f32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmax_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmax_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmax_vs_f32mf2_f32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c

	Show First 20 Lines • Show All 297 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vfredmin_vs_f16m8_f16m1_m(			// CHECK-RV64-LABEL: @test_vfredmin_vs_f16m8_f16m1_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 4 x half> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 4 x half> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
	//			//
	vfloat16m1_t test_vfredmin_vs_f16m8_f16m1_m (vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {			vfloat16m1_t test_vfredmin_vs_f16m8_f16m1_m (vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
	return vfredmin_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl);			return vfredmin_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_vs_f32mf2_f32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_vs_f32mf2_f32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_vs_f32mf2_f32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredmin_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredmin_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredmin_vs_f32mf2_f32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c

	Show First 20 Lines • Show All 603 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vfredosum_vs_f16m8_f16m1_m(			// CHECK-RV64-LABEL: @test_vfredosum_vs_f16m8_f16m1_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 4 x half> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.i64(<vscale x 4 x half> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 4 x half> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
	//			//
	vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {			vfloat16m1_t test_vfredosum_vs_f16m8_f16m1_m(vbool2_t mask, vfloat16m1_t dest, vfloat16m8_t vector, vfloat16m1_t scalar, size_t vl) {
	return vfredosum_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl);			return vfredosum_vs_f16m8_f16m1_m(mask, dest, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_vs_f32mf2_f32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_vs_f32mf2_f32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_vs_f32mf2_f32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredusum_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredusum_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredusum_vs_f32mf2_f32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tu(vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_vs_f32mf2_f32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_ta(vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_vs_f32mf2_f32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tum(vbool64_t mask, vfloat32m1_t merge, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_vs_f32mf2_f32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfredosum_vs_f32mf2_f32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.i64(<vscale x 2 x float> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
				//
				vfloat32m1_t test_vfredosum_vs_f32mf2_f32m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat32m1_t scalar, size_t vl) {
				return vfredosum_vs_f32mf2_f32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c

	Show First 20 Lines • Show All 435 Lines • ▼ Show 20 Lines
	// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1_m(			// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1_m(
	// CHECK-RV64-NEXT: entry:			// CHECK-RV64-NEXT: entry:
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.]], <vscale x 32 x half> [[VECTOR:%.]], <vscale x 2 x float> [[SCALAR:%.]], <vscale x 32 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
	//			//
	vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {			vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {
	return vfwredusum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl);			return vfwredusum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tu(vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_vs_f32mf2_f64m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_ta(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_vs_f32mf2_f64m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_vs_f32mf2_f64m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredusum_vs_f32mf2_f64m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tu(vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_vs_f32mf2_f64m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_ta(vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_vs_f32mf2_f64m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[MERGE:%.]], <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tum(vbool64_t mask, vfloat64m1_t merge, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_vs_f32mf2_f64m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vfwredosum_vs_f32mf2_f64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> undef, <vscale x 1 x float> [[VECTOR:%.]], <vscale x 1 x double> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
				//
				vfloat64m1_t test_vfwredosum_vs_f32mf2_f64m1_tam(vbool64_t mask, vfloat32mf2_t vector, vfloat64m1_t scalar, size_t vl) {
				return vfwredosum_vs_f32mf2_f64m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredand_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredand_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredand_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);			return vredand_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_vs_i32mf2_i32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_vs_u32mf2_u32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_vs_i32mf2_i32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_vs_u32mf2_u32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_vs_i32mf2_i32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_vs_u32mf2_u32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredand_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredand_vs_i32mf2_i32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredand_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredand_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredand_vs_u32mf2_u32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredmaxu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredmaxu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredmaxu_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);			return vredmaxu_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_vs_i32mf2_i32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_vs_u32mf2_u32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_vs_i32mf2_i32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_vs_u32mf2_u32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_vs_i32mf2_i32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_vs_u32mf2_u32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmax_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmax_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmax_vs_i32mf2_i32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmaxu_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredmaxu_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredmaxu_vs_u32mf2_u32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredminu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredminu_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredminu_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);			return vredminu_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_vs_i32mf2_i32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_vs_u32mf2_u32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_vs_i32mf2_i32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_vs_u32mf2_u32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_vs_i32mf2_i32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_vs_u32mf2_u32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredmin_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredmin_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredmin_vs_i32mf2_i32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredminu_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredminu_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredminu_vs_u32mf2_u32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector, vuint64m1_t scalar,			vuint64m8_t vector, vuint64m1_t scalar,
	size_t vl) {			size_t vl) {
	return vredor_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);			return vredor_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_vs_i32mf2_i32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_vs_u32mf2_u32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_vs_i32mf2_i32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_vs_u32mf2_u32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_vs_i32mf2_i32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_vs_u32mf2_u32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredor_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredor_vs_i32mf2_i32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredor_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredor_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredor_vs_u32mf2_u32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredsum_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredsum_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredsum_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);			return vredsum_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_vs_i32mf2_i32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_vs_u32mf2_u32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_vs_i32mf2_i32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_vs_u32mf2_u32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_vs_i32mf2_i32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_vs_u32mf2_u32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredsum_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredsum_vs_i32mf2_i32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredsum_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredsum_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredsum_vs_u32mf2_u32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c

	Show First 20 Lines • Show All 921 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 8 x i64> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 8 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vredxor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,			vuint64m1_t test_vredxor_vs_u64m8_u64m1_m(vbool8_t mask, vuint64m1_t dst,
	vuint64m8_t vector,			vuint64m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vredxor_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);			return vredxor_vs_u64m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_tu(vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_vs_i32mf2_i32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_tu(vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_vs_u32mf2_u32m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_ta(vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_vs_i32mf2_i32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_ta(vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_vs_u32mf2_u32m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_tum(vbool64_t mask, vint32m1_t merge, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_vs_i32mf2_i32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_tum(vbool64_t mask, vuint32m1_t merge, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_vs_u32mf2_u32m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_i32mf2_i32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vint32m1_t test_vredxor_vs_i32mf2_i32m1_tam(vbool64_t mask, vint32mf2_t vector, vint32m1_t scalar, size_t vl) {
				return vredxor_vs_i32mf2_i32m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vredxor_vs_u32mf2_u32m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.i64(<vscale x 2 x i32> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 2 x i32> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]]
				//
				vuint32m1_t test_vredxor_vs_u32mf2_u32m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint32m1_t scalar, size_t vl) {
				return vredxor_vs_u32mf2_u32m1_tam(mask, vector, scalar, vl);
				}

clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c

	Show First 20 Lines • Show All 753 Lines • ▼ Show 20 Lines
	// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 16 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])			// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.i64(<vscale x 1 x i64> [[DST:%.]], <vscale x 16 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 16 x i1> [[MASK:%.]], i64 [[VL:%.]])
	// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]			// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
	//			//
	vuint64m1_t test_vwredsumu_vs_u32m8_u64m1_m(vbool4_t mask, vuint64m1_t dst,			vuint64m1_t test_vwredsumu_vs_u32m8_u64m1_m(vbool4_t mask, vuint64m1_t dst,
	vuint32m8_t vector,			vuint32m8_t vector,
	vuint64m1_t scalar, size_t vl) {			vuint64m1_t scalar, size_t vl) {
	return vwredsumu_vs_u32m8_u64m1_m(mask, dst, vector, scalar, vl);			return vwredsumu_vs_u32m8_u64m1_m(mask, dst, vector, scalar, vl);
	}			}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tu(vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_vs_i32mf2_i64m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tu(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tu(vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_vs_u32mf2_u64m1_tu(merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_ta(vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_vs_i32mf2_i64m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_ta(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_ta(vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_vs_u32mf2_u64m1_ta(vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tum(vbool64_t mask, vint64m1_t merge, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_vs_i32mf2_i64m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tum(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> [[MERGE:%.]], <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tum(vbool64_t mask, vuint64m1_t merge, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_vs_u32mf2_u64m1_tum(mask, merge, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsum_vs_i32mf2_i64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vint64m1_t test_vwredsum_vs_i32mf2_i64m1_tam(vbool64_t mask, vint32mf2_t vector, vint64m1_t scalar, size_t vl) {
				return vwredsum_vs_i32mf2_i64m1_tam(mask, vector, scalar, vl);
				}

				// CHECK-RV64-LABEL: @test_vwredsumu_vs_u32mf2_u64m1_tam(
				// CHECK-RV64-NEXT: entry:
				// CHECK-RV64-NEXT: [[TMP0:%.]] = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> [[VECTOR:%.]], <vscale x 1 x i64> [[SCALAR:%.]], <vscale x 1 x i1> [[MASK:%.]], i64 [[VL:%.*]])
				// CHECK-RV64-NEXT: ret <vscale x 1 x i64> [[TMP0]]
				//
				vuint64m1_t test_vwredsumu_vs_u32mf2_u64m1_tam(vbool64_t mask, vuint32mf2_t vector, vuint64m1_t scalar, size_t vl) {
				return vwredsumu_vs_u32mf2_u64m1_tam(mask, vector, scalar, vl);
				}

clang/utils/TableGen/RISCVVEmitter.cpp

Show First 20 Lines • Show All 188 Lines • ▼ Show 20 Lines	if (RVVI->isMasked()) {
if (RVVI->hasVL()) {		if (RVVI->hasVL()) {
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";		OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
if (RVVI->hasPolicyOperand())		if (RVVI->hasPolicyOperand())
OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(),"		OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(),"
" DefaultPolicy));\n";		" DefaultPolicy));\n";
if (RVVI->hasMaskedOffOperand() &&		if (RVVI->hasMaskedOffOperand() &&
RVVI->getDefaultPolicy() == Policy::TAMA)		RVVI->getDefaultPolicy() == Policy::TAMA)
OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";		OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
		// Masked reduction cases.
		if (!RVVI->hasMaskedOffOperand() && RVVI->hasPassthruOperand() &&
		RVVI->getDefaultPolicy() == Policy::TAMA)
		OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
} else {		} else {
OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";		OS << " std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end());\n";
}		}
} else {		} else {
if (RVVI->hasPolicyOperand())		if (RVVI->hasPolicyOperand())
OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(), "		OS << " Ops.push_back(ConstantInt::get(Ops.back()->getType(), "
"DefaultPolicy));\n";		"DefaultPolicy));\n";
else if (RVVI->hasPassthruOperand() && RVVI->getDefaultPolicy() == Policy::TA)		else if (RVVI->hasPassthruOperand() &&
		RVVI->getDefaultPolicy() == Policy::TA)
OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";		OS << " Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));\n";
}		}

OS << " IntrinsicTypes = {";		OS << " IntrinsicTypes = {";
ListSeparator LS;		ListSeparator LS;
for (const auto &Idx : RVVI->getIntrinsicTypes()) {		for (const auto &Idx : RVVI->getIntrinsicTypes()) {
if (Idx == -1)		if (Idx == -1)
OS << LS << "ResultType";		OS << LS << "ResultType";
▲ Show 20 Lines • Show All 538 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[RISCV][Clang] Support policy functions for Vector Reduction Instructions.ClosedPublic

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Revision Contents

Diff 449338

clang/include/clang/Basic/riscv_vector.td

clang/lib/Support/RISCVVIntrinsicUtils.cpp

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredand.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredor.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vredxor.c

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vwredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfredmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vredand.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vredmax.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vredmin.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vredor.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vredsum.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vredxor.c

clang/test/CodeGen/RISCV/rvv-intrinsics/vwredsum.c

clang/utils/TableGen/RISCVVEmitter.cpp

[RISCV][Clang] Support policy functions for Vector Reduction Instructions.
ClosedPublic