[RISCV] Support LUI+ADDIW in RISCVMergeBaseOffsetOpt::matchLargeOffset.

[craig.topper]

Summary

LUI+ADDIW always produces a simm32. This allows us to always
fold it into a global offset.

[luismarques]

Could this interact badly with the medlow upper address space bound of 0x000000007FFFF7FF?

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

53–55

Minor update here?

[luismarques]

In D126729#3566171, @luismarques wrote:

Could this interact badly with the medlow upper address space bound of 0x000000007FFFF7FF?

I guess not, while the addiw -> addi change isn't safe to represent any simm32 on RV64, it's going to error out in the linker with out-of-bounds %hi and %lo.

To clarify, I was thinking about whether something like this could happen:

Before (non-folded offset computed with addiw):

lui     a0, 0x80000
addiw   a0, a0, -2047
a0 == 0x000000007ffff801

After (folded, using addi):

lui     a0, 0x80000
addi    a0, a0, -2047
a0 == 0xffffffff7ffff801

LGTM.

llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp

bool RISCVMergeBaseOffsetOpt::matchLargeOffset(MachineInstr &TailAdd,
   Register Rt = TailAdd.getOperand(2).getReg();
   Register Reg = Rs == GAReg ? Rt : Rs;
 
   // Can't fold if the register has more than one use.
   if (!MRI->hasOneUse(Reg))
     return false;
   // This can point to an ADDI or a LUI:
   MachineInstr &OffsetTail = *MRI->getVRegDef(Reg);
-  if (OffsetTail.getOpcode() == RISCV::ADDI) {
+  if (OffsetTail.getOpcode() == RISCV::ADDI ||
+      OffsetTail.getOpcode() == RISCV::ADDIW) {
     // The offset value has non zero bits in both %hi and %lo parts.
     // Detect an ADDI that feeds from a LUI instruction.
     MachineOperand &AddiImmOp = OffsetTail.getOperand(2);
     if (AddiImmOp.getTargetFlags() != RISCVII::MO_None)
       return false;
     int64_t OffLo = AddiImmOp.getImm();
     MachineInstr &OffsetLui =
         *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
     MachineOperand &LuiImmOp = OffsetLui.getOperand(1);
     if (OffsetLui.getOpcode() != RISCV::LUI ||
         LuiImmOp.getTargetFlags() != RISCVII::MO_None ||
         !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
       return false;
     Offset = SignExtend64<32>(LuiImmOp.getImm() << 12);
     Offset += OffLo;
-    // RV32 ignores the upper 32 bits.
-    if (!ST->is64Bit())
+    // RV32 ignores the upper 32 bits. ADDIW sign extends the result.
+    if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW)
        Offset = SignExtend64<32>(Offset);
     // We can only fold simm32 offsets.
     if (!isInt<32>(Offset))
       return false;
     LLVM_DEBUG(dbgs() << "  Offset Instrs: " << OffsetTail
                       << "                 " << OffsetLui);
     DeadInstrs.insert(&OffsetTail);
     DeadInstrs.insert(&OffsetLui);

llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll

 if.then:                                          ; preds = %entry
   store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
   br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
 }
 
 ; This test checks that the offset is reconstructed correctly when
 ; "addi" of the big offset has a negative immediate.
 ; without peephole this generates:
 ; lui  a1, %hi(g)
 ; addi a1, a0, %lo(g)
 ; lui  a0, 18     ---> offset
 ; addi a0, a0, -160
 ; add  a0, a0, a1  ---> base + offset.
 define i8* @big_offset_neg_addi() nounwind {
-; RV32-LABEL: big_offset_neg_addi:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, %hi(g+73568)
-; RV32-NEXT:    addi a0, a0, %lo(g+73568)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: big_offset_neg_addi:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(g)
-; RV64-NEXT:    addi a0, a0, %lo(g)
-; RV64-NEXT:    lui a1, 18
-; RV64-NEXT:    addiw a1, a1, -160
-; RV64-NEXT:    add a0, a0, a1
-; RV64-NEXT:    ret
+; CHECK-LABEL: big_offset_neg_addi:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(g+73568)
+; CHECK-NEXT:    addi a0, a0, %lo(g+73568)
+; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([1048576 x i8], [1048576 x i8]* @g, i32 0, i32 73568)
 }
 
 ; This test checks for the case where the offset is only an LUI.
 ; without peephole this generates:
 ; lui  a0, %hi(g)
 ; addi a0, a0, %lo(g)
 ; lui  a1, 128     ---> offset

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(bar-8192)
 ; CHECK-NEXT:    addi a0, a0, %lo(bar-8192)
 ; CHECK-NEXT:    ret
   ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i32 -8192)
 }
 
 define dso_local i32* @big_offset_one_use() local_unnamed_addr nounwind {
-; RV32-LABEL: big_offset_one_use:
-; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    lui a0, %hi(s+16572)
-; RV32-NEXT:    addi a0, a0, %lo(s+16572)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: big_offset_one_use:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    lui a0, %hi(s)
-; RV64-NEXT:    addi a0, a0, %lo(s)
-; RV64-NEXT:    lui a1, 4
-; RV64-NEXT:    addiw a1, a1, 188
-; RV64-NEXT:    add a0, a0, a1
-; RV64-NEXT:    ret
+; CHECK-LABEL: big_offset_one_use:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lui a0, %hi(s+16572)
+; CHECK-NEXT:    addi a0, a0, %lo(s+16572)
+; CHECK-NEXT:    ret
 entry:
   ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
 }
 
 define dso_local i32* @small_offset_one_use() local_unnamed_addr nounwind {
 ; CHECK-LABEL: small_offset_one_use:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lui a0, %hi(s+160)

 ; CHECK-NEXT:    sw a1, %lo(s+160)(a0)
 ; CHECK-NEXT:    ret
 entry:
   store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
   ret void
 }
 
 define i8* @neg_offset() {
-; RV32-LABEL: neg_offset:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, %hi(bar-8191)
-; RV32-NEXT:    addi a0, a0, %lo(bar-8191)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: neg_offset:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(bar)
-; RV64-NEXT:    addi a0, a0, %lo(bar)
-; RV64-NEXT:    lui a1, 1048574
-; RV64-NEXT:    addiw a1, a1, 1
-; RV64-NEXT:    add a0, a0, a1
-; RV64-NEXT:    ret
+; CHECK-LABEL: neg_offset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(bar-8191)
+; CHECK-NEXT:    addi a0, a0, %lo(bar-8191)
+; CHECK-NEXT:    ret
     ret i8* getelementptr inbounds ([0 x i8], [0 x i8]* @bar, i32 0, i32 -8191)
 }
 
 ; This uses an LUI+ADDI on RV64 that does not produce a simm32. For RV32, we'll
 ; truncate the offset.
 define i8* @neg_offset_not_simm32() {
 ; RV32-LABEL: neg_offset_not_simm32:
 ; RV32:       # %bb.0: