[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.

[craig.topper]

Summary

It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+ADDI. Because ADDI uses a sign
extended constant, it's possible that after subtracting it out, we
end up with a simm32 that maps to LUI.

This patch detects this case after removing Lo12 and before shifting
the value for SLLI.

[luismarques]

LGTM.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

13–14

Nit: not needed.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

 //===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVMatInt.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/Support/MathExtras.h"
 using namespace llvm;
 
 static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
   if (!HasRVC)
     return Res.size();
 
   int Cost = 0;
   for (auto Instr : Res) {
     // Assume instructions that aren't listed aren't compressible.
     bool Compressed = false;
static void generateInstSeqImpl(int64_t Val,
   // generateInstSeq. In each recursion, first the lowest 12 bits are removed
   // from the constant and the optimal shift amount, which can be greater than
   // 12 bits if the constant is sparse, is determined. Then, the shifted
   // remaining constant is processed recursively and gets emitted as soon as it
   // fits into 32 bits. The emission of the shifts and additions is subsequently
   // performed when the recursion returns.
 
   int64_t Lo12 = SignExtend64<12>(Val);
-  int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12;
-  int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
-  Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
+  Val = (uint64_t)Val - (uint64_t)Lo12;
+
+  int ShiftAmount = 0;
+  bool Unsigned = false;
+
+  // Val might now be valid for LUI without needing a shift.
+  if (!isInt<32>(Val)) {
+    ShiftAmount = findFirstSet((uint64_t)Val);
+    Val >>= ShiftAmount;
 
     // If the remaining bits don't fit in 12 bits, we might be able to reduce the
     // shift amount in order to use LUI which will zero the lower 12 bits.
-  bool Unsigned = false;
-  if (ShiftAmount > 12 && !isInt<12>(Hi52)) {
-    if (isInt<32>((uint64_t)Hi52 << 12)) {
+    if (ShiftAmount > 12 && !isInt<12>(Val)) {
+      if (isInt<32>((uint64_t)Val << 12)) {
         // Reduce the shift amount and add zeros to the LSBs so it will match LUI.
         ShiftAmount -= 12;
-      Hi52 = (uint64_t)Hi52 << 12;
-    } else if (isUInt<32>((uint64_t)Hi52 << 12) &&
+        Val = (uint64_t)Val << 12;
+      } else if (isUInt<32>((uint64_t)Val << 12) &&
                  ActiveFeatures[RISCV::FeatureStdExtZba]) {
         // Reduce the shift amount and add zeros to the LSBs so it will match
         // LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
         ShiftAmount -= 12;
-      Hi52 = ((uint64_t)Hi52 << 12) | (0xffffffffull << 32);
+        Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
         Unsigned = true;
       }
     }
 
-  // Try to use SLLI_UW for Hi52 when it is uint32 but not int32.
-  if (isUInt<32>((uint64_t)Hi52) && !isInt<32>((uint64_t)Hi52) &&
+    // Try to use SLLI_UW for Val when it is uint32 but not int32.
+    if (isUInt<32>((uint64_t)Val) && !isInt<32>((uint64_t)Val) &&
         ActiveFeatures[RISCV::FeatureStdExtZba]) {
       // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
       // SLLI_UW.
-    Hi52 = ((uint64_t)Hi52) | (0xffffffffull << 32);
+      Val = ((uint64_t)Val) | (0xffffffffull << 32);
       Unsigned = true;
     }
+  }
 
-  generateInstSeqImpl(Hi52, ActiveFeatures, Res);
+  generateInstSeqImpl(Val, ActiveFeatures, Res);
 
+  // Skip shift if we were able to use LUI directly.
+  if (ShiftAmount) {
     if (Unsigned)
       Res.push_back(RISCVMatInt::Inst(RISCV::SLLI_UW, ShiftAmount));
     else
       Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
+  }
+
   if (Lo12)
     Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
 }
 
 static unsigned extractRotateInfo(int64_t Val) {
   // for case: 0b111..1..xxxxxx1..1..
   unsigned LeadingOnes = countLeadingOnes((uint64_t)Val);
   unsigned TrailingOnes = countTrailingOnes((uint64_t)Val);

llvm/test/CodeGen/RISCV/imm.ll

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 524288
 ; RV32I-NEXT:    addi a0, a0, -1365
 ; RV32I-NEXT:    li a1, -1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_neg_2147485013:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    slli a0, a0, 31
+; RV64I-NEXT:    lui a0, 524288
 ; RV64I-NEXT:    addi a0, a0, -1365
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_neg_2147485013:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    li a0, -1
-; RV64IZBA-NEXT:    slli a0, a0, 31
+; RV64IZBA-NEXT:    lui a0, 524288
 ; RV64IZBA-NEXT:    addi a0, a0, -1365
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBB-LABEL: imm_neg_2147485013:
 ; RV64IZBB:       # %bb.0:
-; RV64IZBB-NEXT:    li a0, -1
-; RV64IZBB-NEXT:    slli a0, a0, 31
+; RV64IZBB-NEXT:    lui a0, 524288
 ; RV64IZBB-NEXT:    addi a0, a0, -1365
 ; RV64IZBB-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_neg_2147485013:
 ; RV64IZBS:       # %bb.0:
-; RV64IZBS-NEXT:    li a0, -1365
-; RV64IZBS-NEXT:    bclri a0, a0, 31
+; RV64IZBS-NEXT:    lui a0, 524288
+; RV64IZBS-NEXT:    addi a0, a0, -1365
 ; RV64IZBS-NEXT:    ret
   ret i64 -2147485013
 }
 
 define i64 @imm_12900924131259() {
 ; RV32I-LABEL: imm_12900924131259:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 765952

llvm/test/CodeGen/RISCV/rv64zbs.ll

 ; RV64ZBS-NEXT:    ret
   %and = and i64 %a, -1073741825
   ret i64 %and
 }
 
 define i64 @bclri_i64_31(i64 %a) nounwind {
 ; RV64I-LABEL: bclri_i64_31:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    slli a1, a1, 31
+; RV64I-NEXT:    lui a1, 524288
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBS-LABEL: bclri_i64_31:
 ; RV64ZBS:       # %bb.0:
 ; RV64ZBS-NEXT:    bclri a0, a0, 31
 ; RV64ZBS-NEXT:    ret

llvm/test/MC/RISCV/rv64i-aliases-valid.s

 # CHECK-INST: lui a3, 699051
 # CHECK-INST-NEXT: addiw a3, a3, -1365
 # CHECK-INST-NEXT: slli a3, a3, 1
 # CHECK-ALIAS: lui a3, 699051
 # CHECK-ALIAS-NEXT: addiw a3, a3, -1365
 # CHECK-ALIAS-NEXT: slli a3, a3, 1
 li x13, 0xffffffff55555556
 
+# CHECK-S-OBJ-NOALIAS: lui t0, 524288
+# CHECK-S-OBJ-NOALIAS-NEXT: addi t0, t0, -1365
+# CHECK-S-OBJ: lui t0, 524288
+# CHECK-S-OBJ-NEXT: addi t0, t0, -1365
+li x5, -2147485013
+
 # CHECK-INST: addi a0, zero, 1110
 # CHECK-ALIAS: li a0, 1110
 li a0, %lo(0x123456)
 
 # CHECK-OBJ-NOALIAS: addi a0, zero, 0
 # CHECK-OBJ: R_RISCV_LO12
 li a0, %lo(foo)
 # CHECK-OBJ-NOALIAS: addi a0, zero, 0

llvm/test/MC/RISCV/rv64zbs-aliases-valid.s

 bext x5, x6, 8
 
 # CHECK-S-OBJ-NOALIAS: addi t0, zero, 1365
 # CHECK-S-OBJ-NOALIAS-NEXT: bseti t0, t0, 31
 # CHECK-S-OBJ: li t0, 1365
 # CHECK-S-OBJ-NEXT: bseti t0, t0, 31
 li x5, 2147485013
 
-# CHECK-S-OBJ-NOALIAS: addi t0, zero, -1365
-# CHECK-S-OBJ-NOALIAS-NEXT: bclri t0, t0, 31
-# CHECK-S-OBJ: li t0, -1365
-# CHECK-S-OBJ-NEXT: bclri t0, t0, 31
-li x5, -2147485013
-
 # CHECK-S-OBJ-NOALIAS: lui t1, 572348
 # CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, -1093
 # CHECK-S-OBJ-NOALIAS-NEXT: bclri t1, t1, 44
 # CHECK-S-OBJ-NOALIAS-NEXT: bclri t1, t1, 63
 # CHECK-S-OBJ: lui t1, 572348
 # CHECK-S-OBJ-NEXT: addiw t1, t1, -1093
 # CHECK-S-OBJ-NEXT: bclri t1, t1, 44
 # CHECK-S-OBJ-NEXT: bclri t1, t1, 63