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[RISCV] Improve constant materialization for cases that can use LUI+ADDI instead of LUI+ADDIW.
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Authored by craig.topper on Apr 21 2022, 6:11 PM.

Details

Summary

It's possible that we have a constant that isn't simm32 so we can't
use LUI+ADDIW, but we can use LUI+ADDI. Because ADDI uses a sign
extended constant, it's possible that after subtracting it out, we
end up with a simm32 that maps to LUI.

This patch detects this case after removing Lo12 and before shifting
the value for SLLI.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 21 2022, 6:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 21 2022, 6:11 PM
craig.topper requested review of this revision.Apr 21 2022, 6:11 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 21 2022, 6:11 PM
reames added a subscriber: reames.Apr 25 2022, 9:28 AM
luismarques accepted this revision.Apr 29 2022, 6:06 AM

LGTM.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
13–14

Nit: not needed.

This revision is now accepted and ready to land.Apr 29 2022, 6:06 AM
This revision was landed with ongoing or failed builds.Apr 29 2022, 9:01 AM
This revision was automatically updated to reflect the committed changes.