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Differential D123385

[RISCV] Precommit test for D121881
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Authored by arcbbb on Apr 8 2022, 6:09 AM.

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Reviewers
frasercrmck
rogfer01
craig.topper
khchen
Commits
rGbcb2b86df672: [RISCV] Precommit test for D121881

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arcbbb created this revision.Apr 8 2022, 6:09 AM
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arcbbb added a child revision: D121881: [RISCV][RVV] Select unmasked TU RVV pseudos in a DAG post-process.Apr 8 2022, 6:09 AM
Harbormaster completed remote builds in B158685: Diff 421507.Apr 8 2022, 6:58 AM
frasercrmck added inline comments.Apr 13 2022, 2:20 AM
llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
3

Maybe we should be testing rv32 too?

14

trailing semicolon

34

Typo: AGNOSIC -> AGNOSTIC

Should there be a FIXME that we can use an unmasked instruction here?

56

Again: a FIXME about unmasked instructions?

arcbbb updated this revision to Diff 424936.Apr 25 2022, 9:26 AM

Address @frasercrmck 's comments.

Harbormaster completed remote builds in B161187: Diff 424936.Apr 25 2022, 10:01 AM
This revision was not accepted when it landed; it landed in state Needs Review.Apr 26 2022, 8:15 PM
This revision was landed with ongoing or failed builds.
Closed by commit rGbcb2b86df672: [RISCV] Precommit test for D121881 (authored by arcbbb). · Explain Why
This revision was automatically updated to reflect the committed changes.
arcbbb added a commit: rGbcb2b86df672: [RISCV] Precommit test for D121881.

Revision Contents

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llvm/
test/
CodeGen/
RISCV/
rvv/
96 lines

Diff 425403

llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
frasercrmckUnsubmitted
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Maybe we should be testing rv32 too?

frasercrmck: Maybe we should be testing rv32 too?
declare <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(iXLen);
declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i8>,
<vscale x 1 x i1>,
iXLen, iXLen);
; Use unmasked instruction because the mask operand is allone mask
frasercrmckUnsubmitted
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trailing semicolon

frasercrmck: trailing semicolon
define <vscale x 1 x i8> @test0(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: test0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: ret
entry:
%allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
iXLen %2);
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i1> %allone,
iXLen %2, iXLen 1)
ret <vscale x 1 x i8> %a
}
; FIXME: Use an unmasked TAIL_AGNOSTIC instruction if the tie operand is IMPLICIT_DEF
frasercrmckUnsubmitted
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Typo: AGNOSIC -> AGNOSTIC

Should there be a FIXME that we can use an unmasked instruction here?

frasercrmck: Typo: `AGNOSIC` -> `AGNOSTIC` Should there be a FIXME that we can use an unmasked instruction…
define <vscale x 1 x i8> @test1(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
entry:
%allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
iXLen %2);
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> undef,
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i1> %allone,
iXLen %2, iXLen 0)
ret <vscale x 1 x i8> %a
}
; FIXME: Use an unmasked TU instruction because of the policy operand
frasercrmckUnsubmitted
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Again: a FIXME about unmasked instructions?

frasercrmck: Again: a FIXME about unmasked instructions?
define <vscale x 1 x i8> @test2(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmset.m v0
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, tu, mu
; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
entry:
%allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
iXLen %3);
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %allone,
iXLen %3, iXLen 0)
ret <vscale x 1 x i8> %a
}
; Merge operand is dropped because of the policy operand
define <vscale x 1 x i8> @test3(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vadd.vv v8, v9, v10
; CHECK-NEXT: ret
entry:
%allone = call <vscale x 1 x i1> @llvm.riscv.vmset.nxv1i1(
iXLen %3);
%a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
<vscale x 1 x i8> %2,
<vscale x 1 x i1> %allone,
iXLen %3, iXLen 1)
ret <vscale x 1 x i8> %a
}