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Differential D123364

[RISCV] Precommit test for D122634
ClosedPublic

Authored by • pcwang-thead on Apr 8 2022, 12:05 AM.

Details

Reviewers
lewis-revill
asb
jrtc27
luismarques
craig.topper
Commits
rG6ee890b79e66: [RISCV] Precommit test for D122634
rG360d44e86def: [RISCV] Precommit test for D122634

Diff Detail

Event Timeline

• pcwang-thead created this revision.Apr 8 2022, 12:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 8 2022, 12:05 AM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 25 others. · View Herald Transcript
• pcwang-thead requested review of this revision.Apr 8 2022, 12:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 8 2022, 12:05 AM
Herald added subscribers: llvm-commits, eopXD, MaskRay. · View Herald Transcript
• pcwang-thead mentioned this in D122634: [RISCV] Do not outline CFI instructions when they are needed in EH.Apr 8 2022, 12:25 AM
• pcwang-thead added a child revision: D122634: [RISCV] Do not outline CFI instructions when they are needed in EH.Apr 8 2022, 12:28 AM
Harbormaster completed remote builds in B158632: Diff 421429.Apr 8 2022, 12:50 AM
• pcwang-thead updated this revision to Diff 423045.Apr 15 2022, 1:39 AM

Add test for position instructions and CFI.

Harbormaster completed remote builds in B159797: Diff 423045.Apr 15 2022, 2:55 AM
luismarques accepted this revision.Apr 20 2022, 3:23 AM

LGTM. Don't forget to fix the typo before committing.

llvm/test/CodeGen/RISCV/machine-outliner-position.mir
9

instructions

This revision is now accepted and ready to land.Apr 20 2022, 3:23 AM
• pcwang-thead updated this revision to Diff 424120.Apr 21 2022, 1:07 AM

Rebase and fix typo.

This revision was landed with ongoing or failed builds.Apr 21 2022, 1:09 AM
Closed by commit rG360d44e86def: [RISCV] Precommit test for D122634 (authored by • pcwang-thead). · Explain Why
This revision was automatically updated to reflect the committed changes.
• pcwang-thead added a commit: rG360d44e86def: [RISCV] Precommit test for D122634.
Harbormaster completed remote builds in B160603: Diff 424120.Apr 21 2022, 2:04 AM
• pcwang-thead added a reverting change: rGb1620d40d0f4: Revert "[RISCV] Precommit test for D122634".Apr 21 2022, 5:33 AM
jrtc27 added a comment.Apr 21 2022, 5:52 AM

https://llvm.org/docs/DeveloperPolicy.html:

  • The commit message for the reverting commit should explain why patch is being reverted.

Why was the commit reverted?

• pcwang-thead added a comment.Apr 21 2022, 6:02 AM
In D123364#3464500, @jrtc27 wrote:

https://llvm.org/docs/DeveloperPolicy.html:

  • The commit message for the reverting commit should explain why patch is being reverted.

Why was the commit reverted?

Sorry. This patch caused some errors because there was no nounwind attr in machine-outliner-cfi.mir.

I will add the reason when I recommit it.

• pcwang-thead reopened this revision.Apr 21 2022, 6:15 AM
This revision is now accepted and ready to land.Apr 21 2022, 6:15 AM
• pcwang-thead updated this revision to Diff 424171.Apr 21 2022, 6:16 AM

Add nounwind attr to machine-outliner-cfi.mir.

• pcwang-thead removed a child revision: D122634: [RISCV] Do not outline CFI instructions when they are needed in EH.Apr 21 2022, 6:43 AM
• pcwang-thead added a child revision: D122634: [RISCV] Do not outline CFI instructions when they are needed in EH.
Harbormaster completed remote builds in B160635: Diff 424171.Apr 21 2022, 7:30 AM
This revision was landed with ongoing or failed builds.Apr 21 2022, 9:20 PM
Closed by commit rG6ee890b79e66: [RISCV] Precommit test for D122634 (authored by • pcwang-thead). · Explain Why
This revision was automatically updated to reflect the committed changes.
• pcwang-thead added a commit: rG6ee890b79e66: [RISCV] Precommit test for D122634.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
106 lines
99 lines
58 lines

Diff 424121

llvm/test/CodeGen/RISCV/machine-outliner-cfi.mir

  • This file was added.
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there
# is no need to unwind. CFIs will be stripped when we build outlined functions.
--- |
define void @func1(i32 %a, i32 %b) { ret void }
define void @func2(i32 %a, i32 %b) { ret void }
define void @func3(i32 %a, i32 %b) { ret void }
...
---
name: func1
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: func1
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET
; RV64I-MO-LABEL: name: func1
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET
$x10 = ORI $x10, 1023
CFI_INSTRUCTION offset $x1, 0
$x11 = ORI $x11, 1023
CFI_INSTRUCTION offset $x1, -4
$x12 = ADDI $x10, 17
CFI_INSTRUCTION offset $x1, -8
$x11 = AND $x12, $x11
CFI_INSTRUCTION offset $x1, -12
$x10 = SUB $x10, $x11
PseudoRET
...
---
name: func2
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: func2
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET
; RV64I-MO-LABEL: name: func2
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET
$x10 = ORI $x10, 1023
CFI_INSTRUCTION offset $x1, 0
$x11 = ORI $x11, 1023
CFI_INSTRUCTION offset $x1, -8
$x12 = ADDI $x10, 17
CFI_INSTRUCTION offset $x1, -4
$x11 = AND $x12, $x11
CFI_INSTRUCTION offset $x1, -12
$x10 = SUB $x10, $x11
PseudoRET
...
---
name: func3
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: func3
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET
; RV64I-MO-LABEL: name: func3
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET
$x10 = ORI $x10, 1023
CFI_INSTRUCTION offset $x1, -12
$x11 = ORI $x11, 1023
CFI_INSTRUCTION offset $x1, -8
$x12 = ADDI $x10, 17
CFI_INSTRUCTION offset $x1, -4
$x11 = AND $x12, $x11
CFI_INSTRUCTION offset $x1, 0
$x10 = SUB $x10, $x11
PseudoRET
# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0
# OUTLINED: liveins: $x11, $x10, $x5
# OUTLINED-NEXT: {{ $}}
# OUTLINED-NEXT: $x10 = ORI $x10, 1023
# OUTLINED-NEXT: $x11 = ORI $x11, 1023
# OUTLINED-NEXT: $x12 = ADDI $x10, 17
# OUTLINED-NEXT: $x11 = AND $x12, $x11
# OUTLINED-NEXT: $x10 = SUB $x10, $x11
# OUTLINED-NEXT: $x0 = JALR $x5, 0

llvm/test/CodeGen/RISCV/machine-outliner-position.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV32I-MO %s
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV64I-MO %s
# Position instructions are illegal to outline. The first instruction won't be outlined
# because position instructions break the sequence.
luismarquesUnsubmitted
Not Done
ReplyInline Actions

instructions

luismarques: instructions
--- |
define void @func1(i32 %a, i32 %b) { ret void }
define void @func2(i32 %a, i32 %b) { ret void }
define void @func3(i32 %a, i32 %b) { ret void }
...
---
name: func1
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: func1
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET
; RV64I-MO-LABEL: name: func1
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET
$x10 = ORI $x10, 1023
EH_LABEL <mcsymbol .Ltmp0>
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET
...
---
name: func2
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: func2
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET
; RV64I-MO-LABEL: name: func2
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET
$x10 = ORI $x10, 1023
GC_LABEL <mcsymbol .Ltmp1>
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET
...
---
name: func3
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: func3
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET
; RV64I-MO-LABEL: name: func3
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET
$x10 = ORI $x10, 1023
ANNOTATION_LABEL <mcsymbol .Ltmp2>
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET

llvm/test/CodeGen/RISCV/machine-outliner-throw.ll

  • This file was added.
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mattr=+m -mtriple=riscv64 < %s | FileCheck %s
; Ensure that we won't outline CFIs when they are needed in unwinding.
define i32 @func1(i32 %x) #0 {
; CHECK-LABEL: func1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
; CHECK-NEXT: call __cxa_allocate_exception@plt
; CHECK-NEXT: sw s0, 0(a0)
; CHECK-NEXT: lui a1, %hi(_ZTIi)
; CHECK-NEXT: addi a1, a1, %lo(_ZTIi)
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: call __cxa_throw@plt
entry:
%mul = mul i32 %x, %x
%add = add i32 %mul, 1
%exception = tail call i8* @__cxa_allocate_exception(i64 4)
%0 = bitcast i8* %exception to i32*
store i32 %add, i32* %0
tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
unreachable
}
define i32 @func2(i32 %x) #0 {
; CHECK-LABEL: func2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
; CHECK-NEXT: call __cxa_allocate_exception@plt
; CHECK-NEXT: sw s0, 0(a0)
; CHECK-NEXT: lui a1, %hi(_ZTIi)
; CHECK-NEXT: addi a1, a1, %lo(_ZTIi)
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: call __cxa_throw@plt
entry:
%mul = mul i32 %x, %x
%add = add i32 %mul, 1
%exception = tail call i8* @__cxa_allocate_exception(i64 4)
%0 = bitcast i8* %exception to i32*
store i32 %add, i32* %0
tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
unreachable
}
; CHECK-LABEL: OUTLINED_FUNCTION_0:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd ra, 8(sp)
; CHECK-NEXT: sd s0, 0(sp)
; CHECK-NEXT: mulw a0, a0, a0
; CHECK-NEXT: addiw s0, a0, 1
; CHECK-NEXT: li a0, 4
@_ZTIi = external constant i8*
declare i8* @__cxa_allocate_exception(i64)
declare void @__cxa_throw(i8*, i8*, i8*)
attributes #0 = { minsize noreturn }