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Differential D122961

[RISCV][NFC] Remove some check prefixes as it works the same as FileCheck
ClosedPublic

Authored by Pretty-box on Apr 1 2022, 8:43 PM.

Details

Reviewers
benshi001
craig.topper
frasercrmck
Commits
rG9d453446facb: [RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default

Diff Detail

Event Timeline

Pretty-box created this revision.Apr 1 2022, 8:43 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2022, 8:43 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 27 others. · View Herald Transcript
Pretty-box requested review of this revision.Apr 1 2022, 8:43 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald TranscriptApr 1 2022, 8:43 PM
Harbormaster completed remote builds in B157554: Diff 419927.Apr 1 2022, 8:43 PM
Jimerlife added a reviewer: craig.topper.Apr 1 2022, 9:00 PM
Herald added a subscriber: StephenFan. · View Herald TranscriptApr 1 2022, 9:00 PM
Jimerlife added a reviewer: frasercrmck.Apr 1 2022, 9:02 PM
Jimerlife retitled this revision from [RISCV] Update RISCV rvv test cases to [RISCV][NFC] Update RISCV rvv test cases.
Pretty-box updated this revision to Diff 419942.Apr 1 2022, 11:17 PM
Harbormaster completed remote builds in B157566: Diff 419942.Apr 2 2022, 12:28 AM
frasercrmck accepted this revision.Apr 4 2022, 2:18 AM

LGTM but I'd like just a little extra description about how the tests have been updated.

This revision is now accepted and ready to land.Apr 4 2022, 2:18 AM
Pretty-box retitled this revision from [RISCV][NFC] Update RISCV rvv test cases to [RISCV][NFC] Remove some check prefixes as it works the same as FileCheck.Apr 5 2022, 6:34 PM
This revision was landed with ongoing or failed builds.Apr 5 2022, 8:22 PM
Closed by commit rG9d453446facb: [RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default (authored by Pretty-box, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG9d453446facb: [RISCV][NFC] Remove '--check-prefixes=CHECK' in some cases as they are default.

Revision Contents

Diff 419927

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vnsra-vnsrl.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) { define <8 x i8> @vnsra_v8i16_v8i8_scalar(<8 x i16> %x, i16 %y) {
; CHECK-LABEL: vnsra_v8i16_v8i8_scalar: ; CHECK-LABEL: vnsra_v8i16_v8i8_scalar:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vnsra.wx v8, v8, a0 ; CHECK-NEXT: vnsra.wx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%insert = insertelement <8 x i16> poison, i16 %y, i16 0 %insert = insertelement <8 x i16> poison, i16 %y, i16 0
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmacc_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { define <2 x i16> @vwmacc_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmacc_v2i16: ; CHECK-LABEL: vwmacc_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vle8.v v10, (a1) ; CHECK-NEXT: vle8.v v10, (a1)
; CHECK-NEXT: vwmacc.vv v8, v9, v10 ; CHECK-NEXT: vwmacc.vv v8, v9, v10
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccsu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccsu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { define <2 x i16> @vwmaccsu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccsu_v2i16: ; CHECK-LABEL: vwmaccsu_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vle8.v v10, (a1) ; CHECK-NEXT: vle8.v v10, (a1)
; CHECK-NEXT: vwmaccsu.vv v8, v9, v10 ; CHECK-NEXT: vwmaccsu.vv v8, v9, v10
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) { define <2 x i16> @vwmaccu_v2i16(<2 x i8>* %x, <2 x i8>* %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccu_v2i16: ; CHECK-LABEL: vwmaccu_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vle8.v v10, (a1) ; CHECK-NEXT: vle8.v v10, (a1)
; CHECK-NEXT: vwmaccu.vv v8, v9, v10 ; CHECK-NEXT: vwmaccu.vv v8, v9, v10
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccus_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) { define <2 x i16> @vwmaccus_vx_v2i16(<2 x i8>* %x, i8 %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v2i16: ; CHECK-LABEL: vwmaccus_vx_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9 ; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) { define <2 x i16> @vwmulu_v2i16(<2 x i8>* %x, <2 x i8>* %y) {
; CHECK-LABEL: vwmulu_v2i16: ; CHECK-LABEL: vwmulu_v2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
; CHECK-NEXT: vle8.v v9, (a0) ; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vle8.v v10, (a1) ; CHECK-NEXT: vle8.v v10, (a1)
; CHECK-NEXT: vwmulu.vv v8, v9, v10 ; CHECK-NEXT: vwmulu.vv v8, v9, v10
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llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) { define <vscale x 1 x half> @vfptrunc_nxv1f32_nxv1f16(<vscale x 1 x float> %va) {
; ;
; CHECK-LABEL: vfptrunc_nxv1f32_nxv1f16: ; CHECK-LABEL: vfptrunc_nxv1f32_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfncvt.f.f.w v9, v8 ; CHECK-NEXT: vfncvt.f.f.w v9, v8
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
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llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) { define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsra_wv_nxv1i32_sext: ; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsra.wv v8, v8, v9 ; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64> %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
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llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) { define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsrl_wv_nxv1i32_sext: ; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wv v8, v8, v9 ; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64> %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
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llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) { define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
; CHECK-LABEL: vwmacc_vv_nxv1i32: ; CHECK-LABEL: vwmacc_vv_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vwmacc.vv v10, v8, v9 ; CHECK-NEXT: vwmacc.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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