[InlineAsm] Add support for address operands ("p").

[jonpa]

Summary

This patch adds support for inline assembly address operands using the "p" constraint.

This is in fact broken on X86, see example at https://reviews.llvm.org/D110267 (Nov 23). As suggested there, here is the basic support for "p" and introduction of the C_Memory ConstraintType which fixes this bug on X86 (and also adds support for "p" on SystemZ).

Reasoning:

Memory ("m") and Address ("p") are operands that are selected (and printed) the same way by the backend (i.e. "select address"), but on the other hand they are also different as "p" takes an address present at the source level, while "m" causes the address of a value to be passed (indirect). For example, "p" should not get the mayLoad flag.

The different inline asm operand types are handled in InlineAsm.h but also in TargetLowering: An "m" operand is an InlineAsm::Kind_Mem but also a TargetLowering::C_Memory.

InlineAsm supports different constraint codes for memory operands so that the code gets shifted into its place in Flags. I have reused this for address operands by simply adding a new memory constraint "Constraint_p" for "p". I haven't found a reason yet to add a new InlineAsm::Kind_Address, so addresses are InlineAsm::Kind_Mem with Constraint_p.

In TargetLowering I similarly started out by treating "p" as C_Memory, but we then decided to instead introduce a new C_Address ConstraintType. It seems to make sense to have a different type here as they are in some cases treated differently in SelectionDAGBuilder.

Not sure if it is too confusing to have an address be a Kind_Mem and then a C_Address instead of C_Memory, but it kind of makes sense to me. I could possibly imagine renaming Kind_Mem to Kind_MemOrAddr.

X86:

X86TargetInfo::validateAsmConstraint(): I don't know why not 'm' is accepted here..? I think 'p' should also be recognized here, but the test case passes without it...
X86 test cases in clang/test/CodeGen/asm.c and llvm/test/CodeGen/X86/inline-asm-p-constraint.ll.

CodeGenPrepare:

It seems that addresses could be handled just like memory operands, given that they are handled the same by the back-end. "TODO comments" added for this.

GlobalISel:

@npopov: GlobalISel has not really been handled, but C_Address has been added in switch statements to silence warnings.

[xiangzhangllvm]

I didn't see the 'p' defined in
Machine-Constraints on x86

A question I care about is:
How we (customers) can quickly refer to the meaning of new added constrain 'p'.

[xiangzhangllvm]

X86TargetInfo::validateAsmConstraint(): I don't know why not 'm' is accepted here..?

The answer can be find in function TargetInfo::validateInputConstraint.
Because not all constrains will be checked by validateAsmConstraint.

[jonpa]

Thanks for review!

In D122220#3407060, @xiangzhangllvm wrote:

I didn't see the 'p' defined in
Machine-Constraints on x86

A question I care about is:
How we (customers) can quickly refer to the meaning of new added constrain 'p'.

That is a good point, and I think we need to add a description in the LLVM llanguage manual for 'p' under the section "Supported Constraint Code List". As 'p' is a shared code over targets I think it should be listed in the common section (as it is in gcc documentation link). I updated the patch with this addition - what do you think?

In D122220#3407081, @xiangzhangllvm wrote:

X86TargetInfo::validateAsmConstraint(): I don't know why not 'm' is accepted here..?

The answer can be find in function TargetInfo::validateInputConstraint.
Because not all constrains will be checked by validateAsmConstraint.

Ah, I see: first validateInputConstraint() is called and then only if needed is the target validateAsmConstraint() used. I removed the 'p' handling I had added in SystemZ::validateAsmConstraint() which is actually then not needed/used. I am a little surprised now that this works, as validateInputConstraint() does not call 'Info.setAllowsRegister()' for 'p', which is needed for the SystemZ specific address constraints (see https://reviews.llvm.org/D110267).

[xiangzhangllvm]

In D122220#3408331, @jonpa wrote:

Thanks for review!

In D122220#3407060, @xiangzhangllvm wrote:

I didn't see the 'p' defined in
Machine-Constraints on x86

A question I care about is:
How we (customers) can quickly refer to the meaning of new added constrain 'p'.

That is a good point, and I think we need to add a description in the LLVM llanguage manual for 'p' under the section "Supported Constraint Code List". As 'p' is a shared code over targets I think it should be listed in the common section (as it is in gcc documentation link). I updated the patch with this addition - what do you think?

In D122220#3407081, @xiangzhangllvm wrote:

X86TargetInfo::validateAsmConstraint(): I don't know why not 'm' is accepted here..?

The answer can be find in function TargetInfo::validateInputConstraint.
Because not all constrains will be checked by validateAsmConstraint.

Ah, I see: first validateInputConstraint() is called and then only if needed is the target validateAsmConstraint() used. I removed the 'p' handling I had added in SystemZ::validateAsmConstraint() which is actually then not needed/used. I am a little surprised now that this works, as validateInputConstraint() does not call 'Info.setAllowsRegister()' for 'p', which is needed for the SystemZ specific address constraints (see https://reviews.llvm.org/D110267).

I agree with you, some constraint codes are typically supported by all targets.

[jonpa]

Ping!

It would be nice to get review as we expect this to fix inline assembly address operands on X86, while we also have another patch for SystemZ address operands waiting on this...

[xiangzhangllvm]

Thanks for your job, I am not familiar with the SystemZ part, PLS make sure all tests passed.
(+ Better to sync the clang format)
If no others object it, I'll accepted 1 day later.

[jonpa]

Thanks for your job, I am not familiar with the SystemZ part, PLS make sure all tests passed.
(+ Better to sync the clang format)
If no others object it, I'll accepted 1 day later.

All tests are passing, and I fixed the one format issue that this patch introduced.

It would be great to get review on the common code + X86 changes at this stage. I think I could either commit the SystemZ part as well even if no review is given as it is follows quite trivially, or I could wait with that part and commit it at a later point. The X86 tests should be enough on their own, right?

[xiangzhangllvm]

The X86 tests should be enough on their own, right?

Most the common uses existed in the tests.
If it cause very rarely/corner case fail, (I think almost no customers use it), let we fix it when we meet it.

clang/lib/Basic/Targets/X86.cpp

1494

Did you check the difference with the previous constraint "im" at llvm end.
Looks the C_Address is mostly same with C_Memory, but no relation with C_Immediate.

[jonpa]

clang/lib/Basic/Targets/X86.cpp

1494

No I have not: there are no tests failing due to this change, and what's more is that the previous handling of "p" was actually incorrect (as showed earlier with example), with wrong code resulting.

I would also hope that the address handling in the X86 backend can handle an immediate if it is accepted as an address...

[xiangzhangllvm]

In my eye, the reason we need the "p" is Front End miss handle the constrain "*", so the "m" and "*m" have the same action at qWvod14G9
(both isIndirect)

In IR level the constrain "p" is equal with "m" (TargetLowering::C_Memory + !isIndirect)

llvm/lib/CodeGen/CodeGenPrepare.cpp

4838

I think C_Address the should return false. It is direct mem (!OpInfo.isIndirect). So no need change here.

5621

I think we can handle the C_Address.
As the comment ahead optimizeMemoryInst, this is used to
"Sink addressing mode computation immediate before MemoryInst if doing so
can be done without increasing register pressure."
Anyway that is not a big problem.

[jonpa]

In IR level the constrain "p" is equal with "m" (TargetLowering::C_Memory + !isIndirect)

I am not sure there is such a thing as "m" without the indirect flag ('*')... "m" and "p" are however different as "*m" is used to access memory and "p" typically to load the address into a register (at least that's my understanding so far).

llvm/lib/CodeGen/CodeGenPrepare.cpp

4838

I think actually this should be treated the same as an indirect memory operand since the address can be sunk into user just the same way. So for a C_Address, false should *not* be returned, I think.

5621

Yes, they should be treated the same, I agre...

[xiangzhangllvm]

LGTM, I prefer to accept this patch. Thank you for your effort.

[jonpa]

Thank you for your review! I will commit this within a few days unless someone else has any objections...

[uweigand]

The SystemZ parts LGTM as well. Thanks!

[jonpa]

-no-opaque-pointers added to SystemZ clang test, per 532dc62.

clang/lib/Basic/Targets/SystemZ.h

public:
 
   bool isSPRegName(StringRef RegName) const override {
     return RegName.equals("r15");
   }
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &info) const override;
 
+  std::string convertConstraint(const char *&Constraint) const override {
+    switch (Constraint[0]) {
+    case 'p': // Keep 'p' constraint.
+      return std::string("p");
+    default:
+      break;
+    }
+    return TargetInfo::convertConstraint(Constraint);
+  }
+
   const char *getClobbers() const override {
     // FIXME: Is this really right?
     return "";
   }
 
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::SystemZBuiltinVaList;
   }

clang/lib/Basic/Targets/X86.cpp

std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
   case 'c':
     return std::string("{cx}");
   case 'd':
     return std::string("{dx}");
   case 'S':
     return std::string("{si}");
   case 'D':
     return std::string("{di}");
-  case 'p': // address
-    return std::string("im");
+  case 'p': // Keep 'p' constraint (address).
+    return std::string("p");
   case 't': // top of floating point stack.
     return std::string("{st}");
   case 'u':                        // second from top of floating point stack.
     return std::string("{st(1)}"); // second from top of floating point stack.
   case 'Y':
     switch (Constraint[1]) {
     default:
       // Break from inner switch and fall through (copy single char),

clang/test/CodeGen/SystemZ/systemz-inline-asm-03.c

+// RUN: %clang_cc1 -no-opaque-pointers -triple s390x-linux-gnu -O2 -emit-llvm \
+// RUN:   -o - %s 2>&1 | FileCheck %s
+// REQUIRES: systemz-registered-target
+
+long *A;
+long Idx;
+unsigned long Addr;
+
+unsigned long fun_BD12_p() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD12_p()
+// CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "p" (&A[100]));
+  return Addr;
+}
+
+unsigned long fun_BDX12_p() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX12_p()
+// CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "p" (&A[Idx + 100]));
+  return Addr;
+}
+
+unsigned long fun_BD20_p() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BD20_p()
+// CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "p" (&A[1000]));
+  return Addr;
+}
+
+unsigned long fun_BDX20_p() {
+// CHECK-LABEL: define{{.*}} i64 @fun_BDX20_p()
+// CHECK: call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
+  asm("lay %0, %1" : "=r" (Addr) : "p" (&A[Idx + 1000]));
+  return Addr;
+}

clang/test/CodeGen/asm.c

int t32(int cond)
   asm goto("testl %0, %0; jne %l1;" :: "r"(cond)::label_true, loop);
   // CHECK: callbr void asm sideeffect "testl $0, $0; jne ${1:l};", "r,i,i,~{dirflag},~{fpsr},~{flags}"(i32 %0, i8* blockaddress(@t32, %label_true), i8* blockaddress(@t32, %loop)) #1
   return 0;
 loop:
   return 0;
 label_true:
   return 1;
 }
+
+void *t33(void *ptr)
+{
+  void *ret;
+  asm ("lea %1, %0" : "=r" (ret) : "p" (ptr));
+  return ret;
+
+  // CHECK: @t33
+  // CHECK: %1 = call i8* asm "lea $1, $0", "=r,p,~{dirflag},~{fpsr},~{flags}"(i8* %0)
+}

llvm/docs/LangRef.rst

 and GCC likely indicates a bug in LLVM.
 
 Some constraint codes are typically supported by all targets:
 
 - ``r``: A register in the target's general purpose register class.
 - ``m``: A memory address operand. It is target-specific what addressing modes
   are supported, typical examples are register, or register + register offset,
   or register + immediate offset (of some target-specific size).
+- ``p``: An address operand. Similar to ``m``, but used by "load address"
+  type instructions without touching memory.
 - ``i``: An integer constant (of target-specific width). Allows either a simple
   immediate, or a relocatable value.
 - ``n``: An integer constant -- *not* including relocatable values.
 - ``s``: An integer constant, but allowing *only* relocatable values.
 - ``X``: Allows an operand of any kind, no constraint whatsoever. Typically
   useful to pass a label for an asm branch or call.
 
   .. FIXME: but that surely isn't actually okay to jump out of an asm

llvm/include/llvm/CodeGen/TargetLowering.h

public:
   virtual bool ExpandInlineAsm(CallInst *) const {
     return false;
   }
 
   enum ConstraintType {
     C_Register,            // Constraint represents specific register(s).
     C_RegisterClass,       // Constraint represents any of register(s) in class.
     C_Memory,              // Memory constraint.
+    C_Address,             // Address constraint.
     C_Immediate,           // Requires an immediate.
     C_Other,               // Something else.
     C_Unknown              // Unsupported constraint.
   };
 
   enum ConstraintWeight {
     // Generic weights.
     CW_Invalid  = -1,     // No match.

 
   virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
     if (ConstraintCode == "m")
       return InlineAsm::Constraint_m;
     if (ConstraintCode == "o")
       return InlineAsm::Constraint_o;
     if (ConstraintCode == "X")
       return InlineAsm::Constraint_X;
+    if (ConstraintCode == "p")
+      return InlineAsm::Constraint_p;
     return InlineAsm::Constraint_Unknown;
   }
 
   /// Try to replace an X constraint, which matches anything, with another that
   /// has more specific requirements based on the type of the corresponding
   /// operand.  This returns null if there is no replacement to make.
   virtual const char *LowerXConstraint(EVT ConstraintVT) const;
 

llvm/include/llvm/IR/InlineAsm.h

enum : uint32_t {
     // Inline asm operands map to multiple SDNode / MachineInstr operands.
     // The first operand is an immediate describing the asm operand, the low
     // bits is the kind:
     Kind_RegUse = 1,             // Input register, "r".
     Kind_RegDef = 2,             // Output register, "=r".
     Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
     Kind_Clobber = 4,            // Clobbered register, "~r".
     Kind_Imm = 5,                // Immediate.
-    Kind_Mem = 6,                // Memory operand, "m".
+    Kind_Mem = 6,                // Memory operand, "m", or an address, "p".
 
     // Memory constraint codes.
     // These could be tablegenerated but there's little need to do that since
     // there's plenty of space in the encoding to support the union of all
     // constraint codes for all targets.
+    // Addresses are included here as they need to be treated the same by the
+    // backend, the only difference is that they are not used to actaully
+    // access memory by the instruction.
     Constraint_Unknown = 0,
     Constraint_es,
     Constraint_i,
     Constraint_m,
     Constraint_o,
     Constraint_v,
     Constraint_A,
     Constraint_Q,
     Constraint_R,
     Constraint_S,
     Constraint_T,
     Constraint_Um,
     Constraint_Un,
     Constraint_Uq,
     Constraint_Us,
     Constraint_Ut,
     Constraint_Uv,
     Constraint_Uy,
     Constraint_X,
     Constraint_Z,
     Constraint_ZC,
     Constraint_Zy,
-    Constraints_Max = Constraint_Zy,
+
+    // Address constraints
+    Constraint_p,
+
+    Constraints_Max = Constraint_p,
     Constraints_ShiftAmount = 16,
 
     Flag_MatchingOperand = 0x80000000
   };
 
   static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
     assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
     assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind");
static StringRef getMemConstraintName(unsigned Constraint) {
     case InlineAsm::Constraint_X:
       return "X";
     case InlineAsm::Constraint_Z:
       return "Z";
     case InlineAsm::Constraint_ZC:
       return "ZC";
     case InlineAsm::Constraint_Zy:
       return "Zy";
+    case InlineAsm::Constraint_p:
+      return "p";
     default:
       llvm_unreachable("Unknown memory constraint");
     }
   }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_IR_INLINEASM_H

llvm/lib/CodeGen/CodeGenPrepare.cpp

static bool IsOperandAMemoryOperand(CallInst *CI, InlineAsm *IA, Value *OpVal,
   TargetLowering::AsmOperandInfoVector TargetConstraints =
       TLI.ParseConstraints(F->getParent()->getDataLayout(), &TRI, *CI);
 
   for (TargetLowering::AsmOperandInfo &OpInfo : TargetConstraints) {
     // Compute the constraint code and ConstraintType to use.
     TLI.ComputeConstraintToUse(OpInfo, SDValue());
 
     // If this asm operand is our Value*, and if it isn't an indirect memory
-    // operand, we can't fold it!
+    // operand, we can't fold it!  TODO: Also handle C_Address?
     if (OpInfo.CallOperandVal == OpVal &&
         (OpInfo.ConstraintType != TargetLowering::C_Memory ||
          !OpInfo.isIndirect))
       return false;
   }
 
   return true;
 }
const TargetRegisterInfo *TRI =
       TM->getSubtargetImpl(*CS->getFunction())->getRegisterInfo();
   TargetLowering::AsmOperandInfoVector TargetConstraints =
       TLI->ParseConstraints(*DL, TRI, *CS);
   unsigned ArgNo = 0;
   for (TargetLowering::AsmOperandInfo &OpInfo : TargetConstraints) {
     // Compute the constraint code and ConstraintType to use.
     TLI->ComputeConstraintToUse(OpInfo, SDValue());
 
+    // TODO: Also handle C_Address?
     if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
         OpInfo.isIndirect) {
       Value *OpVal = CS->getArgOperand(ArgNo++);
       MadeChange |= optimizeMemoryInst(CS, OpVal, OpVal->getType(), ~0u);
     } else if (OpInfo.Type == InlineAsm::isInput)
       ArgNo++;
   }
 

llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp

static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
   case TargetLowering::C_Other:
   case TargetLowering::C_Unknown:
     return 0;
   case TargetLowering::C_Register:
     return 1;
   case TargetLowering::C_RegisterClass:
     return 2;
   case TargetLowering::C_Memory:
+  case TargetLowering::C_Address:
     return 3;
   }
   llvm_unreachable("Invalid constraint type");
 }
 
 static void chooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
                              const TargetLowering *TLI) {
   assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
for (unsigned int i = 0, e = ResRegs.size(); i < e; i++) {
     }
     case TargetLowering::C_Immediate:
     case TargetLowering::C_Other:
       LLVM_DEBUG(
           dbgs() << "Cannot lower target specific output constraints yet\n");
       return false;
     case TargetLowering::C_Memory:
       break; // Already handled.
+    case TargetLowering::C_Address:
+      break; // Silence warning.
     case TargetLowering::C_Unknown:
       LLVM_DEBUG(dbgs() << "Unexpected unknown constraint\n");
       return false;
     }
   }
 
   return true;
 }

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

getRegistersForValue(SelectionDAG &DAG, const SDLoc &DL,
                      SDISelAsmOperandInfo &RefOpInfo) {
   LLVMContext &Context = *DAG.getContext();
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
   MachineFunction &MF = DAG.getMachineFunction();
   SmallVector<unsigned, 4> Regs;
   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
 
-  // No work to do for memory operations.
-  if (OpInfo.ConstraintType == TargetLowering::C_Memory)
+  // No work to do for memory/address operands.
+  if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
+      OpInfo.ConstraintType == TargetLowering::C_Address)
     return None;
 
   // If this is a constraint for a single physreg, or a constraint for a
   // register class, find it.
   unsigned AssignedReg;
   const TargetRegisterClass *RC;
   std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint(
       &TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
     if (OpInfo.hasMatchingInput()) {
       SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
       patchMatchingInput(OpInfo, Input, DAG);
     }
 
     // Compute the constraint code and ConstraintType to use.
     TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
 
-    if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
-        OpInfo.Type == InlineAsm::isClobber)
+    if ((OpInfo.ConstraintType == TargetLowering::C_Memory &&
+         OpInfo.Type == InlineAsm::isClobber) ||
+        OpInfo.ConstraintType == TargetLowering::C_Address)
       continue;
 
     // If this is a memory input, and if the operand is not indirect, do what we
     // need to provide an address for the memory input.
     if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
         !OpInfo.isIndirect) {
       assert((OpInfo.isMultipleAlternative ||
               (OpInfo.Type == InlineAsm::isInput)) &&
auto DetectWriteToReservedRegister = [&]() {
           const char *RegName = TRI.getName(Reg);
           emitInlineAsmError(Call, "write to reserved register '" +
                                        Twine(RegName) + "'");
           return true;
         }
       }
       return false;
     };
+    assert((OpInfo.ConstraintType != TargetLowering::C_Address ||
+            (OpInfo.Type == InlineAsm::isInput &&
+             !OpInfo.isMatchingInputConstraint())) &&
+           "Only address as input operand is allowed.");
 
     switch (OpInfo.Type) {
     case InlineAsm::isOutput:
       if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
         unsigned ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
case InlineAsm::isInput: {
         unsigned ResOpType =
           InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
         AsmNodeOperands.push_back(DAG.getTargetConstant(
             ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
         llvm::append_range(AsmNodeOperands, Ops);
         break;
       }
 
-      if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
-        assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
+      if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
+          OpInfo.ConstraintType == TargetLowering::C_Address) {
+        assert((OpInfo.isIndirect ||
+                OpInfo.ConstraintType != TargetLowering::C_Memory) &&
+               "Operand must be indirect to be a mem!");
         assert(InOperandVal.getValueType() ==
                    TLI.getPointerTy(DAG.getDataLayout()) &&
                "Memory operands expect pointer values");
 
         unsigned ConstraintID =
             TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
         assert(ConstraintID != InlineAsm::Constraint_Unknown &&
                "Failed to convert memory constraint code to constraint id.");
if (OpInfo.Type == InlineAsm::isOutput) {
         break;
       case TargetLowering::C_Immediate:
       case TargetLowering::C_Other:
         Val = TLI.LowerAsmOutputForConstraint(Chain, Flag, getCurSDLoc(),
                                               OpInfo, DAG);
         break;
       case TargetLowering::C_Memory:
         break; // Already handled.
+      case TargetLowering::C_Address:
+        break; // Silence warning.
       case TargetLowering::C_Unknown:
         assert(false && "Unexpected unknown constraint");
       }
 
       // Indirect output manifest as stores. Record output chains.
       if (OpInfo.isIndirect) {
         const Value *Ptr = OpInfo.CallOperandVal;
         assert(Ptr && "Expected value CallOperandVal for indirect asm operand");

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (S == 1) {
     switch (Constraint[0]) {
     default: break;
     case 'r':
       return C_RegisterClass;
     case 'm': // memory
     case 'o': // offsetable
     case 'V': // not offsetable
       return C_Memory;
+    case 'p': // Address.
+      return C_Address;
     case 'n': // Simple Integer
     case 'E': // Floating Point Constant
     case 'F': // Floating Point Constant
       return C_Immediate;
     case 'i': // Simple Integer or Relocatable Constant
     case 's': // Relocatable Constant
-    case 'p': // Address.
     case 'X': // Allow ANY value.
     case 'I': // Target registers.
     case 'J':
     case 'K':
     case 'L':
     case 'M':
     case 'N':
     case 'O':
static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
   case TargetLowering::C_Other:
   case TargetLowering::C_Unknown:
     return 0;
   case TargetLowering::C_Register:
     return 1;
   case TargetLowering::C_RegisterClass:
     return 2;
   case TargetLowering::C_Memory:
+  case TargetLowering::C_Address:
     return 3;
   }
   llvm_unreachable("Invalid constraint type");
 }
 
 /// Examine constraint type and operand type and determine a weight value.
 /// This object must already have been set up with the operand type
 /// and the current alternative constraint selected.

llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

SelectInlineAsmMemoryOperand(const SDValue &Op,
   case InlineAsm::Constraint_S:
     // Accept an address with a long displacement, but no index.
     Form = SystemZAddressingMode::FormBD;
     DispRange = SystemZAddressingMode::Disp20Only;
     break;
   case InlineAsm::Constraint_T:
   case InlineAsm::Constraint_m:
   case InlineAsm::Constraint_o:
+  case InlineAsm::Constraint_p:
     // Accept an address with a long displacement and an index.
     // m works the same as T, as this is the most general case.
     // We don't really have any special handling of "offsettable"
     // memory addresses, so just treat o the same as m.
     Form = SystemZAddressingMode::FormBDXNormal;
     DispRange = SystemZAddressingMode::Disp20Only;
     break;
   }

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
   SDValue Op0, Op1, Op2, Op3, Op4;
   switch (ConstraintID) {
   default:
     llvm_unreachable("Unexpected asm memory constraint");
   case InlineAsm::Constraint_o: // offsetable        ??
   case InlineAsm::Constraint_v: // not offsetable    ??
   case InlineAsm::Constraint_m: // memory
   case InlineAsm::Constraint_X:
+  case InlineAsm::Constraint_p: // address
     if (!selectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
       return true;
     break;
   }
 
   OutOps.push_back(Op0);
   OutOps.push_back(Op1);
   OutOps.push_back(Op2);

llvm/test/CodeGen/SystemZ/inline-asm-addr.ll

+; RUN: llc -mtriple=s390x-linux-gnu < %s | FileCheck %s
+
+@Addr = global i64 0, align 8
+@A = global i64* null, align 8
+@Idx = global i64 0, align 8
+
+define i64 @fun_BD12_p() {
+; CHECK-LABEL: fun_BD12_p:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 100
+  %1 = tail call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BDX12_p() {
+; CHECK-LABEL: fun_BDX12_p:
+; CHECK: #APP
+; CHECK: lay  %r2, 800(%r1,%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 100
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}
+
+define i64 @fun_BD20_p() {
+; CHECK-LABEL: fun_BD20_p:
+; CHECK: #APP
+; CHECK: lay  %r2, 8000(%r1)
+entry:
+  %0 = load i64*, i64** @A
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 1000
+  %1 = tail call i64 asm "lay $0, $1", "=r,p"(i64* nonnull %arrayidx)
+  store i64 %1, i64* @Addr
+  ret i64 %1
+}
+
+define i64 @fun_BDX20_p() {
+; CHECK-LABEL: fun_BDX20_p:
+; CHECK: #APP
+; CHECK: lay  %r2, 8000(%r1,%r2)
+entry:
+  %0 = load i64*, i64** @A
+  %1 = load i64, i64* @Idx
+  %add = add nsw i64 %1, 1000
+  %arrayidx = getelementptr inbounds i64, i64* %0, i64 %add
+  %2 = tail call i64 asm "lay $0, $1", "=r,p"(i64* %arrayidx)
+  store i64 %2, i64* @Addr
+  ret i64 %2
+}

llvm/test/CodeGen/X86/inline-asm-p-constraint.ll

+; RUN: llc -mtriple=x86_64-unknown-unknown -no-integrated-as < %s 2>&1 | FileCheck %s
+
+define i8* @foo(i8* %ptr) {
+; CHECK-LABEL: foo:
+  %1 = tail call i8* asm "lea $1, $0", "=r,p,~{dirflag},~{fpsr},~{flags}"(i8* %ptr)
+; CHECK:      #APP
+; CHECK-NEXT: lea (%rdi), %rax
+; CHECK-NEXT: #NO_APP
+  ret i8* %1
+; CHECK-NEXT: retq
+}