Because Verilog uses the backtick instead of hash for preprocessor
directives, we replaced is(tok::hash) with a new function isPPHash.
UnwrappedLineParser::parseBlock has more flags, so we used a bit
field.
We need to lex the backtick, and the lexer had problems with that. So
we modified how the lexer looks for whitespace.
I don't feel "InstancePorts" is clear here I assume this is a Verilog thing, if we are going to have Verilog specific options I think they should be prefixed with the name
VerilogBreakBetweenInstancePorts