User Details
User Details
- User Since
- Feb 11 2022, 2:39 PM (59 w, 1 d)
Today
Today
sstwcw committed rGfeb585e7d62c: [clang-format] Handle Verilog struct literals (authored by sstwcw).
[clang-format] Handle Verilog struct literals
[clang-format] Handle enum in Verilog
sstwcw updated the diff for D147327: [clang-format] Add option for having one port per line in Verilog.
- Use shorter conditions
Yesterday
Yesterday
sstwcw updated the diff for D147327: [clang-format] Add option for having one port per line in Verilog.
Generate doc
sstwcw retitled D147327: [clang-format] Add option for having one port per line in Verilog from [clang-format] Add option for having one port on a line in Verilog to [clang-format] Add option for having one port per line in Verilog.
sstwcw requested review of D147329: [clang-format] Handle Verilog struct literals.
sstwcw requested review of D147328: [clang-format] Handle enum in Verilog.
sstwcw requested review of D147327: [clang-format] Add option for having one port per line in Verilog.
NOTE: Clang-Format Team Automated Review Comment
Sun, Mar 26
Sun, Mar 26
sstwcw committed rG6cef325481a8: [clang-format] Don't squash Verilog escaped identifiers (authored by sstwcw).
[clang-format] Don't squash Verilog escaped identifiers
Sat, Mar 25
Sat, Mar 25
sstwcw committed rGf90668c8ccc5: [clang-format] Handle Verilog assign statements (authored by sstwcw).
[clang-format] Handle Verilog assign statements
sstwcw committed rG0e01c3d28217: [clang-format] More work on space around operators in Verilog (authored by sstwcw).
[clang-format] More work on space around operators in Verilog
Wed, Mar 22
Wed, Mar 22
sstwcw added inline comments to D146401: [clang-format] Don't squash Verilog escaped identifiers.
Sun, Mar 19
Sun, Mar 19
sstwcw updated the diff for D146403: [clang-format] More work on space around operators in Verilog.
sstwcw added a project to D146403: [clang-format] More work on space around operators in Verilog: Restricted Project.
sstwcw added a project to D146402: [clang-format] Handle Verilog assign statements: Restricted Project.
sstwcw requested review of D146403: [clang-format] More work on space around operators in Verilog.
sstwcw requested review of D146402: [clang-format] Handle Verilog assign statements.
sstwcw added a project to D146401: [clang-format] Don't squash Verilog escaped identifiers: Restricted Project.
sstwcw requested review of D146401: [clang-format] Don't squash Verilog escaped identifiers.
sstwcw committed rGb688b58f83ce: [clang-format] Fix non-case colons in Verilog case lines (authored by sstwcw).
[clang-format] Fix non-case colons in Verilog case lines
Wed, Mar 15
Wed, Mar 15
sstwcw added inline comments to D145888: [clang-format] Fix non-case colons in Verilog case lines.
Mon, Mar 13
Mon, Mar 13
sstwcw committed rGa1f8bab9bad7: [clang-format] Recognize Verilog always blocks (authored by sstwcw).
[clang-format] Recognize Verilog always blocks
Sun, Mar 12
Sun, Mar 12
sstwcw added a project to D145888: [clang-format] Fix non-case colons in Verilog case lines: Restricted Project.
sstwcw requested review of D145888: [clang-format] Fix non-case colons in Verilog case lines.
Fri, Mar 10
Fri, Mar 10
sstwcw updated the summary of D145794: [clang-format] Recognize Verilog always blocks.
sstwcw requested review of D145794: [clang-format] Recognize Verilog always blocks.
Feb 19 2023
Feb 19 2023
sstwcw committed rG6e473aeffdc1: [clang-format] Put ports on separate lines in Verilog module headers (authored by sstwcw).
[clang-format] Put ports on separate lines in Verilog module headers
sstwcw added a comment to D144355: [clang-format][NFC] Clean up nullptr comparison style.
@MyDeveloperDay Looking at the return lines in the functions in FormatToken.h got me to check the similar functions not changed by this patch. And I noticed that the final == in isCSharpKeyword seems to return true when the token is not a keyword.
sstwcw added inline comments to D143825: [clang-format] Put ports on separate lines in Verilog module headers.
Feb 17 2023
Feb 17 2023
sstwcw updated the diff for D143825: [clang-format] Put ports on separate lines in Verilog module headers.
- add tests
sstwcw added inline comments to D143825: [clang-format] Put ports on separate lines in Verilog module headers.
Feb 11 2023
Feb 11 2023
sstwcw added a project to D143825: [clang-format] Put ports on separate lines in Verilog module headers: Restricted Project.
sstwcw requested review of D143825: [clang-format] Put ports on separate lines in Verilog module headers.
Feb 5 2023
Feb 5 2023
sstwcw committed rGcad708b9a1ec: [clang-format] Recognize Verilog non-blocking assignment (authored by sstwcw).
[clang-format] Recognize Verilog non-blocking assignment
Feb 4 2023
Feb 4 2023
sstwcw updated the diff for D142891: [clang-format] Recognize Verilog non-blocking assignment.
- add parentheses
- rename field
Feb 2 2023
Feb 2 2023
sstwcw added inline comments to D142891: [clang-format] Recognize Verilog non-blocking assignment.
sstwcw updated the diff for D142891: [clang-format] Recognize Verilog non-blocking assignment.
- add parentheses
Jan 30 2023
Jan 30 2023
sstwcw added a project to D142891: [clang-format] Recognize Verilog non-blocking assignment: Restricted Project.
sstwcw requested review of D142891: [clang-format] Recognize Verilog non-blocking assignment.
Nov 13 2022
Nov 13 2022
sstwcw added a comment to D137181: [clang-format] Don't use 'PPIndentWidth' inside multi-line macros.
Can you make TokenAnnotator::printDebugInfo print PPLevel?
Nov 6 2022
Nov 6 2022
sstwcw added a comment to D137181: [clang-format] Don't use 'PPIndentWidth' inside multi-line macros.
Here is one problem:
Nov 3 2022
Nov 3 2022
It does some more than D137052. But the additional stuff is not very important and no one can review it. So I am closing it.
Nov 1 2022
Nov 1 2022
sstwcw added a comment to D137052: [clang-format] Don't skip #else/#elif of #if 0.
It just occurred to me that klimek is the one who added all this stuff. Why didn't you include him as a reviewer?
Thanks for fixing the problem I caused.
Oct 30 2022
Oct 30 2022
sstwcw added a comment to D137052: [clang-format] Don't skip #else/#elif of #if 0.
This patch fixes the regression caused by 2183fe2 while introducing a new regression. But in my opinion the new regression is less of a problem than the old one. Therefore I think it is okay.
Oct 29 2022
Oct 29 2022
sstwcw committed rGd5be1550f140: [clang-format] Don't crash on malformed preprocessor conditions (authored by sstwcw).
[clang-format] Don't crash on malformed preprocessor conditions
Oct 25 2022
Oct 25 2022
sstwcw added inline comments to D135972: [clang-format] Don't crash on malformed preprocessor conditions.
sstwcw updated the diff for D135972: [clang-format] Don't crash on malformed preprocessor conditions.
Oct 23 2022
Oct 23 2022
sstwcw updated the diff for D135740: [clang-format] Fix multiple preprocessor if sections parsing incorrectly.
- Merge
- use ArrayRef
sstwcw added inline comments to D135972: [clang-format] Don't crash on malformed preprocessor conditions.
sstwcw updated the diff for D135972: [clang-format] Don't crash on malformed preprocessor conditions.
Oct 14 2022
Oct 14 2022
sstwcw updated the diff for D135740: [clang-format] Fix multiple preprocessor if sections parsing incorrectly.
- correct spelling
sstwcw updated the diff for D135972: [clang-format] Don't crash on malformed preprocessor conditions.
sstwcw added a comment to D135740: [clang-format] Fix multiple preprocessor if sections parsing incorrectly.
sstwcw updated the diff for D135740: [clang-format] Fix multiple preprocessor if sections parsing incorrectly.
- add tests
sstwcw requested review of D135972: [clang-format] Don't crash on malformed preprocessor conditions.
Oct 11 2022
Oct 11 2022
sstwcw abandoned D135372: [clang-format] Fix for #58188.
I am closing it now there is D135740.
sstwcw added a project to D135740: [clang-format] Fix multiple preprocessor if sections parsing incorrectly: Restricted Project.
Should I add a test with comments to be aligned like in the bug report? I was not sure because I didn't find an existing test for alignment of comments.
sstwcw requested review of D135740: [clang-format] Fix multiple preprocessor if sections parsing incorrectly.
Oct 6 2022
Oct 6 2022
sstwcw added a comment to D135372: [clang-format] Fix for #58188.
The problem that remains is this, as I explained in the issue. The second branch of the second block is not indented.
sstwcw updated the diff for D135372: [clang-format] Fix for #58188.
sstwcw added a comment to D135372: [clang-format] Fix for #58188.
sstwcw requested review of D135372: [clang-format] Fix for #58188.
Sep 21 2022
Sep 21 2022
sstwcw added a comment to D134329: [clang-format][NFC] Reformat clang/lib/Format using 6257832bf94f.
Did you leave out clang/include/clang/Format and clang/unittests/Format?
Sep 16 2022
Sep 16 2022
sstwcw committed rGe5964223d99a: [clang-format] Fix template arguments in macros (authored by sstwcw).
[clang-format] Fix template arguments in macros
sstwcw committed rG2183fe2160fb: [clang-format] Parse the else part of `#if 0` (authored by sstwcw).
[clang-format] Parse the else part of `#if 0`
Sep 15 2022
Sep 15 2022
sstwcw added a project to D133954: [clang-format] Fix template arguments in macros: Restricted Project.
sstwcw requested review of D133954: [clang-format] Fix template arguments in macros.
Sep 13 2022
Sep 13 2022
sstwcw added inline comments to D133635: [clang-format] Don't insert braces for loops with a null statement.
Sep 10 2022
Sep 10 2022
sstwcw updated the summary of D133647: [clang-format] Parse the else part of `#if 0`.
sstwcw added a project to D133647: [clang-format] Parse the else part of `#if 0`: Restricted Project.
sstwcw requested review of D133647: [clang-format] Parse the else part of `#if 0`.
Jul 28 2022
Jul 28 2022
sstwcw added a comment to D88299: [clang-format] Add MacroUnexpander..
It looks like some of the braces in the code should be removed for example those surrounding one-line for bodies. Sorry if it is not my job to point this out, but MyDeveloperDay has not said anything.
[clang-format] Handle Verilog attributes
sstwcw committed rGc88719483c69: [clang-format] Handle Verilog case statements (authored by sstwcw).
[clang-format] Handle Verilog case statements
sstwcw committed rGb67ee18e85f3: [clang-format] Handle Verilog user-defined primitives (authored by sstwcw).
[clang-format] Handle Verilog user-defined primitives
[clang-format] Handle Verilog modules
[clang-format] Handle Verilog blocks
sstwcw committed rGf93182a88788: [clang-format] Handle Verilog numbers and operators (authored by sstwcw).
[clang-format] Handle Verilog numbers and operators
Jul 25 2022
Jul 25 2022
sstwcw added a comment to D126845: [clang-format] Handle Verilog numbers and operators.
Are there any problems with this revision? The ones that depend on it are approved.
Jul 11 2022
Jul 11 2022
sstwcw added inline comments to D128712: [clang-format] Handle Verilog modules.
sstwcw updated the diff for D128712: [clang-format] Handle Verilog modules.
- take out check
- use boolean as boolean