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Differential D121002

[DAG] Don't convert undef to 0 when creating buildvector
ClosedPublic

Authored by dmgreen on Mar 4 2022, 8:46 AM.

Details

Reviewers
RKSimon
craig.topper
nemanjai
spatel
Commits
rG4388f4f77694: [DAG] Don't convert undef to 0 when creating buildvector
Summary

When inserting undef into buildvectors created from shuffles of buildvectors, we convert elements to the largest needed type. This had the effect of converting undef into 0, which isn't needed as the buildvector implicitly truncates and trunc(zext(undef)) == undef.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 4 2022, 8:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2022, 8:46 AM
Herald added subscribers: ecnelises, hiraditya. · View Herald Transcript
dmgreen requested review of this revision.Mar 4 2022, 8:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 4 2022, 8:46 AM
RKSimon accepted this revision.Mar 4 2022, 8:55 AM

LGTM

This revision is now accepted and ready to land.Mar 4 2022, 8:55 AM
Harbormaster completed remote builds in B152606: Diff 413026.Mar 4 2022, 9:08 AM
probinson added a subscriber: probinson.Mar 4 2022, 10:28 AM
probinson added inline comments.
llvm/test/CodeGen/AArch64/arm64-vshuffle.ll
4

I think FileCheck is case-sensitive with regard to suffixes? So should be CHECK-LABEL. Willing to be proven wrong but that was my impression.

dmgreen added a comment.Mar 6 2022, 10:09 AM

Oh yeah, good point. Will do, thanks.

This revision was landed with ongoing or failed builds.Mar 6 2022, 10:35 AM
Closed by commit rG4388f4f77694: [DAG] Don't convert undef to 0 when creating buildvector (authored by dmgreen). · Explain Why
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG4388f4f77694: [DAG] Don't convert undef to 0 when creating buildvector.

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
7 lines
test/
CodeGen/
AArch64/
16 lines
PowerPC/
22 lines
95 lines
22 lines
67 lines
Thumb2/
17 lines

Diff 413305

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 21,633 Lines • ▼ Show 20 Linesstatic SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN,
// BUILD_VECTOR requires all inputs to be of the same type, find the // BUILD_VECTOR requires all inputs to be of the same type, find the
// maximum type and extend them all. // maximum type and extend them all.
EVT SVT = VT.getScalarType(); EVT SVT = VT.getScalarType();
if (SVT.isInteger()) if (SVT.isInteger())
for (SDValue &Op : Ops) for (SDValue &Op : Ops)
SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT); SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
if (SVT != VT.getScalarType()) if (SVT != VT.getScalarType())
for (SDValue &Op : Ops) for (SDValue &Op : Ops)
Op = TLI.isZExtFree(Op.getValueType(), SVT) Op = Op.isUndef() ? DAG.getUNDEF(SVT)
: (TLI.isZExtFree(Op.getValueType(), SVT)
? DAG.getZExtOrTrunc(Op, SDLoc(SVN), SVT) ? DAG.getZExtOrTrunc(Op, SDLoc(SVN), SVT)
: DAG.getSExtOrTrunc(Op, SDLoc(SVN), SVT); : DAG.getSExtOrTrunc(Op, SDLoc(SVN), SVT));
return DAG.getBuildVector(VT, SDLoc(SVN), Ops); return DAG.getBuildVector(VT, SDLoc(SVN), Ops);
} }
// Match shuffles that can be converted to any_vector_extend_in_reg. // Match shuffles that can be converted to any_vector_extend_in_reg.
// This is often generated during legalization. // This is often generated during legalization.
// e.g. v4i32 <0,u,1,u> -> (v2i64 any_vector_extend_in_reg(v4i32 src)) // e.g. v4i32 <0,u,1,u> -> (v2i64 any_vector_extend_in_reg(v4i32 src))
// TODO Add support for ZERO_EXTEND_VECTOR_INREG when we have a test case. // TODO Add support for ZERO_EXTEND_VECTOR_INREG when we have a test case.
static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN, static SDValue combineShuffleToVectorExtend(ShuffleVectorSDNode *SVN,
▲ Show 20 Lines • Show All 2,761 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/arm64-vshuffle.ll

; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s
; CHECK: test1 ; CHECK-LABEL: test1
probinsonUnsubmitted
Not Done
ReplyInline Actions

I think FileCheck is case-sensitive with regard to suffixes? So should be CHECK-LABEL. Willing to be proven wrong but that was my impression.

probinson: I think FileCheck is case-sensitive with regard to suffixes? So should be CHECK-LABEL. Willing…
; CHECK: movi.16b v[[REG0:[0-9]+]], #0 ; CHECK: movi.16b v[[REG0:[0-9]+]], #0
define <8 x i1> @test1() { define <8 x i1> @test1() {
entry: entry:
%Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6, %Shuff = shufflevector <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
i1 7>, i1 7>,
<8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6, <8 x i1> <i1 0, i1 1, i1 2, i1 3, i1 4, i1 5, i1 6,
i1 7>, i1 7>,
<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10,
i32 12, i32 14, i32 0> i32 12, i32 14, i32 0>
ret <8 x i1> %Shuff ret <8 x i1> %Shuff
} }
; CHECK: lCPI1_0: ; CHECK-LABEL: lCPI1_0:
; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .space 1
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .space 1
; CHECK: .byte 1 ; 0x1 ; CHECK: .byte 1 ; 0x1
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: test2 ; CHECK-LABEL: test2
; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_0@PAGE ; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_0@PAGE
; CHECK: ldr d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF] ; CHECK: ldr d[[REG1:[0-9]+]], [x[[REG2]], lCPI1_0@PAGEOFF]
define <8 x i1>@test2() { define <8 x i1>@test2() {
bb: bb:
%Shuff = shufflevector <8 x i1> zeroinitializer, %Shuff = shufflevector <8 x i1> zeroinitializer,
<8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
<8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14, <8 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
i32 0> i32 0>
ret <8 x i1> %Shuff ret <8 x i1> %Shuff
} }
; CHECK: test3 ; CHECK-LABEL: test3
; CHECK: movi.4s v{{[0-9]+}}, #1 ; CHECK: movi.4s v{{[0-9]+}}, #1
define <16 x i1> @test3(i1* %ptr, i32 %v) { define <16 x i1> @test3(i1* %ptr, i32 %v) {
bb: bb:
%Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef, %Shuff = shufflevector <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, <16 x i1> undef,
<16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14, <16 x i32> <i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 14,
i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12, i32 0, i32 2, i32 undef, i32 6, i32 undef, i32 10, i32 12,
i32 14, i32 0> i32 14, i32 0>
ret <16 x i1> %Shuff ret <16 x i1> %Shuff
} }
; CHECK: lCPI3_0: ; CHECK-LABEL: lCPI3_0:
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 1 ; 0x1 ; CHECK: .byte 1 ; 0x1
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0
; CHECK: _test4: ; CHECK-LABEL: _test4:
; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0@PAGE ; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0@PAGE
; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF] ; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF]
define <16 x i1> @test4(i1* %ptr, i32 %v) { define <16 x i1> @test4(i1* %ptr, i32 %v) {
bb: bb:
%Shuff = shufflevector <16 x i1> zeroinitializer, %Shuff = shufflevector <16 x i1> zeroinitializer,
<16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1, <16 x i1> <i1 0, i1 1, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0, i1 0, i1 1,
i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>, i1 1, i1 0, i1 0, i1 1, i1 0, i1 0>,
<16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0, <16 x i32> <i32 2, i32 1, i32 6, i32 18, i32 10, i32 12, i32 14, i32 0,
i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0> i32 2, i32 31, i32 6, i32 30, i32 10, i32 12, i32 14, i32 0>
ret <16 x i1> %Shuff ret <16 x i1> %Shuff
} }

llvm/test/CodeGen/PowerPC/vec-itofp.ll

Show First 20 Lines • Show All 301 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: stest8: ; CHECK-BE-LABEL: stest8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI3_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI3_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16 %0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
%1 = sitofp <8 x i16> %0 to <8 x double> %1 = sitofp <8 x i16> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %Sink, align 16 store <8 x double> %1, <8 x double>* %Sink, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: stest4: ; CHECK-BE-LABEL: stest4:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_0@toc@l
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI4_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI4_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16 %0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
%1 = sitofp <4 x i16> %0 to <4 x double> %1 = sitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %Sink, align 16 store <4 x double> %1, <4 x double>* %Sink, align 16
ret void ret void
} }
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

Show First 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <4 x i16> %0 = bitcast i64 %a.coerce to <4 x i16>
%1 = sitofp <4 x i16> %0 to <4 x double> %1 = sitofp <4 x i16> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
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; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: vextsh2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3 ; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <8 x i16> %a to <8 x double> %0 = sitofp <8 x i16> %a to <8 x double>
store <8 x double> %0, <8 x double>* %agg.result, align 64 store <8 x double> %0, <8 x double>* %agg.result, align 64
ret void ret void
} }
define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 { define void @test16elt_signed(<16 x double>* noalias nocapture sret(<16 x double>) %agg.result, <16 x i16>* nocapture readonly) local_unnamed_addr #3 {
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs7, v2 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs6, 96(r3) ; CHECK-P9-NEXT: stxv vs6, 96(r3)
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v2, 0(r4)
; CHECK-BE-NEXT: lxv v1, 16(r4)
; CHECK-BE-NEXT: xxlxor v5, v5, v5
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: lxv v3, 0(r5)
; CHECK-BE-NEXT: lxv v2, 0(r5)
; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_1@toc@l
; CHECK-BE-NEXT: lxv v3, 0(r5) ; CHECK-BE-NEXT: lxv v5, 0(r5)
; CHECK-BE-NEXT: vperm v0, v5, v4, v2 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: vperm v2, v5, v1, v2 ; CHECK-BE-NEXT: vperm v4, v2, v2, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vextsh2d v0, v0 ; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs2, v2 ; CHECK-BE-NEXT: lxv v0, 0(r5)
; CHECK-BE-NEXT: vperm v2, v5, v1, v3 ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: xvcvsxddp vs0, v0 ; CHECK-BE-NEXT: xvcvsxddp vs0, v4
; CHECK-BE-NEXT: vperm v0, v5, v4, v3 ; CHECK-BE-NEXT: vperm v4, v2, v2, v5
; CHECK-BE-NEXT: addi r5, r5, .LCPI7_3@toc@l
; CHECK-BE-NEXT: lxv v1, 0(r5)
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs1, v4
; CHECK-BE-NEXT: vperm v4, v2, v2, v0
; CHECK-BE-NEXT: vperm v2, v2, v2, v1
; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: xvcvsxddp vs2, v4
; CHECK-BE-NEXT: lxv v4, 16(r4)
; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: vextsh2d v0, v0
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: vperm v2, v4, v4, v3
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: xvcvsxddp vs1, v0 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: xvcvsxddp vs4, v2
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: vperm v2, v4, v4, v5
; CHECK-BE-NEXT: vperm v3, v4, v4, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: vperm v2, v1, v1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs5, v2
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: vperm v2, v4, v4, v0
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: vextsh2d v3, v3
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: xvcvsxddp vs6, v2 ; CHECK-BE-NEXT: xvcvsxddp vs6, v2
; CHECK-BE-NEXT: vperm v4, v4, v4, v3 ; CHECK-BE-NEXT: vperm v2, v4, v4, v1
; CHECK-BE-NEXT: vperm v2, v1, v1, v3 ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: stxv vs6, 64(r3)
; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: vextsh2d v4, v4
; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: vextsh2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs5, v4
; CHECK-BE-NEXT: xvcvsxddp vs7, v2 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 96(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x i16>, <16 x i16>* %0, align 32 %a = load <16 x i16>, <16 x i16>* %0, align 32
%1 = sitofp <16 x i16> %a to <16 x double> %1 = sitofp <16 x i16> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

Show First 20 Lines • Show All 398 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxwsp vs1, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs1, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = sitofp <8 x i8> %0 to <8 x float> %1 = sitofp <8 x i8> %0 to <8 x float>
store <8 x float> %1, <8 x float>* %agg.result, align 32 store <8 x float> %1, <8 x float>* %agg.result, align 32
ret void ret void
} }
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; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: vextsb2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp vs3, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs0, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs1, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs1, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vextsb2w v3, v3 ; CHECK-BE-NEXT: vextsb2w v3, v3
; CHECK-BE-NEXT: xvcvsxwsp vs2, v3 ; CHECK-BE-NEXT: xvcvsxwsp vs2, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: vextsb2w v2, v2
; CHECK-BE-NEXT: xvcvsxwsp vs3, v2 ; CHECK-BE-NEXT: xvcvsxwsp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <16 x i8> %a to <16 x float> %0 = sitofp <16 x i8> %a to <16 x float>
store <16 x float> %0, <16 x float>* %agg.result, align 64 store <16 x float> %0, <16 x float>* %agg.result, align 64
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

Show First 20 Lines • Show All 486 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs1, v2 ; CHECK-P9-NEXT: xvcvsxddp vs1, v2
; CHECK-P9-NEXT: stxv vs1, 16(r3) ; CHECK-P9-NEXT: stxv vs1, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrwz v2, r4 ; CHECK-BE-NEXT: mtvsrwz v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs1, v2 ; CHECK-BE-NEXT: xvcvsxddp vs1, v2
; CHECK-BE-NEXT: stxv vs1, 0(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <4 x i8> %0 = bitcast i32 %a.coerce to <4 x i8>
%1 = sitofp <4 x i8> %0 to <4 x double> %1 = sitofp <4 x i8> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: xvcvsxddp vs3, v2 ; CHECK-P9-NEXT: xvcvsxddp vs3, v2
; CHECK-P9-NEXT: stxv vs3, 48(r3) ; CHECK-P9-NEXT: stxv vs3, 48(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-BE-NEXT: xxlxor v4, v4, v4
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v3 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-BE-NEXT: vperm v3, v4, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v3 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI6_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI6_3@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v3 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 0(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs3, v2 ; CHECK-BE-NEXT: xvcvsxddp vs3, v2
; CHECK-BE-NEXT: stxv vs3, 32(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <8 x i8> %0 = bitcast i64 %a.coerce to <8 x i8>
%1 = sitofp <8 x i8> %0 to <8 x double> %1 = sitofp <8 x i8> %0 to <8 x double>
store <8 x double> %1, <8 x double>* %agg.result, align 64 store <8 x double> %1, <8 x double>* %agg.result, align 64
ret void ret void
} }
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; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: vextsb2d v2, v2
; CHECK-P9-NEXT: xvcvsxddp vs7, v2 ; CHECK-P9-NEXT: xvcvsxddp vs7, v2
; CHECK-P9-NEXT: stxv vs7, 112(r3) ; CHECK-P9-NEXT: stxv vs7, 112(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha
; CHECK-BE-NEXT: xxlxor v3, v3, v3
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_1@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_1@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs0, v4 ; CHECK-BE-NEXT: xvcvsxddp vs0, v3
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_2@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_2@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 0(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs1, v4 ; CHECK-BE-NEXT: xvcvsxddp vs1, v3
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_3@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_3@toc@l
; CHECK-BE-NEXT: vperm v4, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs1, 48(r3) ; CHECK-BE-NEXT: stxv vs1, 16(r3)
; CHECK-BE-NEXT: vextsb2d v4, v4 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs2, v4 ; CHECK-BE-NEXT: xvcvsxddp vs2, v3
; CHECK-BE-NEXT: lxv v4, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_4@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_4@toc@l
; CHECK-BE-NEXT: vperm v3, v3, v2, v4 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs2, 80(r3) ; CHECK-BE-NEXT: stxv vs2, 32(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs3, v3 ; CHECK-BE-NEXT: xvcvsxddp vs3, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_5@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_5@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs3, 112(r3) ; CHECK-BE-NEXT: stxv vs3, 48(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs4, v3 ; CHECK-BE-NEXT: xvcvsxddp vs4, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_6@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_6@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 64(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs5, v3 ; CHECK-BE-NEXT: xvcvsxddp vs5, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha ; CHECK-BE-NEXT: addis r4, r2, .LCPI7_7@toc@ha
; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l ; CHECK-BE-NEXT: addi r4, r4, .LCPI7_7@toc@l
; CHECK-BE-NEXT: vperm v3, v2, v2, v3 ; CHECK-BE-NEXT: vperm v3, v2, v2, v3
; CHECK-BE-NEXT: stxv vs5, 32(r3) ; CHECK-BE-NEXT: stxv vs5, 80(r3)
; CHECK-BE-NEXT: vextsb2d v3, v3 ; CHECK-BE-NEXT: vextsb2d v3, v3
; CHECK-BE-NEXT: xvcvsxddp vs6, v3 ; CHECK-BE-NEXT: xvcvsxddp vs6, v3
; CHECK-BE-NEXT: lxv v3, 0(r4) ; CHECK-BE-NEXT: lxv v3, 0(r4)
; CHECK-BE-NEXT: vperm v2, v2, v2, v3 ; CHECK-BE-NEXT: vperm v2, v2, v2, v3
; CHECK-BE-NEXT: stxv vs6, 64(r3) ; CHECK-BE-NEXT: stxv vs6, 96(r3)
; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: vextsb2d v2, v2
; CHECK-BE-NEXT: xvcvsxddp vs7, v2 ; CHECK-BE-NEXT: xvcvsxddp vs7, v2
; CHECK-BE-NEXT: stxv vs7, 96(r3) ; CHECK-BE-NEXT: stxv vs7, 112(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = sitofp <16 x i8> %a to <16 x double> %0 = sitofp <16 x i8> %a to <16 x double>
store <16 x double> %0, <16 x double>* %agg.result, align 128 store <16 x double> %0, <16 x double>* %agg.result, align 128
ret void ret void
} }

llvm/test/CodeGen/Thumb2/mve-vst3.ll

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ret void ret void
} }
; i8 ; i8
define void @vst3_v2i8(<2 x i8> *%src, <6 x i8> *%dst) { define void @vst3_v2i8(<2 x i8> *%src, <6 x i8> *%dst) {
; CHECK-LABEL: vst3_v2i8: ; CHECK-LABEL: vst3_v2i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r7, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .pad #16 ; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16 ; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: ldrb r2, [r0] ; CHECK-NEXT: ldrb r2, [r0]
; CHECK-NEXT: movs r6, #0 ; CHECK-NEXT: mov r4, sp
; CHECK-NEXT: ldrb r3, [r0, #1] ; CHECK-NEXT: ldrb r3, [r0, #1]
; CHECK-NEXT: ldrb.w r12, [r0, #2] ; CHECK-NEXT: ldrb.w r12, [r0, #2]
; CHECK-NEXT: vmov q0[2], q0[0], r2, r3 ; CHECK-NEXT: vmov q0[2], q0[0], r2, r3
; CHECK-NEXT: ldrb.w lr, [r0, #3] ; CHECK-NEXT: ldrb.w lr, [r0, #3]
; CHECK-NEXT: vmov r4, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: ldrb r5, [r0, #5] ; CHECK-NEXT: ldrb r5, [r0, #5]
; CHECK-NEXT: vmov.16 q0[0], r4 ; CHECK-NEXT: vmov.16 q0[0], r2
; CHECK-NEXT: ldrb r0, [r0, #4] ; CHECK-NEXT: ldrb r0, [r0, #4]
; CHECK-NEXT: vmov.16 q0[1], r12 ; CHECK-NEXT: vmov.16 q0[1], r12
; CHECK-NEXT: mov r2, sp
; CHECK-NEXT: vmov.16 q0[2], r0 ; CHECK-NEXT: vmov.16 q0[2], r0
; CHECK-NEXT: add r0, sp, #8 ; CHECK-NEXT: add r0, sp, #8
; CHECK-NEXT: vmov.16 q0[3], r3 ; CHECK-NEXT: vmov.16 q0[3], r3
; CHECK-NEXT: vmov.16 q0[4], lr ; CHECK-NEXT: vmov.16 q0[4], lr
; CHECK-NEXT: vmov.16 q0[5], r5 ; CHECK-NEXT: vmov.16 q0[5], r5
; CHECK-NEXT: vmov.16 q0[6], r6 ; CHECK-NEXT: vstrb.16 q0, [r4]
; CHECK-NEXT: vmov.16 q0[7], r6
; CHECK-NEXT: vstrb.16 q0, [r2]
; CHECK-NEXT: vstrb.16 q0, [r0] ; CHECK-NEXT: vstrb.16 q0, [r0]
; CHECK-NEXT: vldrh.u32 q0, [r0] ; CHECK-NEXT: vldrh.u32 q0, [r0]
; CHECK-NEXT: ldr r2, [sp] ; CHECK-NEXT: ldr r2, [sp]
; CHECK-NEXT: str r2, [r1] ; CHECK-NEXT: str r2, [r1]
; CHECK-NEXT: vmov r0, s2 ; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: strh r0, [r1, #4] ; CHECK-NEXT: strh r0, [r1, #4]
; CHECK-NEXT: add sp, #16 ; CHECK-NEXT: add sp, #16
; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: pop {r4, r5, r7, pc}
entry: entry:
%s1 = getelementptr <2 x i8>, <2 x i8>* %src, i32 0 %s1 = getelementptr <2 x i8>, <2 x i8>* %src, i32 0
%l1 = load <2 x i8>, <2 x i8>* %s1, align 4 %l1 = load <2 x i8>, <2 x i8>* %s1, align 4
%s2 = getelementptr <2 x i8>, <2 x i8>* %src, i32 1 %s2 = getelementptr <2 x i8>, <2 x i8>* %src, i32 1
%l2 = load <2 x i8>, <2 x i8>* %s2, align 4 %l2 = load <2 x i8>, <2 x i8>* %s2, align 4
%s3 = getelementptr <2 x i8>, <2 x i8>* %src, i32 2 %s3 = getelementptr <2 x i8>, <2 x i8>* %src, i32 2
%l3 = load <2 x i8>, <2 x i8>* %s3, align 4 %l3 = load <2 x i8>, <2 x i8>* %s3, align 4
%t1 = shufflevector <2 x i8> %l1, <2 x i8> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %t1 = shufflevector <2 x i8> %l1, <2 x i8> %l2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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