[AArch64] Try to convert signed to unsigned pred to re-use zext.

[fhahn]

Summary

Building on D120481, try to convert a signed predicate to unsigned to
re-use existing zext.

The following conversion is supported: %a >s -1 -> zext(%a) <u 128.
https://alive2.llvm.org/ce/z/RVnadn

Depends on D120481.

[fhahn]

rebase on top of additional tests

[dmgreen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

17095–17096

Should this be overriding Op1ExtV?

llvm/test/CodeGen/AArch64/vselect-ext.ll

169–183

This doesn't seem to be correct.

[fhahn]

This is no longer relevant.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

if (Op->getOperand(0).getValueType() != MVT::v16i8)
     return SDValue();
 
   if (any_of(Op->uses(), [](const SDNode *N) {
         return N->getOpcode() != ISD::VSELECT ||
                N->getValueType(0) != MVT::v16i32;
       }))
     return SDValue();
 
-  APInt V;
-  if (!ISD::isConstantSplatVector(Op->getOperand(1).getNode(), V))
+  APInt SplatVal;
+  if (!ISD::isConstantSplatVector(Op->getOperand(1).getNode(), SplatVal))
     return SDValue();
 
   SDLoc DL(Op);
   SDValue Op0ExtV;
   SDValue Op1ExtV;
   ISD::CondCode CC = cast<CondCodeSDNode>(Op->getOperand(2))->get();
   // Check if the first operand of the SET_CC is already extended. If it is,
   // split the SET_CC and re-use the extended version of the operand.
   SDNode *Op0SExt = DAG.getNodeIfExists(
       ISD::SIGN_EXTEND, DAG.getVTList(MVT::v16i32), Op->getOperand(0));
   SDNode *Op0ZExt = DAG.getNodeIfExists(
       ISD::ZERO_EXTEND, DAG.getVTList(MVT::v16i32), Op->getOperand(0));
   if (Op0SExt && isSignedIntSetCC(CC)) {
     Op0ExtV = SDValue(Op0SExt, 0);
     Op1ExtV = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
-  } else if (Op0ZExt && isUnsignedIntSetCC(CC)) {
+  } else if (Op0ZExt) {
     Op0ExtV = SDValue(Op0ZExt, 0);
-    Op1ExtV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
-  } else
+    // Try to convert signed to unsigned predicate, so zext can be used: %a >s
+    // -1 -> zext(%a) <u 128.
+    if (CC == ISD::SETGT && SplatVal.isAllOnes()) {
+      CC = ISD::SETULT;
+      Op1ExtV = DAG.getSplatBuildVector(MVT::v16i32, DL,
+                                        DAG.getConstant(128, DL, MVT::i32));
+    }
+    if (isUnsignedIntSetCC(CC))
+      Op1ExtV =
+          DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v16i32, Op->getOperand(1));
+  }
+
+  if (!Op0ExtV || !Op1ExtV)
     return SDValue();
 
   return DAG.getNode(ISD::SETCC, DL, MVT::v16i1, Op0ExtV, Op1ExtV,
-                     Op->getOperand(2));
+                     DAG.getCondCode(CC));
 }
 
 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
   assert(N->getOpcode() == ISD::SETCC && "Unexpected opcode!");
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
 

llvm/test/CodeGen/AArch64/vselect-ext.ll

entry:
   %cmp = icmp ugt <16 x i8> %a, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>
   %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
   ret <16 x i32> %sel
 }
 
 define <16 x i32> @same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred(<16 x i8> %a) {
 ; CHECK-LABEL: same_zext_used_in_cmp_signed_pred_and_select_can_convert_to_unsigned_pred:
 ; CHECK:       ; %bb.0: ; %entry
-; CHECK-NEXT:    movi.2d v1, #0xffffffffffffffff
-; CHECK-NEXT:    ushll.8h v2, v0, #0
-; CHECK-NEXT:    ushll2.8h v3, v0, #0
-; CHECK-NEXT:    ushll.4s v4, v2, #0
-; CHECK-NEXT:    cmgt.16b v0, v0, v1
-; CHECK-NEXT:    ushll.4s v5, v3, #0
-; CHECK-NEXT:    ushll2.4s v1, v3, #0
-; CHECK-NEXT:    sshll.8h v3, v0, #0
-; CHECK-NEXT:    sshll2.8h v0, v0, #0
-; CHECK-NEXT:    ushll2.4s v2, v2, #0
-; CHECK-NEXT:    sshll.4s v6, v3, #0
-; CHECK-NEXT:    sshll.4s v7, v0, #0
-; CHECK-NEXT:    sshll2.4s v0, v0, #0
-; CHECK-NEXT:    sshll2.4s v16, v3, #0
-; CHECK-NEXT:    and.16b v3, v1, v0
-; CHECK-NEXT:    and.16b v1, v2, v16
-; CHECK-NEXT:    and.16b v2, v5, v7
-; CHECK-NEXT:    and.16b v0, v4, v6
+; CHECK-NEXT:    movi.2d v1, #0x0000ff000000ff
+; CHECK-NEXT:    ushll2.8h v2, v0, #0
+; CHECK-NEXT:    ushll.8h v0, v0, #0
+; CHECK-NEXT:    ushll2.4s v3, v2, #0
+; CHECK-NEXT:    ushll2.4s v4, v0, #0
+; CHECK-NEXT:    ushll.4s v0, v0, #0
+; CHECK-NEXT:    ushll.4s v2, v2, #0
+; CHECK-NEXT:    cmhi.4s v5, v1, v0
+; CHECK-NEXT:    cmhi.4s v6, v1, v2
+; CHECK-NEXT:    cmhi.4s v7, v1, v3
+; CHECK-NEXT:    cmhi.4s v1, v1, v4
+; CHECK-NEXT:    and.16b v3, v3, v7
+; CHECK-NEXT:    and.16b v1, v4, v1
+; CHECK-NEXT:    and.16b v2, v2, v6
+; CHECK-NEXT:    and.16b v0, v0, v5
 ; CHECK-NEXT:    ret
 entry:
   %ext = zext <16 x i8> %a to <16 x i32>
   %cmp = icmp sgt <16 x i8> %a,  <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
   %sel = select <16 x i1> %cmp, <16 x i32> %ext, <16 x i32> zeroinitializer
   ret <16 x i32> %sel
 }