[RISCV] Teach VSETVLInsert to optimize vsetvli for ScalarMoveInstr

[Chenbing.Zheng]

Summary

VSETVLI from ScalarMove don't care different LMUL or non-zero AVL.
It provides an opportunity for our optimization.

In D116307, it shared VSETVLI of ScalarMove with previous VSETVLI as far as possible.

In this patch, we try to shared VSETVLI of single ScalarMoveInstr with next VSETVLI as far as possible。

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

1056

The scalar move instruction may share a VSETVLI with one or some other instruction.

1092

As the former comment, the scalar move instruction may share a VSETVLI with one or some other instructions, so in this situation, we could not only think about the scalar move instruction, other instructions may care about the LMUL.

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

1092

Yer, if scalar move instruction share a VSETVLI with others, we do not optimize this case. Because as you said, that would cause the error. ScalarMoveVSETVLI will be nullptr in this case.

[Chenbing.Zheng]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

1056

In the case you said，the insertVSETVLI function will not be called. So ScalarMoveVSETVLI only be set if VSETVLI come from single ScalarMoveInstr.

[Chenbing.Zheng]

Ping

[Chenbing.Zheng]

Ping

[Chenbing.Zheng]

ping

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
   // to insert a VSETVLI.
   return false;
 }
 
 void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
   VSETVLIInfo CurInfo;
   // Only be set if current VSETVLIInfo is from an explicit VSET(I)VLI.
   MachineInstr *PrevVSETVLIMI = nullptr;
+  // Only be set if VSET(I)VLI is from ScalarMove.
+  MachineInstr *ScalarMoveVSETVLI = nullptr;
 
   for (MachineInstr &MI : MBB) {
     // If this is an explicit VSETVLI or VSETIVLI, update our state.
     if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
         MI.getOpcode() == RISCV::PseudoVSETVLIX0 ||
         MI.getOpcode() == RISCV::PseudoVSETIVLI) {
       // Conservatively, mark the VL and VTYPE as live.
       assert(MI.getOperand(3).getReg() == RISCV::VL &&
if (RISCVII::hasSEWOp(TSFlags)) {
       if (!CurInfo.isValid()) {
         // We haven't found any vector instructions or VL/VTYPE changes yet,
         // use the predecessor information.
         assert(BlockInfo[MBB.getNumber()].Pred.isValid() &&
                "Expected a valid predecessor state.");
         if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred) &&
             needVSETVLIPHI(NewInfo, MBB)) {
           insertVSETVLI(MBB, MI, NewInfo, BlockInfo[MBB.getNumber()].Pred);
+          if (isScalarMoveInstr(MI))
+            ScalarMoveVSETVLI = MI.getPrevNode();
           CurInfo = NewInfo;
         }
       } else {
         // If this instruction isn't compatible with the previous VL/VTYPE
         // we need to insert a VSETVLI.
         // If this is a unit-stride or strided load/store, we may be able to use
         // the EMUL=(EEW/SEW)*LMUL relationship to avoid changing vtype.
         // NOTE: We can't use predecessor information for the store. We must
if (RISCVII::hasSEWOp(TSFlags)) {
             if (isScalarMoveInstr(MI) &&
                 ((CurInfo.hasNonZeroAVL() && NewInfo.hasNonZeroAVL()) ||
                  (CurInfo.hasZeroAVL() && NewInfo.hasZeroAVL())) &&
                 NewInfo.hasSameVLMAX(CurInfo)) {
               PrevVSETVLIMI->getOperand(2).setImm(NewInfo.encodeVTYPE());
               NeedInsertVSETVLI = false;
             }
           }
-          if (NeedInsertVSETVLI)
+          if (ScalarMoveVSETVLI) {
+            if (NewInfo.hasAVLImm() &&
+                ((NewInfo.hasNonZeroAVL() && CurInfo.hasNonZeroAVL()) ||
+                 (CurInfo.hasZeroAVL() && CurInfo.hasZeroAVL())) &&
+                NewInfo.hasSameSEW(CurInfo) && NewInfo.hasSamePolicy(CurInfo)) {
+              // Because VSETVLI from ScalarMove don't care LMUL and non-zero
+              // AVL, so we can use new VSETVLI to instead old VSETVLI.
+              insertVSETVLI(MBB, *ScalarMoveVSETVLI, NewInfo, CurInfo);
+              ScalarMoveVSETVLI->removeFromParent();
+              NeedInsertVSETVLI = false;
+            }
+          }
+          if (NeedInsertVSETVLI) {
             insertVSETVLI(MBB, MI, NewInfo, CurInfo);
+            if (isScalarMoveInstr(MI))
+              ScalarMoveVSETVLI = MI.getPrevNode();
+            else
+              ScalarMoveVSETVLI = nullptr;
+          }
+
           CurInfo = NewInfo;
         }
       }
       PrevVSETVLIMI = nullptr;
     }
 
     // If this is something updates VL/VTYPE that we don't know about, set
     // the state to unknown.
     if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) ||
         MI.modifiesRegister(RISCV::VTYPE)) {
       CurInfo = VSETVLIInfo::getUnknown();
       PrevVSETVLIMI = nullptr;
+      ScalarMoveVSETVLI = nullptr;
     }
 
     // If we reach the end of the block and our current info doesn't match the
     // expected info, insert a vsetvli to correct.
     if (MI.isTerminator()) {
       const VSETVLIInfo &ExitInfo = BlockInfo[MBB.getNumber()].Exit;
       if (CurInfo.isValid() && ExitInfo.isValid() && !ExitInfo.isUnknown() &&
           CurInfo != ExitInfo) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

 }
 
 define void @buildvec_seq_v9i8(<9 x i8>* %x) {
 ; RV32-LABEL: buildvec_seq_v9i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    li a1, 3
 ; RV32-NEXT:    sb a1, 8(a0)
 ; RV32-NEXT:    li a1, 73
-; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vmv.v.i v9, 2
 ; RV32-NEXT:    li a1, 36
 ; RV32-NEXT:    vmv.s.x v8, a1
 ; RV32-NEXT:    vmerge.vim v9, v9, 1, v0
 ; RV32-NEXT:    vmv1r.v v0, v8
 ; RV32-NEXT:    vmerge.vim v8, v9, 3, v0
 ; RV32-NEXT:    vse8.v v8, (a0)
 ; RV32-NEXT:    ret

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
   ret <8 x i8> %shuff
 }
 
 define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
 ; CHECK-LABEL: splat_ve2_we0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 66
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vi v10, v8, 2
 ; CHECK-NEXT:    vrgather.vi v10, v9, 0, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
   ret <8 x i8> %shuff
 }
 
; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
   ret <8 x i8> %shuff
 }
 
 define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
 ; CHECK-LABEL: splat_ve2_we0_ins_i0we4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 67
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vi v10, v8, 2
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v8, 4
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vrgather.vv v10, v9, v8, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 4
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vmv.s.x v10, a0
 ; CHECK-NEXT:    vmv.v.i v11, 0
 ; CHECK-NEXT:    vsetivli zero, 3, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v11, v10, 2
 ; CHECK-NEXT:    li a0, 70
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vi v10, v8, 2
 ; CHECK-NEXT:    vrgather.vv v10, v9, v11, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v10
 ; CHECK-NEXT:    ret
   %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
   ret <8 x i8> %shuff
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vmv.v.i v10, 3
 ; CHECK-NEXT:    vmerge.vim v10, v10, 2, v0
 ; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, mu
 ; CHECK-NEXT:    vslideup.vi v10, v9, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vmv.v.i v11, 0
 ; CHECK-NEXT:    lui a1, 1048568
-; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
-; CHECK-NEXT:    vmv.v.i v12, 0
-; CHECK-NEXT:    vmv.s.x v12, a1
 ; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, mu
+; CHECK-NEXT:    vmv1r.v v12, v11
+; CHECK-NEXT:    vmv.s.x v12, a1
 ; CHECK-NEXT:    vslideup.vi v11, v9, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    lui a1, %hi(.LCPI53_0)
 ; CHECK-NEXT:    addi a1, a1, %lo(.LCPI53_0)
 ; CHECK-NEXT:    vle16.v v9, (a1)
 ; CHECK-NEXT:    vsrl.vv v11, v8, v11
 ; CHECK-NEXT:    vmulhu.vv v9, v11, v9
 ; CHECK-NEXT:    vsub.vv v8, v8, v9

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

 ; RV64-ELEN8-NEXT:    ret
   ret <4 x i1> <i1 0, i1 1, i1 1, i1 0>
 }
 
 define <4 x i1> @buildvec_mask_nonconst_v4i1(i1 %x, i1 %y) {
 ; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a2, 3
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vmv.v.x v8, a1
 ; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; CHECK-NEXT:    vand.vi v8, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
 ;
 ; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV32-ELEN32:       # %bb.0:
 ; RV32-ELEN32-NEXT:    li a2, 3
-; RV32-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN32-NEXT:    vand.vi v8, v8, 1
 ; RV32-ELEN32-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-ELEN32-NEXT:    ret
 ;
 ; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV64-ELEN32:       # %bb.0:
 ; RV64-ELEN32-NEXT:    li a2, 3
-; RV64-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN32-NEXT:    vand.vi v8, v8, 1
 ; RV64-ELEN32-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-ELEN32-NEXT:    ret
 ;
 ; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV32-ELEN16:       # %bb.0:
 ; RV32-ELEN16-NEXT:    li a2, 3
-; RV32-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vsetivli zero, 4, e8, mf2, ta, mu
+; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN16-NEXT:    vand.vi v8, v8, 1
 ; RV32-ELEN16-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-ELEN16-NEXT:    ret
 ;
 ; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV64-ELEN16:       # %bb.0:
 ; RV64-ELEN16-NEXT:    li a2, 3
-; RV64-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vsetivli zero, 4, e8, mf2, ta, mu
+; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN16-NEXT:    vand.vi v8, v8, 1
 ; RV64-ELEN16-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-ELEN16-NEXT:    ret
 ;
 ; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV32-ELEN8:       # %bb.0:
 ; RV32-ELEN8-NEXT:    li a2, 3
-; RV32-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vsetivli zero, 4, e8, m1, ta, mu
+; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN8-NEXT:    vand.vi v8, v8, 1
 ; RV32-ELEN8-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-ELEN8-NEXT:    ret
 ;
 ; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV64-ELEN8:       # %bb.0:
 ; RV64-ELEN8-NEXT:    li a2, 3
-; RV64-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vsetivli zero, 4, e8, m1, ta, mu
+; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN8-NEXT:    vand.vi v8, v8, 1
 ; RV64-ELEN8-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-ELEN8-NEXT:    ret
   %1 = insertelement <4 x i1> poison, i1 %x, i32 0
   %2 = insertelement <4 x i1> %1,  i1 %x, i32 1
   %3 = insertelement <4 x i1> %2,  i1 %y, i32 2

 ; RV64-ELEN8-NEXT:    ret
   ret <8 x i1> <i1 0, i1 1, i1 1, i1 0, i1 1, i1 1, i1 0, i1 1>
 }
 
 define <8 x i1> @buildvec_mask_nonconst_v8i1(i1 %x, i1 %y) {
 ; CHECK-LABEL: buildvec_mask_nonconst_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a2, 19
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vmv.v.x v8, a1
 ; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; CHECK-NEXT:    vand.vi v8, v8, 1
 ; CHECK-NEXT:    vmsne.vi v0, v8, 0
 ; CHECK-NEXT:    ret
 ;
 ; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV32-ELEN32:       # %bb.0:
 ; RV32-ELEN32-NEXT:    li a2, 19
-; RV32-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN32-NEXT:    vand.vi v8, v8, 1
 ; RV32-ELEN32-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-ELEN32-NEXT:    ret
 ;
 ; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV64-ELEN32:       # %bb.0:
 ; RV64-ELEN32-NEXT:    li a2, 19
-; RV64-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN32-NEXT:    vand.vi v8, v8, 1
 ; RV64-ELEN32-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-ELEN32-NEXT:    ret
 ;
 ; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV32-ELEN16:       # %bb.0:
 ; RV32-ELEN16-NEXT:    li a2, 19
-; RV32-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN16-NEXT:    vand.vi v8, v8, 1
 ; RV32-ELEN16-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-ELEN16-NEXT:    ret
 ;
 ; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV64-ELEN16:       # %bb.0:
 ; RV64-ELEN16-NEXT:    li a2, 19
-; RV64-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN16-NEXT:    vand.vi v8, v8, 1
 ; RV64-ELEN16-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-ELEN16-NEXT:    ret
 ;
 ; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV32-ELEN8:       # %bb.0:
 ; RV32-ELEN8-NEXT:    li a2, 19
-; RV32-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vsetivli zero, 8, e8, m1, ta, mu
+; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN8-NEXT:    vand.vi v8, v8, 1
 ; RV32-ELEN8-NEXT:    vmsne.vi v0, v8, 0
 ; RV32-ELEN8-NEXT:    ret
 ;
 ; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV64-ELEN8:       # %bb.0:
 ; RV64-ELEN8-NEXT:    li a2, 19
-; RV64-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vsetivli zero, 8, e8, m1, ta, mu
+; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN8-NEXT:    vand.vi v8, v8, 1
 ; RV64-ELEN8-NEXT:    vmsne.vi v0, v8, 0
 ; RV64-ELEN8-NEXT:    ret
   %1 = insertelement <8 x i1> poison, i1 %x, i32 0
   %2 = insertelement <8 x i1> %1,  i1 %x, i32 1
   %3 = insertelement <8 x i1> %2,  i1 %y, i32 2