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[SVE] Remove AArch64ISD::ADD_PRED and AArch64ISD::SUB_PRED.
ClosedPublic

Authored by paulwalker-arm on Feb 9 2022, 9:55 AM.

Details

Summary

These nodes provide an indirection that is not necessary because
SVE has unpredicated add/sub instructions and there's no downside
to using them for partial register operations. In fact, the test
changes show that unifying how fixed-length and scalable vector
add/sub are lowered enables better use of existing isel patterns.

Diff Detail

Event Timeline

paulwalker-arm created this revision.Feb 9 2022, 9:55 AM
paulwalker-arm requested review of this revision.Feb 9 2022, 9:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 9 2022, 9:55 AM

Updated CHECK line within srem_v16i16.

Matt added a subscriber: Matt.Feb 9 2022, 10:53 AM
sdesmalen accepted this revision.Feb 10 2022, 1:01 AM
sdesmalen added a subscriber: sdesmalen.

LGTM

This revision is now accepted and ready to land.Feb 10 2022, 1:01 AM
This revision was landed with ongoing or failed builds.Feb 10 2022, 9:24 AM
This revision was automatically updated to reflect the committed changes.