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Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines	- Support has been added for the following processors (``-mcpu`` identifiers in parentheses):
- RISC-V SiFive E20 (``sifive-e20``).		- RISC-V SiFive E20 (``sifive-e20``).
- RISC-V SiFive E21 (``sifive-e21``).		- RISC-V SiFive E21 (``sifive-e21``).
- RISC-V SiFive E24 (``sifive-e24``).		- RISC-V SiFive E24 (``sifive-e24``).
- RISC-V SiFive E34 (``sifive-e34``).		- RISC-V SiFive E34 (``sifive-e34``).
- RISC-V SiFive S21 (``sifive-s21``).		- RISC-V SiFive S21 (``sifive-s21``).
- RISC-V SiFive S51 (``sifive-s51``).		- RISC-V SiFive S51 (``sifive-s51``).
- RISC-V SiFive S54 (``sifive-s54``).		- RISC-V SiFive S54 (``sifive-s54``).
- RISC-V SiFive S76 (``sifive-s76``).		- RISC-V SiFive S76 (``sifive-s76``).
		- Arm Cortex-X1C (``cortex-x1c``)
		- Arm Cortex-X2 (``cortex-x2``)
		- Arm Cortex-A510 (``cortex-a510``)
		- Arm Cortex-A710 (``cortex-a710``)

- Support has been added for the following architectures (``-march`` identifiers in parentheses):		- Support has been added for the following architectures (``-march`` identifiers in parentheses):

- Armv9-A (``armv9-a``).		- Armv9-A (``armv9-a``).
- Armv9.1-A (``armv9.1-a``).		- Armv9.1-A (``armv9.1-a``).
- Armv9.2-A (``armv9.2-a``).		- Armv9.2-A (``armv9.2-a``).

Removed Compiler Flags		Removed Compiler Flags
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- The default DWARF version has increased from DWARFv4 to DWARFv5. You can opt		- The default DWARF version has increased from DWARFv4 to DWARFv5. You can opt
back in to the old behavior with ``-gdwarf-4`` or ``-fdebug-default-version=4``.		back in to the old behavior with ``-gdwarf-4`` or ``-fdebug-default-version=4``.
Some platforms (Darwin, Android, and SCE for instance) already opt out of this		Some platforms (Darwin, Android, and SCE for instance) already opt out of this
version bump as is suitable for the platform		version bump as is suitable for the platform

Arm and AArch64 Support in Clang		Arm and AArch64 Support in Clang
--------------------------------		--------------------------------

- Support has been added for the following processors (command-line identifiers in parentheses):
- Arm Cortex-A510 (``cortex-a510``)
- Arm Cortex-X2 (``cortex-x2``)
- Arm Cortex-A710 (``cortex-A710``)

- The -mtune flag is no longer ignored for AArch64. It is now possible to		- The -mtune flag is no longer ignored for AArch64. It is now possible to
tune code generation for a particular CPU with -mtune without setting any		tune code generation for a particular CPU with -mtune without setting any
architectural features. For example, compiling with		architectural features. For example, compiling with
"-mcpu=generic -mtune=cortex-a57" will not enable any Cortex-A57 specific		"-mcpu=generic -mtune=cortex-a57" will not enable any Cortex-A57 specific
architecture features, but will enable certain optimizations specific to		architecture features, but will enable certain optimizations specific to
Cortex-A57 CPUs and enable the use of a more accurate scheduling model.		Cortex-A57 CPUs and enable the use of a more accurate scheduling model.

- The --aarch64-none-elf target now uses the BareMetal driver rather than the		- The --aarch64-none-elf target now uses the BareMetal driver rather than the
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This is an archive of the discontinued LLVM Phabricator instance.

Add Cortex-X1C to Clang LLVM 14 release notesClosedPublic

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clang/docs/ReleaseNotes.rst

Add Cortex-X1C to Clang LLVM 14 release notes
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