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Differential D118218

[RISCV] Pre-commit test for D118216
ClosedPublic

Authored by Luhaocong on Jan 26 2022, 12:03 AM.

Details

Reviewers
asb
craig.topper
jrtc27
frasercrmck
Commits
rG2e57156fead3: [RISCV][test] Precommit a test of CSE within an unroll loop

Diff Detail

Event Timeline

Luhaocong created this revision.Jan 26 2022, 12:03 AM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 26 others. · View Herald TranscriptJan 26 2022, 12:03 AM
Luhaocong requested review of this revision.Jan 26 2022, 12:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 26 2022, 12:03 AM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD and 2 others. · View Herald Transcript
Luhaocong added a child revision: D118216: [RISCV] LUI used for address computation should not isAsCheapAsAMove.Jan 26 2022, 12:05 AM
Harbormaster completed remote builds in B145682: Diff 403152.Jan 26 2022, 11:32 PM
asb added a comment.Jan 28 2022, 6:41 AM

Although it's a bit repetitive, we typically try to run tests with both riscv32 and riscv64 if possible. It looks like this test case actually has identical assembly for RV32 and RV64, so you can just add a second CHECK line and leave them both using the default 'CHECK' prefix.

It would also be helpful to add a comment to the file explaining what it's trying to test. e.g. "This test case checks whether the address of an array is repeatedly rematerialised within a loop.".

Luhaocong updated this revision to Diff 406307.Feb 6 2022, 5:54 PM
Luhaocong added a reviewer: asb.
  1. Add test for rv64.
  2. Add description of test case.
Harbormaster completed remote builds in B147863: Diff 406307.Feb 6 2022, 6:41 PM
Luhaocong added reviewers: craig.topper, jrtc27.Feb 7 2022, 6:13 PM
frasercrmck accepted this revision.Feb 8 2022, 9:12 AM

LGTM otherwise.

llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
4

You don't need --check-prefix=CHECK at all, since it's the default.

This revision is now accepted and ready to land.Feb 8 2022, 9:12 AM
Luhaocong updated this revision to Diff 407101.Feb 9 2022, 2:36 AM

delete unnecessary CHECK

Harbormaster completed remote builds in B148440: Diff 407101.Feb 9 2022, 4:15 AM
This revision was landed with ongoing or failed builds.Feb 11 2022, 10:30 PM
Closed by commit rG2e57156fead3: [RISCV][test] Precommit a test of CSE within an unroll loop (authored by Luhaocong, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rG2e57156fead3: [RISCV][test] Precommit a test of CSE within an unroll loop.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
92 lines

Diff 407101

llvm/test/CodeGen/RISCV/unroll-loop-cse.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

You don't need --check-prefix=CHECK at all, since it's the default.

frasercrmck: You don't need `--check-prefix=CHECK` at all, since it's the default.
@x = global [6 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5], align 4
@check = global [6 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5], align 4
; This test case checks whether the base address of an array is repeatedly
; rematerialised within a unrolled loop.
define signext i32 @unroll_loop_cse() {
; CHECK-LABEL: unroll_loop_cse:
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(x)
; CHECK-NEXT: lw a3, %lo(x)(a1)
; CHECK-NEXT: lui a2, %hi(check)
; CHECK-NEXT: lw a4, %lo(check)(a2)
; CHECK-NEXT: li a0, 1
; CHECK-NEXT: bne a3, a4, .LBB0_6
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: addi a1, a1, %lo(x)
; CHECK-NEXT: lw a1, 4(a1)
; CHECK-NEXT: addi a2, a2, %lo(check)
; CHECK-NEXT: lw a2, 4(a2)
; CHECK-NEXT: bne a1, a2, .LBB0_6
; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: lui a1, %hi(x)
; CHECK-NEXT: addi a1, a1, %lo(x)
; CHECK-NEXT: lw a3, 8(a1)
; CHECK-NEXT: lui a2, %hi(check)
; CHECK-NEXT: addi a2, a2, %lo(check)
; CHECK-NEXT: lw a4, 8(a2)
; CHECK-NEXT: bne a3, a4, .LBB0_6
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: lw a1, 12(a1)
; CHECK-NEXT: lw a2, 12(a2)
; CHECK-NEXT: bne a1, a2, .LBB0_6
; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: lui a1, %hi(x)
; CHECK-NEXT: addi a1, a1, %lo(x)
; CHECK-NEXT: lw a3, 16(a1)
; CHECK-NEXT: lui a2, %hi(check)
; CHECK-NEXT: addi a2, a2, %lo(check)
; CHECK-NEXT: lw a4, 16(a2)
; CHECK-NEXT: bne a3, a4, .LBB0_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: lw a0, 20(a1)
; CHECK-NEXT: lw a1, 20(a2)
; CHECK-NEXT: xor a0, a0, a1
; CHECK-NEXT: snez a0, a0
; CHECK-NEXT: .LBB0_6:
; CHECK-NEXT: ret
%1 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 0), align 4
%2 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 0), align 4
%3 = icmp eq i32 %1, %2
br i1 %3, label %4, label %25
4:
%5 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 1), align 4
%6 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 1), align 4
%7 = icmp eq i32 %5, %6
br i1 %7, label %8, label %25
8:
%9 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 2), align 4
%10 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 2), align 4
%11 = icmp eq i32 %9, %10
br i1 %11, label %12, label %25
12:
%13 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 3), align 4
%14 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 3), align 4
%15 = icmp eq i32 %13, %14
br i1 %15, label %16, label %25
16:
%17 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 4), align 4
%18 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 4), align 4
%19 = icmp eq i32 %17, %18
br i1 %19, label %20, label %25
20:
%21 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 5), align 4
%22 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 5), align 4
%23 = icmp ne i32 %21, %22
%24 = zext i1 %23 to i32
br label %25
25:
%26 = phi i32 [ 1, %0 ], [ 1, %4 ], [ 1, %8 ], [ 1, %12 ], [ 1, %16 ], [ %24, %20 ]
ret i32 %26
}