[RISCV] Pre-commit test for D118216

[asb]

Although it's a bit repetitive, we typically try to run tests with both riscv32 and riscv64 if possible. It looks like this test case actually has identical assembly for RV32 and RV64, so you can just add a second CHECK line and leave them both using the default 'CHECK' prefix.

It would also be helpful to add a comment to the file explaining what it's trying to test. e.g. "This test case checks whether the address of an array is repeatedly rematerialised within a loop.".

[Luhaocong]

1. Add test for rv64.
2. Add description of test case.

[frasercrmck]

LGTM otherwise.

llvm/test/CodeGen/RISCV/unroll-loop-cse.ll

4

You don't need --check-prefix=CHECK at all, since it's the default.

[Luhaocong]

delete unnecessary CHECK

llvm/test/CodeGen/RISCV/unroll-loop-cse.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I
+
+@x = global [6 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5], align 4
+@check = global [6 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5], align 4
+
+define signext i32 @unroll_loop_cse() {
+; RV32I-LABEL: unroll_loop_cse:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, %hi(x)
+; RV32I-NEXT:    lw a3, %lo(x)(a1)
+; RV32I-NEXT:    lui a2, %hi(check)
+; RV32I-NEXT:    lw a4, %lo(check)(a2)
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    bne a3, a4, .LBB0_6
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    addi a1, a1, %lo(x)
+; RV32I-NEXT:    lw a1, 4(a1)
+; RV32I-NEXT:    addi a2, a2, %lo(check)
+; RV32I-NEXT:    lw a2, 4(a2)
+; RV32I-NEXT:    bne a1, a2, .LBB0_6
+; RV32I-NEXT:  # %bb.2:
+; RV32I-NEXT:    lui a1, %hi(x)
+; RV32I-NEXT:    addi a1, a1, %lo(x)
+; RV32I-NEXT:    lw a3, 8(a1)
+; RV32I-NEXT:    lui a2, %hi(check)
+; RV32I-NEXT:    addi a2, a2, %lo(check)
+; RV32I-NEXT:    lw a4, 8(a2)
+; RV32I-NEXT:    bne a3, a4, .LBB0_6
+; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:    lw a1, 12(a1)
+; RV32I-NEXT:    lw a2, 12(a2)
+; RV32I-NEXT:    bne a1, a2, .LBB0_6
+; RV32I-NEXT:  # %bb.4:
+; RV32I-NEXT:    lui a1, %hi(x)
+; RV32I-NEXT:    addi a1, a1, %lo(x)
+; RV32I-NEXT:    lw a3, 16(a1)
+; RV32I-NEXT:    lui a2, %hi(check)
+; RV32I-NEXT:    addi a2, a2, %lo(check)
+; RV32I-NEXT:    lw a4, 16(a2)
+; RV32I-NEXT:    bne a3, a4, .LBB0_6
+; RV32I-NEXT:  # %bb.5:
+; RV32I-NEXT:    lw a0, 20(a1)
+; RV32I-NEXT:    lw a1, 20(a2)
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:  .LBB0_6:
+; RV32I-NEXT:    ret
+  %1 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 0), align 4
+  %2 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 0), align 4
+  %3 = icmp eq i32 %1, %2
+  br i1 %3, label %4, label %25
+
+4:
+  %5 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 1), align 4
+  %6 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 1), align 4
+  %7 = icmp eq i32 %5, %6
+  br i1 %7, label %8, label %25
+
+8:
+  %9 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 2), align 4
+  %10 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 2), align 4
+  %11 = icmp eq i32 %9, %10
+  br i1 %11, label %12, label %25
+
+12:
+  %13 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 3), align 4
+  %14 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 3), align 4
+  %15 = icmp eq i32 %13, %14
+  br i1 %15, label %16, label %25
+
+16:
+  %17 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 4), align 4
+  %18 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 4), align 4
+  %19 = icmp eq i32 %17, %18
+  br i1 %19, label %20, label %25
+
+20:
+  %21 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @x, i64 0, i64 5), align 4
+  %22 = load i32, i32* getelementptr inbounds ([6 x i32], [6 x i32]* @check, i64 0, i64 5), align 4
+  %23 = icmp ne i32 %21, %22
+  %24 = zext i1 %23 to i32
+  br label %25
+
+25:
+  %26 = phi i32 [ 1, %0 ], [ 1, %4 ], [ 1, %8 ], [ 1, %12 ], [ 1, %16 ], [ %24, %20 ]
+  ret i32 %26
+}
+