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Differential D118199

[AArch64] ACLE feature macro for Armv8.8-A MOPS
ClosedPublic

Authored by tyb0807 on Jan 25 2022, 2:58 PM.

Details

Reviewers
ktkachov
chill
SjoerdMeijer
lenary
Matt
dmgreen
nickdesaulniers
t.p.northover
ab
Commits
rGc70b93508901: [AArch64] ACLE feature macro for Armv8.8-A MOPS
rGd379ec99085e: [AArch64] ACLE feature macro for Armv8.8-A MOPS
Summary

This introduces the new __ARM_FEATURE_MOPS ACLE feature test macro,
which signals the availability of the new Armv8.8-A/Armv9.3-A
instructions for standardising memcpy, memset and memmove operations.

This patch supersedes the one from https://reviews.llvm.org/D116160.

Diff Detail

Event Timeline

tyb0807 created this revision.Jan 25 2022, 2:58 PM
Herald added a subscriber: kristof.beyls. · View Herald TranscriptJan 25 2022, 2:58 PM
tyb0807 requested review of this revision.Jan 25 2022, 2:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 25 2022, 2:58 PM
Herald added a subscriber: cfe-commits. · View Herald Transcript
Harbormaster completed remote builds in B145611: Diff 403046.Jan 25 2022, 2:59 PM
tyb0807 added reviewers: ktkachov, chill, SjoerdMeijer, lenary, Matt, dmgreen, nickdesaulniers, t.p.northover, ab.Jan 25 2022, 3:00 PM
nickdesaulniers added a comment.Jan 25 2022, 6:18 PM

This patch supersedes the one from https://reviews.llvm.org/D116160.

Can that one be abandoned then?

tyb0807 added a comment.Jan 25 2022, 8:24 PM

Yes, https://reviews.llvm.org/D116160 is deprecated and will be abandoned.

tyb0807 updated this revision to Diff 404347.Jan 30 2022, 12:05 AM

Add more tests and update accordingly to change from ACLE specification: __builtin_arm_mops_memset_tag requires _both_ MOPS and MTE features

Harbormaster completed remote builds in B146517: Diff 404347.Jan 30 2022, 12:05 AM
tyb0807 added a parent revision: D117764: [AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS.Jan 30 2022, 1:39 PM
tyb0807 updated this revision to Diff 404854.Feb 1 2022, 2:29 AM

Add support for +nomops

Harbormaster completed remote builds in B146845: Diff 404854.Feb 1 2022, 3:12 AM
tyb0807 updated this revision to Diff 404897.Feb 1 2022, 5:36 AM

Revert latest patchset, as it should be put into a separate commit for clarity

Harbormaster completed remote builds in B146875: Diff 404897.Feb 1 2022, 6:50 AM
chill added inline comments.Feb 1 2022, 8:31 AM
clang/lib/Basic/Targets/AArch64.cpp
229

What's the deal with "+nomops" ? This FIXME sort of contradicts with an earlier comment

Add support for +nomops

chill added a comment.Feb 1 2022, 8:41 AM

I suppose clang/test/CodeGen/aarch64-mops.c needs to be run with clang -march=armv8-a+mops+memtag (not clang_cc1) so it picks up declarations of tagging intrinsics from arm_acle.h.

chill added a comment.Feb 1 2022, 9:46 AM
In D118199#3287636, @chill wrote:

I suppose clang/test/CodeGen/aarch64-mops.c needs to be run with clang -march=armv8-a+mops+memtag (not clang_cc1) so it picks up declarations of tagging intrinsics from arm_acle.h.

Uhm, scratch that.

For checking diagnostics, clang_cc1 --verify.

tyb0807 updated this revision to Diff 405080.Feb 1 2022, 1:31 PM
tyb0807 marked an inline comment as done.

Update tests with clang_cc1 -verify

clang/lib/Basic/Targets/AArch64.cpp
229

I wanted to add support for +nomops, but I think it is advisable to keep that in a separate commit to not block this review, so I reverted it with a FIXME

tyb0807 updated this revision to Diff 405083.Feb 1 2022, 1:37 PM

Update tests with clang -Xclang -verify

tyb0807 updated this revision to Diff 405085.Feb 1 2022, 1:39 PM

Remove prefix from tests

Harbormaster completed remote builds in B147011: Diff 405085.Feb 1 2022, 4:19 PM
tyb0807 mentioned this in D116160: [AArch64] ACLE feature macro for Armv8.8-A MOPS.Feb 7 2022, 3:24 AM
chill accepted this revision.Feb 8 2022, 4:08 AM
This revision is now accepted and ready to land.Feb 8 2022, 4:08 AM
This revision was landed with ongoing or failed builds.Feb 8 2022, 1:08 PM
Closed by commit rGd379ec99085e: [AArch64] ACLE feature macro for Armv8.8-A MOPS (authored by tyb0807). · Explain Why
This revision was automatically updated to reflect the committed changes.
tyb0807 added a commit: rGd379ec99085e: [AArch64] ACLE feature macro for Armv8.8-A MOPS.
browneee added a subscriber: browneee.Feb 8 2022, 3:23 PM

Hi,

This change appears to break on of the buildbots (clang-ppc64le-linux-lnt):
https://lab.llvm.org/buildbot/#/builders/105/builds/21233/steps/7/logs/FAIL__Clang__aarch64-mops_c

******************** TEST 'Clang :: CodeGen/aarch64-mops.c' FAILED ********************
Script:
--
: 'RUN: at line 3';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -cc1 -internal-isystem /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/lib/clang/15.0.0/include -nostdsysteminc -triple aarch64-arm-unknown-eabi -target-feature +mops -target-feature +mte -S -emit-llvm -o - /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c  | /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/FileCheck /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
: 'RUN: at line 4';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -cc1 -internal-isystem /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/lib/clang/15.0.0/include -nostdsysteminc -triple aarch64-arm-unknown-eabi -verify /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
: 'RUN: at line 5';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv8.7-a+mops+memtag          -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o - | /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/FileCheck /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
: 'RUN: at line 6';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv8.8-a+memtag               -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o - | /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/FileCheck /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
: 'RUN: at line 7';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv9.2-a+mops+memtag          -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o - | /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/FileCheck /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
: 'RUN: at line 8';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv9.3-a+memtag               -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o - | /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/FileCheck /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
: 'RUN: at line 9';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv8.7-a      -Xclang -verify -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o -
: 'RUN: at line 10';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv8.7-a+mops -Xclang -verify -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o -
: 'RUN: at line 11';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv8.8-a      -Xclang -verify -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o -
: 'RUN: at line 12';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv9.2-a      -Xclang -verify -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o -
: 'RUN: at line 13';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv9.2-a+mops -Xclang -verify -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o -
: 'RUN: at line 14';   /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/clang -target aarch64-arm-none-eabi -march=armv9.3-a      -Xclang -verify -S -emit-llvm /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c -o -
--
Exit Code: 2
Command Output (stderr):
--
In file included from /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c:16:
In file included from /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/lib/clang/15.0.0/include/arm_acle.h:17:
In file included from /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/lib/clang/15.0.0/include/stdint.h:52:
In file included from /usr/include/stdint.h:26:
In file included from /usr/include/bits/libc-header-start.h:33:
In file included from /usr/include/features.h:452:
/usr/include/gnu/stubs.h:8:11: fatal error: 'gnu/stubs-32.h' file not found
# include <gnu/stubs-32.h>
          ^~~~~~~~~~~~~~~~
1 error generated.
FileCheck error: '<stdin>' is empty.
FileCheck command line:  /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/stage1/bin/FileCheck /home/buildbots/ppc64le-clang-lnt-test/clang-ppc64le-lnt/llvm/clang/test/CodeGen/aarch64-mops.c
--
********************
tyb0807 added a reverting change: rG9b81d2fae8c0: Revert "[AArch64] ACLE feature macro for Armv8.8-A MOPS".Feb 8 2022, 4:11 PM
tyb0807 reopened this revision.Feb 8 2022, 4:12 PM

Reverted due to buildbots failures

This revision is now accepted and ready to land.Feb 8 2022, 4:12 PM
tyb0807 updated this revision to Diff 407155.Feb 9 2022, 7:10 AM

Fix buildbots failures

tyb0807 updated this revision to Diff 407159.Feb 9 2022, 7:31 AM

Turn off warnings for negative tests

Harbormaster completed remote builds in B148486: Diff 407159.Feb 9 2022, 7:59 AM
chill accepted this revision.Feb 9 2022, 12:50 PM
This revision was landed with ongoing or failed builds.Feb 10 2022, 1:09 AM
Closed by commit rGc70b93508901: [AArch64] ACLE feature macro for Armv8.8-A MOPS (authored by tyb0807). · Explain Why
This revision was automatically updated to reflect the committed changes.
tyb0807 added a commit: rGc70b93508901: [AArch64] ACLE feature macro for Armv8.8-A MOPS.

Revision Contents

PathSize
clang/
lib/
Basic/
Targets/
7 lines
test/
CodeGen/
325 lines
Preprocessor/
12 lines

Diff 404347

clang/lib/Basic/Targets/AArch64.cpp

//===--- AArch64.cpp - Implement AArch64 target feature support -----------===// //===--- AArch64.cpp - Implement AArch64 target feature support -----------===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Lines
void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV87A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Also include the Armv8.6 defines // Also include the Armv8.6 defines
getTargetDefinesARMV86A(Opts, Builder); getTargetDefinesARMV86A(Opts, Builder);
} }
void AArch64TargetInfo::getTargetDefinesARMV88A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV88A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// FIXME: this does not handle the case where MOPS is disabled using +nomops
chillUnsubmitted
Done
ReplyInline Actions

What's the deal with "+nomops" ? This FIXME sort of contradicts with an earlier comment

Add support for +nomops

chill: What's the deal with `"+nomops"` ? This FIXME sort of contradicts with an earlier comment >…
tyb0807AuthorUnsubmitted
Done
ReplyInline Actions

I wanted to add support for +nomops, but I think it is advisable to keep that in a separate commit to not block this review, so I reverted it with a FIXME

tyb0807: I wanted to add support for `+nomops`, but I think it is advisable to keep that in a separate…
Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
// Also include the Armv8.7 defines // Also include the Armv8.7 defines
getTargetDefinesARMV87A(Opts, Builder); getTargetDefinesARMV87A(Opts, Builder);
} }
void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts, void AArch64TargetInfo::getTargetDefinesARMV9A(const LangOptions &Opts,
MacroBuilder &Builder) const { MacroBuilder &Builder) const {
// Armv9-A maps to Armv8.5-A // Armv9-A maps to Armv8.5-A
getTargetDefinesARMV85A(Opts, Builder); getTargetDefinesARMV85A(Opts, Builder);
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines if (Opts.BranchTargetEnforcement)
Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1"); Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
if (HasLS64) if (HasLS64)
Builder.defineMacro("__ARM_FEATURE_LS64", "1"); Builder.defineMacro("__ARM_FEATURE_LS64", "1");
if (HasRandGen) if (HasRandGen)
Builder.defineMacro("__ARM_FEATURE_RNG", "1"); Builder.defineMacro("__ARM_FEATURE_RNG", "1");
if (HasMOPS)
Builder.defineMacro("__ARM_FEATURE_MOPS", "1");
switch (ArchKind) { switch (ArchKind) {
default: default:
break; break;
case llvm::AArch64::ArchKind::ARMV8_1A: case llvm::AArch64::ArchKind::ARMV8_1A:
getTargetDefinesARMV81A(Opts, Builder); getTargetDefinesARMV81A(Opts, Builder);
break; break;
case llvm::AArch64::ArchKind::ARMV8_2A: case llvm::AArch64::ArchKind::ARMV8_2A:
getTargetDefinesARMV82A(Opts, Builder); getTargetDefinesARMV82A(Opts, Builder);
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines for (const auto &Feature : Features) {
if (Feature == "+ls64") if (Feature == "+ls64")
HasLS64 = true; HasLS64 = true;
if (Feature == "+rand") if (Feature == "+rand")
HasRandGen = true; HasRandGen = true;
if (Feature == "+flagm") if (Feature == "+flagm")
HasFlagM = true; HasFlagM = true;
if (Feature == "+hbc") if (Feature == "+hbc")
HasHBC = true; HasHBC = true;
if (Feature == "+mops")
HasMOPS = true;
} }
setDataLayout(); setDataLayout();
return true; return true;
} }
TargetInfo::CallingConvCheckResult TargetInfo::CallingConvCheckResult
▲ Show 20 Lines • Show All 394 Lines • Show Last 20 Lines

clang/test/CodeGen/aarch64-mops.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -target-feature +mops -target-feature +mte -S -emit-llvm -o - %s | FileCheck %s // RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -target-feature +mops -target-feature +mte -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang_cc1 -triple aarch64-arm-unknown-eabi -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-NOMOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.7-a+mops+memtag -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.7-a -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.8-a+memtag -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.8-a -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.2-a+mops+memtag -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.2-a -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a+memtag -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
#define __ARM_FEATURE_MOPS 1
#include <arm_acle.h> #include <arm_acle.h>
#include <stddef.h> #include <stddef.h>
// CHECK-LABEL: @bzero_0( // CHECK-MOPS-LABEL: @bzero_0(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 0) // CHECK-MOPS-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 0)
// CHECK-NEXT: ret i8* [[TMP1]] // CHECK-MOPS-NEXT: ret i8* [[TMP1]]
//
// CHECK-NOMOPS-LABEL: @bzero_0(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef 0, i32 noundef 0)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP1]]
// //
void *bzero_0(void *dst) { void *bzero_0(void *dst) {
return __arm_mops_memset_tag(dst, 0, 0); return __arm_mops_memset_tag(dst, 0, 0);
} }
// CHECK-LABEL: @bzero_1( // CHECK-MOPS-LABEL: @bzero_1(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 1) // CHECK-MOPS-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 1)
// CHECK-NEXT: ret i8* [[TMP1]] // CHECK-MOPS-NEXT: ret i8* [[TMP1]]
//
// CHECK-NOMOPS-LABEL: @bzero_1(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef 0, i32 noundef 1)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP1]]
// //
void *bzero_1(void *dst) { void *bzero_1(void *dst) {
return __arm_mops_memset_tag(dst, 0, 1); return __arm_mops_memset_tag(dst, 0, 1);
} }
// CHECK-LABEL: @bzero_10( // CHECK-MOPS-LABEL: @bzero_10(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 10) // CHECK-MOPS-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 10)
// CHECK-NEXT: ret i8* [[TMP1]] // CHECK-MOPS-NEXT: ret i8* [[TMP1]]
//
// CHECK-NOMOPS-LABEL: @bzero_10(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef 0, i32 noundef 10)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP1]]
// //
void *bzero_10(void *dst) { void *bzero_10(void *dst) {
return __arm_mops_memset_tag(dst, 0, 10); return __arm_mops_memset_tag(dst, 0, 10);
} }
// CHECK-LABEL: @bzero_10000( // CHECK-MOPS-LABEL: @bzero_10000(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 10000) // CHECK-MOPS-NEXT: [[TMP1:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 10000)
// CHECK-NEXT: ret i8* [[TMP1]] // CHECK-MOPS-NEXT: ret i8* [[TMP1]]
//
// CHECK-NOMOPS-LABEL: @bzero_10000(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef 0, i32 noundef 10000)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP1]]
// //
void *bzero_10000(void *dst) { void *bzero_10000(void *dst) {
return __arm_mops_memset_tag(dst, 0, 10000); return __arm_mops_memset_tag(dst, 0, 10000);
} }
// CHECK-LABEL: @bzero_n( // CHECK-MOPS-LABEL: @bzero_n(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: [[SIZE_ADDR:%.*]] = alloca i64, align 8 // CHECK-MOPS-NEXT: [[SIZE_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: store i64 [[SIZE:%.*]], i64* [[SIZE_ADDR]], align 8 // CHECK-MOPS-NEXT: store i64 [[SIZE:%.*]], i64* [[SIZE_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIZE_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIZE_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 [[TMP1]]) // CHECK-MOPS-NEXT: [[TMP2:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 0, i64 [[TMP1]])
// CHECK-NEXT: ret i8* [[TMP2]] // CHECK-MOPS-NEXT: ret i8* [[TMP2]]
//
// CHECK-NOMOPS-LABEL: @bzero_n(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: [[SIZE_ADDR:%.*]] = alloca i64, align 8
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: store i64 [[SIZE:%.*]], i64* [[SIZE_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = load i64, i64* [[SIZE_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i64)*)(i8* noundef [[TMP0]], i32 noundef 0, i64 noundef [[TMP1]])
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP2]]
// //
void *bzero_n(void *dst, size_t size) { void *bzero_n(void *dst, size_t size) {
return __arm_mops_memset_tag(dst, 0, size); return __arm_mops_memset_tag(dst, 0, size);
} }
// CHECK-LABEL: @memset_0( // CHECK-MOPS-LABEL: @memset_0(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 // CHECK-MOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 // CHECK-MOPS-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
// CHECK-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 0) // CHECK-MOPS-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 0)
// CHECK-NEXT: ret i8* [[TMP3]] // CHECK-MOPS-NEXT: ret i8* [[TMP3]]
//
// CHECK-NOMOPS-LABEL: @memset_0(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef [[TMP1]], i32 noundef 0)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP2]]
// //
void *memset_0(void *dst, int value) { void *memset_0(void *dst, int value) {
return __arm_mops_memset_tag(dst, value, 0); return __arm_mops_memset_tag(dst, value, 0);
} }
// CHECK-LABEL: @memset_1( // CHECK-MOPS-LABEL: @memset_1(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 // CHECK-MOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 // CHECK-MOPS-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
// CHECK-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 1) // CHECK-MOPS-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 1)
// CHECK-NEXT: ret i8* [[TMP3]] // CHECK-MOPS-NEXT: ret i8* [[TMP3]]
//
// CHECK-NOMOPS-LABEL: @memset_1(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef [[TMP1]], i32 noundef 1)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP2]]
// //
void *memset_1(void *dst, int value) { void *memset_1(void *dst, int value) {
return __arm_mops_memset_tag(dst, value, 1); return __arm_mops_memset_tag(dst, value, 1);
} }
// CHECK-LABEL: @memset_10( // CHECK-MOPS-LABEL: @memset_10(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 // CHECK-MOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 // CHECK-MOPS-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
// CHECK-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 10) // CHECK-MOPS-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 10)
// CHECK-NEXT: ret i8* [[TMP3]] // CHECK-MOPS-NEXT: ret i8* [[TMP3]]
//
// CHECK-NOMOPS-LABEL: @memset_10(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef [[TMP1]], i32 noundef 10)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP2]]
// //
void *memset_10(void *dst, int value) { void *memset_10(void *dst, int value) {
return __arm_mops_memset_tag(dst, value, 10); return __arm_mops_memset_tag(dst, value, 10);
} }
// CHECK-LABEL: @memset_10000( // CHECK-MOPS-LABEL: @memset_10000(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 // CHECK-MOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8 // CHECK-MOPS-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i8
// CHECK-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 10000) // CHECK-MOPS-NEXT: [[TMP3:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP2]], i64 10000)
// CHECK-NEXT: ret i8* [[TMP3]] // CHECK-MOPS-NEXT: ret i8* [[TMP3]]
//
// CHECK-NOMOPS-LABEL: @memset_10000(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i32)*)(i8* noundef [[TMP0]], i32 noundef [[TMP1]], i32 noundef 10000)
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP2]]
// //
void *memset_10000(void *dst, int value) { void *memset_10000(void *dst, int value) {
return __arm_mops_memset_tag(dst, value, 10000); return __arm_mops_memset_tag(dst, value, 10000);
} }
// CHECK-LABEL: @memset_n( // CHECK-MOPS-LABEL: @memset_n(
// CHECK-NEXT: entry: // CHECK-MOPS: entry:
// CHECK-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8 // CHECK-MOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4 // CHECK-MOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[SIZE_ADDR:%.*]] = alloca i64, align 8 // CHECK-MOPS-NEXT: [[SIZE_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: store i64 [[SIZE:%.*]], i64* [[SIZE_ADDR]], align 8 // CHECK-MOPS-NEXT: store i64 [[SIZE:%.*]], i64* [[SIZE_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4 // CHECK-MOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[SIZE_ADDR]], align 8 // CHECK-MOPS-NEXT: [[TMP2:%.*]] = load i64, i64* [[SIZE_ADDR]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP1]] to i8 // CHECK-MOPS-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP1]] to i8
// CHECK-NEXT: [[TMP4:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP3]], i64 [[TMP2]]) // CHECK-MOPS-NEXT: [[TMP4:%.*]] = call i8* @llvm.aarch64.mops.memset.tag(i8* [[TMP0]], i8 [[TMP3]], i64 [[TMP2]])
// CHECK-NEXT: ret i8* [[TMP4]] // CHECK-MOPS-NEXT: ret i8* [[TMP4]]
//
// CHECK-NOMOPS-LABEL: @memset_n(
// CHECK-NOMOPS: entry:
// CHECK-NOMOPS-NEXT: [[DST_ADDR:%.*]] = alloca i8*, align 8
// CHECK-NOMOPS-NEXT: [[VALUE_ADDR:%.*]] = alloca i32, align 4
// CHECK-NOMOPS-NEXT: [[SIZE_ADDR:%.*]] = alloca i64, align 8
// CHECK-NOMOPS-NEXT: store i8* [[DST:%.*]], i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: store i32 [[VALUE:%.*]], i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: store i64 [[SIZE:%.*]], i64* [[SIZE_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP0:%.*]] = load i8*, i8** [[DST_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[TMP1:%.*]] = load i32, i32* [[VALUE_ADDR]], align 4
// CHECK-NOMOPS-NEXT: [[TMP2:%.*]] = load i64, i64* [[SIZE_ADDR]], align 8
// CHECK-NOMOPS-NEXT: [[CALL:%.*]] = call i32 bitcast (i32 (...)* @__arm_mops_memset_tag to i32 (i8*, i32, i64)*)(i8* noundef [[TMP0]], i32 noundef [[TMP1]], i64 noundef [[TMP2]])
// CHECK-NOMOPS-NEXT: [[CONV:%.*]] = sext i32 [[CALL]] to i64
// CHECK-NOMOPS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[CONV]] to i8*
// CHECK-NOMOPS-NEXT: ret i8* [[TMP3]]
// //
void *memset_n(void *dst, int value, size_t size) { void *memset_n(void *dst, int value, size_t size) {
return __arm_mops_memset_tag(dst, value, size); return __arm_mops_memset_tag(dst, value, size);
} }

clang/test/Preprocessor/aarch64-target-features.c

Show First 20 Lines • Show All 510 Lines • ▼ Show 20 Lines
// CHECK-NO-SVE-VECTOR-BITS-NOT: __ARM_FEATURE_SVE_VECTOR_OPERATORS // CHECK-NO-SVE-VECTOR-BITS-NOT: __ARM_FEATURE_SVE_VECTOR_OPERATORS
// ================== Check Largse System Extensions (LSE) // ================== Check Largse System Extensions (LSE)
// RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+lse -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+lse -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+lse -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+lse -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s
// RUN: %clang -target aarch64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s // RUN: %clang -target aarch64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s
// RUN: %clang -target arm64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-LSE %s
// CHECK-LSE: __ARM_FEATURE_ATOMICS 1 // CHECK-LSE: __ARM_FEATURE_ATOMICS 1
// ================== Check Armv8.8-A/Armv9.3-A memcpy and memset acceleration instructions (MOPS)
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.7-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.7-a+mops -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.8-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.8-a+mops -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.2-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-NOMOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.2-a+mops -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// RUN: %clang -target aarch64-arm-none-eabi -march=armv9.3-a+mops -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-MOPS %s
// CHECK-MOPS: __ARM_FEATURE_MOPS 1
// CHECK-NOMOPS-NOT: __ARM_FEATURE_MOPS 1