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[AArch64][SVE] Implement missing lowering for extract_subvector for predicates.
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Authored by sdesmalen on Jan 24 2022, 10:21 AM.

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sdesmalen created this revision.Jan 24 2022, 10:21 AM
sdesmalen requested review of this revision.Jan 24 2022, 10:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 24 2022, 10:21 AM
efriedma added inline comments.Jan 24 2022, 3:47 PM
llvm/test/CodeGen/AArch64/sve-insert-vector.ll
557

I don't get this. <vscale x 4 x i1> doesn't have the right layout; it has padding bits in between each value bit.

sdesmalen updated this revision to Diff 402845.Jan 25 2022, 4:26 AM

Removed erroneous fold, and implemented the operation as operation-lowering instead of a DAGCombine.

sdesmalen edited the summary of this revision. (Show Details)Jan 25 2022, 4:27 AM
sdesmalen added inline comments.
llvm/test/CodeGen/AArch64/sve-insert-vector.ll
557

You're right, I had my wires crossed here, thanks for pointing out!

This revision is now accepted and ready to land.Jan 25 2022, 10:32 AM
Matt added a subscriber: Matt.Jan 25 2022, 3:22 PM
This revision was landed with ongoing or failed builds.Jan 27 2022, 3:01 AM
This revision was automatically updated to reflect the committed changes.