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Differential D118013

[RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv.
ClosedPublic

Authored by craig.topper on Jan 23 2022, 9:40 PM.

Details

Reviewers
frasercrmck
rogfer01
khchen
arcbbb
kito-cheng
HanKuanChen
Commits
rGcd2a9ff39788: [RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv.
Summary

Add might be faster than shift. We can't do this earlier without
using a Freeze instruction.

This is the intrinsic version of D106689.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 23 2022, 9:40 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptJan 23 2022, 9:40 PM
craig.topper requested review of this revision.Jan 23 2022, 9:40 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 23 2022, 9:40 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper added a reviewer: HanKuanChen.Jan 23 2022, 11:02 PM
Harbormaster completed remote builds in B145156: Diff 402394.Jan 23 2022, 11:32 PM
frasercrmck accepted this revision.Jan 24 2022, 2:27 AM

LGTM

This revision is now accepted and ready to land.Jan 24 2022, 2:27 AM
This revision was landed with ongoing or failed builds.Jan 24 2022, 8:05 AM
Closed by commit rGcd2a9ff39788: [RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGcd2a9ff39788: [RISCV] Select int_riscv_vsll with shift of 1 to vadd.vv..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
24 lines
test/
CodeGen/
RISCV/
rvv/
32 lines
32 lines

Diff 402534

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors, defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsll", "PseudoVSLL", AllIntegerVectors,
uimm5>; uimm5>;
defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors, defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsrl", "PseudoVSRL", AllIntegerVectors,
uimm5>; uimm5>;
defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors, defm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
uimm5>; uimm5>;
foreach vti = AllIntegerVectors in {
// Emit shift by 1 as an add since it might be faster.
def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector vti.RegClass:$rs1),
(XLenVT 1), VLOpFrag)),
(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
vti.RegClass:$rs1,
GPR:$vl,
vti.Log2SEW)>;
def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs1),
(XLenVT 1),
(vti.Mask V0),
VLOpFrag,
(XLenVT timm:$policy))),
(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK")
vti.RegClass:$merge,
vti.RegClass:$rs1,
vti.RegClass:$rs1,
(vti.Mask V0),
GPR:$vl,
vti.Log2SEW,
(XLenVT timm:$policy))>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.7. Vector Narrowing Integer Right Shift Instructions // 12.7. Vector Narrowing Integer Right Shift Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>; defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>;
defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>; defm : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.8. Vector Integer Comparison Instructions // 12.8. Vector Integer Comparison Instructions
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llvm/test/CodeGen/RISCV/rvv/vsll-rv32.ll

Show First 20 Lines • Show All 1,994 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i32 9, i32 9,
i32 %1) i32 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_1_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0,
i32 1,
i32 %1)
ret <vscale x 1 x i8> %a
}
define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3, i32 1) i32 %3, i32 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i32 1,
<vscale x 1 x i1> %2,
i32 %3, i32 1)
ret <vscale x 1 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
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llvm/test/CodeGen/RISCV/rvv/vsll-rv64.ll

Show First 20 Lines • Show All 1,994 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
i64 9, i64 9,
i64 %1) i64 %1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_1_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.nxv1i8(
<vscale x 1 x i8> %0,
i64 1,
i64 %1)
ret <vscale x 1 x i8> %a
}
define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind { define <vscale x 1 x i8> @intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vsll_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t ; CHECK-NEXT: vsll.vi v8, v9, 9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3, i64 1) i64 %3, i64 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
define <vscale x 1 x i8> @intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsll_mask_1_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vadd.vv v8, v9, v9, v0.t
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsll.mask.nxv1i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i64 1,
<vscale x 1 x i1> %2,
i64 %3, i64 1)
ret <vscale x 1 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i8> @intrinsic_vsll_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vsll_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vsll.vi v8, v8, 9 ; CHECK-NEXT: vsll.vi v8, v8, 9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8( %a = call <vscale x 2 x i8> @llvm.riscv.vsll.nxv2i8(
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