[RISCV] Select vector shl by 1 to a vector add.

[craig.topper]

Summary

A vector add may be faster than a vector shift.

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 defm : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
 defm : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
 defm : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
 defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
 
+foreach vti = AllIntegerVectors in {
+  // Emit shift by 1 as an add since it might be faster.
+  def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
+                 (vti.Vector (splat_vector (XLenVT 1)))),
+            (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
+                 vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+}
+foreach vti = [VI64M1, VI64M2, VI64M4, VI64M8] in {
+  def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
+                 (vti.Vector (rv32_splat_i64 (XLenVT 1)))),
+            (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
+                 vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>;
+
+}
+
 // 12.8. Vector Integer Comparison Instructions
 defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ,  "PseudoVMSEQ">;
 defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE,  "PseudoVMSNE">;
 
 defm : VPatIntegerSetCCSDNode_VV_VX<SETLT,  "PseudoVMSLT">;
 defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
 defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
                                       SplatPat_simm5_plus1>;

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

 defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl,  "PseudoVOR">;
 defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>;
 defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>;
 defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>;
 
-
+foreach vti = AllIntegerVectors in {
+  // Emit shift by 1 as an add since it might be faster.
+  def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1),
+                          (riscv_vmv_v_x_vl 1, (XLenVT srcvalue)),
+                          (vti.Mask true_mask),
+                          VLOpFrag),
+            (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
+                 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
+}
 
 // 12.7. Vector Narrowing Integer Right Shift Instructions
 foreach vtiTowti = AllWidenableIntVectors in {
   defvar vti = vtiTowti.Vti;
   defvar wti = vtiTowti.Wti;
   def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1),
                                                (vti.Mask true_mask),
                                                VLOpFrag)),

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

 ; LMULMAX2-RV32-NEXT:    lui a1, 13
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX2-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 5
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vand.vx v26, v25, a1
-; LMULMAX2-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 11
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV32-NEXT:    vse16.v v25, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;

 ; LMULMAX2-RV64-NEXT:    lui a1, 13
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -820
 ; LMULMAX2-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX2-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV64-NEXT:    lui a1, 5
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v25, a1
-; LMULMAX2-RV64-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX2-RV64-NEXT:    lui a1, 11
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1366
 ; LMULMAX2-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX2-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV64-NEXT:    vse16.v v25, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;

 ; LMULMAX1-RV32-NEXT:    lui a1, 13
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 5
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v25, a1
-; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 11
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;

 ; LMULMAX1-RV64-NEXT:    lui a1, 13
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, -820
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV64-NEXT:    lui a1, 5
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v25, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV64-NEXT:    lui a1, 11
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, -1366
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV64-NEXT:    vse16.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <8 x i16>, <8 x i16>* %x

 ; LMULMAX2-RV32-NEXT:    lui a1, 838861
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX2-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vand.vx v26, v25, a1
-; LMULMAX2-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 699051
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;

 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -820
 ; LMULMAX2-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX2-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV64-NEXT:    lui a1, 349525
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v25, a1
-; LMULMAX2-RV64-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX2-RV64-NEXT:    lui a1, 171
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX2-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV64-NEXT:    vse32.v v25, (a0)

 ; LMULMAX1-RV32-NEXT:    lui a1, 838861
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 349525
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v25, a1
-; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 699051
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;

 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, -820
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV64-NEXT:    lui a1, 349525
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v25, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV64-NEXT:    lui a1, 171
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, -1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, -1366
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV64-NEXT:    vse32.v v25, (a0)

 ; LMULMAX2-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v26, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX2-RV32-NEXT:    vand.vv v26, v25, v26
-; LMULMAX2-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX2-RV32-NEXT:    lui a1, 699051
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v27, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX2-RV32-NEXT:    vand.vv v25, v25, v27
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX2-RV32-NEXT:    vor.vv v25, v25, v26

 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v25, a1
-; LMULMAX2-RV64-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX2-RV64-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX2-RV64-NEXT:    lui a1, 1026731
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1366

 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 349525
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v26, a1
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v26, v25, v26
-; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV32-NEXT:    lui a1, 699051
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v27, a1
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26

 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v25, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV64-NEXT:    lui a1, 1026731
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, -1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, -1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, -1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, -1366

 ; LMULMAX2-RV32-NEXT:    lui a1, 13
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX2-RV32-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 5
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vand.vx v28, v26, a1
-; LMULMAX2-RV32-NEXT:    vsll.vi v28, v28, 1
+; LMULMAX2-RV32-NEXT:    vadd.vv v28, v28, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 11
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV32-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;

 ; LMULMAX2-RV64-NEXT:    lui a1, 13
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -820
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX2-RV64-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 5
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vand.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT:    vsll.vi v28, v28, 1
+; LMULMAX2-RV64-NEXT:    vadd.vv v28, v28, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 11
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1366
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX2-RV64-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse16.v v26, (a0)
 ; LMULMAX2-RV64-NEXT:    ret
 ;

 ; LMULMAX1-RV32-NEXT:    lui a5, 13
 ; LMULMAX1-RV32-NEXT:    addi a5, a5, -820
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a5
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    lui a1, 5
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v25, a1
-; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV32-NEXT:    lui a2, 11
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, -1366
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a2
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v27, v26, 8
 ; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 8
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v26, a7
 ; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 4
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v26, a3
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v26, 4
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v26, a4
 ; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 2
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v26, a5
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v26, a1
-; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v26, a2
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vse16.v v26, (a0)
 ; LMULMAX1-RV32-NEXT:    vse16.v v25, (a6)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: bitreverse_v16i16:

 ; LMULMAX1-RV64-NEXT:    lui a5, 13
 ; LMULMAX1-RV64-NEXT:    addiw a5, a5, -820
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a5
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    lui a1, 5
 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v25, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV64-NEXT:    lui a2, 11
 ; LMULMAX1-RV64-NEXT:    addiw a2, a2, -1366
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a2
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v27, v26, 8
 ; LMULMAX1-RV64-NEXT:    vsll.vi v26, v26, 8
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v26, a7
 ; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 4
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v26, a3
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v26, v26, 4
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v26, a4
 ; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 2
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v26, a5
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v26, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v26, a2
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vse16.v v26, (a0)
 ; LMULMAX1-RV64-NEXT:    vse16.v v25, (a6)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <16 x i16>, <16 x i16>* %x
   %b = load <16 x i16>, <16 x i16>* %y

 ; LMULMAX2-RV32-NEXT:    lui a1, 838861
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX2-RV32-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vand.vx v28, v26, a1
-; LMULMAX2-RV32-NEXT:    vsll.vi v28, v28, 1
+; LMULMAX2-RV32-NEXT:    vadd.vv v28, v28, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 699051
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV32-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    vse32.v v26, (a0)
 ; LMULMAX2-RV32-NEXT:    ret
 ;

 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -820
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX2-RV64-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 349525
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vand.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT:    vsll.vi v28, v28, 1
+; LMULMAX2-RV64-NEXT:    vadd.vv v28, v28, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 171
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV64-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX2-RV64-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX2-RV64-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV64-NEXT:    vse32.v v26, (a0)

 ; LMULMAX1-RV32-NEXT:    lui a1, 838861
 ; LMULMAX1-RV32-NEXT:    addi a1, a1, -820
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    lui a2, 349525
 ; LMULMAX1-RV32-NEXT:    addi a2, a2, 1365
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v25, a2
-; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV32-NEXT:    lui a4, 699051
 ; LMULMAX1-RV32-NEXT:    addi a4, a4, -1366
 ; LMULMAX1-RV32-NEXT:    vand.vx v25, v25, a4
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v27, v26, 8
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v27, t0
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v28, v26, 24

 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v26, 4
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v26, a3
 ; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 2
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v27, v26, a2
-; LMULMAX1-RV32-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV32-NEXT:    vand.vx v26, v26, a4
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vse32.v v26, (a0)
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a7)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: bitreverse_v8i32:

 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, -820
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a1
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    lui a2, 349525
 ; LMULMAX1-RV64-NEXT:    addiw a2, a2, 1365
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v25, a2
-; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV64-NEXT:    lui a4, 171
 ; LMULMAX1-RV64-NEXT:    addiw a4, a4, -1365
 ; LMULMAX1-RV64-NEXT:    slli a4, a4, 12
 ; LMULMAX1-RV64-NEXT:    addi a4, a4, -1366
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a4
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v27, v26, 8

 ; LMULMAX1-RV64-NEXT:    vsrl.vi v26, v26, 4
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v26, a3
 ; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 2
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v26, a1
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v26, a2
-; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v26, v26, a4
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v26, v26, v27
 ; LMULMAX1-RV64-NEXT:    vse32.v v26, (a0)
 ; LMULMAX1-RV64-NEXT:    vse32.v v25, (a7)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <8 x i32>, <8 x i32>* %x
   %b = load <8 x i32>, <8 x i32>* %y

 ; LMULMAX2-RV32-NEXT:    vsrl.vi v26, v26, 2
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 349525
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v28, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; LMULMAX2-RV32-NEXT:    vand.vv v28, v26, v28
-; LMULMAX2-RV32-NEXT:    vsll.vi v28, v28, 1
+; LMULMAX2-RV32-NEXT:    vadd.vv v28, v28, v28
 ; LMULMAX2-RV32-NEXT:    lui a1, 699051
 ; LMULMAX2-RV32-NEXT:    addi a1, a1, -1366
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; LMULMAX2-RV32-NEXT:    vmv.v.x v30, a1
 ; LMULMAX2-RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, mu
 ; LMULMAX2-RV32-NEXT:    vand.vv v26, v26, v30
 ; LMULMAX2-RV32-NEXT:    vsrl.vi v26, v26, 1
 ; LMULMAX2-RV32-NEXT:    vor.vv v26, v26, v28

 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX2-RV64-NEXT:    vand.vx v28, v26, a1
-; LMULMAX2-RV64-NEXT:    vsll.vi v28, v28, 1
+; LMULMAX2-RV64-NEXT:    vadd.vv v28, v28, v28
 ; LMULMAX2-RV64-NEXT:    lui a1, 1026731
 ; LMULMAX2-RV64-NEXT:    addiw a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1365
 ; LMULMAX2-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX2-RV64-NEXT:    addi a1, a1, -1366

 ; LMULMAX1-RV32-NEXT:    vsrl.vi v31, v31, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v31, v10
 ; LMULMAX1-RV32-NEXT:    lui a5, 349525
 ; LMULMAX1-RV32-NEXT:    addi a5, a5, 1365
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v10, a5
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v12, v31, v10
-; LMULMAX1-RV32-NEXT:    vsll.vi v12, v12, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v12, v12, v12
 ; LMULMAX1-RV32-NEXT:    lui a5, 699051
 ; LMULMAX1-RV32-NEXT:    addi a5, a5, -1366
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.x v13, a5
 ; LMULMAX1-RV32-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; LMULMAX1-RV32-NEXT:    vand.vv v31, v31, v13
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v31, v31, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v31, v31, v12

 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 4
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    vand.vv v26, v25, v8
 ; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 2
 ; LMULMAX1-RV32-NEXT:    vand.vv v25, v25, v11
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    vand.vv v26, v25, v10
-; LMULMAX1-RV32-NEXT:    vsll.vi v26, v26, 1
+; LMULMAX1-RV32-NEXT:    vadd.vv v26, v26, v26
 ; LMULMAX1-RV32-NEXT:    vand.vv v25, v25, v13
 ; LMULMAX1-RV32-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV32-NEXT:    vor.vv v25, v25, v26
 ; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    vse64.v v31, (a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV64-LABEL: bitreverse_v4i64:

 ; LMULMAX1-RV64-NEXT:    addiw a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    slli a1, a1, 12
 ; LMULMAX1-RV64-NEXT:    addi a1, a1, 1365
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v26, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV64-NEXT:    lui s0, 1026731
 ; LMULMAX1-RV64-NEXT:    addiw s0, s0, -1365
 ; LMULMAX1-RV64-NEXT:    slli s0, s0, 12
 ; LMULMAX1-RV64-NEXT:    addi s0, s0, -1365
 ; LMULMAX1-RV64-NEXT:    slli s0, s0, 12
 ; LMULMAX1-RV64-NEXT:    addi s0, s0, -1365
 ; LMULMAX1-RV64-NEXT:    slli s0, s0, 12
 ; LMULMAX1-RV64-NEXT:    addi s0, s0, -1366

 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 4
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v25, a2
 ; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 2
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, a3
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 2
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v27, v25, a1
-; LMULMAX1-RV64-NEXT:    vsll.vi v27, v27, 1
+; LMULMAX1-RV64-NEXT:    vadd.vv v27, v27, v27
 ; LMULMAX1-RV64-NEXT:    vand.vx v25, v25, s0
 ; LMULMAX1-RV64-NEXT:    vsrl.vi v25, v25, 1
 ; LMULMAX1-RV64-NEXT:    vor.vv v25, v25, v27
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    vse64.v v26, (t1)
 ; LMULMAX1-RV64-NEXT:    ld s0, 8(sp) # 8-byte Folded Reload
 ; LMULMAX1-RV64-NEXT:    addi sp, sp, 16
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = load <4 x i64>, <4 x i64>* %y
   %c = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %a)
   store <4 x i64> %c, <4 x i64>* %x
   ret void
 }
 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

; CHECK-NEXT:    ret
   ret void
 }
 
 define void @buildvec_vid_step2_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3) {
 ; CHECK-LABEL: buildvec_vid_step2_add0_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vid.v v25
-; CHECK-NEXT:    vsll.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v25, v25, v25
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    vse8.v v25, (a3)
 ; CHECK-NEXT:    ret
   store <4 x i8> <i8 0, i8 2, i8 4, i8 6>, <4 x i8>* %z0
   store <4 x i8> <i8 undef, i8 2, i8 4, i8 6>, <4 x i8>* %z1
   store <4 x i8> <i8 undef, i8 undef, i8 4, i8 6>, <4 x i8>* %z2
   store <4 x i8> <i8 0, i8 undef, i8 undef, i8 6>, <4 x i8>* %z3
   ret void
 }
 
 define void @buildvec_vid_step2_add1_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3) {
 ; CHECK-LABEL: buildvec_vid_step2_add1_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vid.v v25
-; CHECK-NEXT:    vsll.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v25, v25, v25
 ; CHECK-NEXT:    vadd.vi v25, v25, 1
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    vse8.v v25, (a3)
 ; CHECK-NEXT:    ret
   store <4 x i8> <i8 1, i8 3, i8 5, i8 7>, <4 x i8>* %z0
   store <4 x i8> <i8 undef, i8 3, i8 5, i8 7>, <4 x i8>* %z1
i8>* %z2, <4 x i8>* %z3) {
   ret void
 }
 
 define void @buildvec_vid_stepn2_add0_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3) {
 ; CHECK-LABEL: buildvec_vid_stepn2_add0_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vid.v v25
-; CHECK-NEXT:    vsll.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v25, v25, v25
 ; CHECK-NEXT:    vrsub.vi v25, v25, 0
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    vse8.v v25, (a1)
 ; CHECK-NEXT:    vse8.v v25, (a2)
 ; CHECK-NEXT:    vse8.v v25, (a3)
 ; CHECK-NEXT:    ret
   store <4 x i8> <i8 0, i8 -2, i8 -4, i8 -6>, <4 x i8>* %z0
   store <4 x i8> <i8 undef, i8 -2, i8 -4, i8 -6>, <4 x i8>* %z1
   store <4 x i8> <i8 undef, i8 undef, i8 -4, i8 -6>, <4 x i8>* %z2
   store <4 x i8> <i8 0, i8 undef, i8 undef, i8 -6>, <4 x i8>* %z3
   ret void
 }
 
 define void @buildvec_vid_stepn2_add3_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3) {
 ; CHECK-LABEL: buildvec_vid_stepn2_add3_v4i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vid.v v25
-; CHECK-NEXT:    vsll.vi v25, v25, 1
+; CHECK-NEXT:    vadd.vv v25, v25, v25
 ; CHECK-NEXT:    vrsub.vi v25, v25, 3
 ; CHECK-NEXT:    vse8.v v25, (a0)
 ; CHECK-NEXT:    ret
   store <4 x i8> <i8 3, i8 1, i8 -1, i8 -3>, <4 x i8>* %z0
   ret void
 }
 
 define void @buildvec_vid_stepn3_add3_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3) {

 ; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
 ; RV32-NEXT:    vle32.v v9, (a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: buildvec_vid_step2_add0_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e64, m1, ta, mu
 ; RV64-NEXT:    vid.v v25
-; RV64-NEXT:    vsll.vi v8, v25, 1
+; RV64-NEXT:    vadd.vv v8, v25, v25
 ; RV64-NEXT:    vadd.vi v9, v8, 4
 ; RV64-NEXT:    ret
   ret <4 x i64> <i64 0, i64 2, i64 4, i64 6>
 }
 
 define void @buildvec_no_vid_v4i8(<4 x i8>* %z0, <4 x i8>* %z1, <4 x i8>* %z2, <4 x i8>* %z3, <4 x i8>* %z4, <4 x i8>* %z5) {
 ; RV32-LABEL: buildvec_no_vid_v4i8:
 ; RV32:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

; RV64-NEXT:    ret
   ret <8 x i16> %v
 }
 
 define <8 x i16> @mgather_baseidx_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_v8i8_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_v8i8_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs
   %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
   ret <8 x i16> %v
 }
 
 define <8 x i16> @mgather_baseidx_sext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %eidxs = sext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
   %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
   ret <8 x i16> %v
 }
 
 define <8 x i16> @mgather_baseidx_zext_v8i8_v8i16(i16* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vzext.vf4 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vzext.vf8 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %eidxs = zext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
   %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
   ret <8 x i16> %v
 }
 
 define <8 x i16> @mgather_baseidx_v8i16(i16* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf2 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf4 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs
   %v = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> %ptrs, i32 2, <8 x i1> %m, <8 x i16> %passthru)
   ret <8 x i16> %v
 }
; RV64-NEXT:    ret
   ret <8 x half> %v
 }
 
 define <8 x half> @mgather_baseidx_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_v8i8_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_v8i8_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs
   %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
   ret <8 x half> %v
 }
 
 define <8 x half> @mgather_baseidx_sext_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_sext_v8i8_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_sext_v8i8_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %eidxs = sext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
   %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
   ret <8 x half> %v
 }
 
 define <8 x half> @mgather_baseidx_zext_v8i8_v8f16(half* %base, <8 x i8> %idxs, <8 x i1> %m, <8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_zext_v8i8_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vzext.vf4 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_zext_v8i8_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vzext.vf8 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %eidxs = zext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
   %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
   ret <8 x half> %v
 }
 
 define <8 x half> @mgather_baseidx_v8f16(half* %base, <8 x i16> %idxs, <8 x i1> %m, <8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf2 v26, v8
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV32-NEXT:    vluxei32.v v9, (a0), v26, v0.t
 ; RV32-NEXT:    vmv1r.v v8, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf4 v28, v8
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
 ; RV64-NEXT:    vluxei64.v v9, (a0), v28, v0.t
 ; RV64-NEXT:    vmv1r.v v8, v9
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs
   %v = call <8 x half> @llvm.masked.gather.v8f16.v8p0f16(<8 x half*> %ptrs, i32 2, <8 x i1> %m, <8 x half> %passthru)
   ret <8 x half> %v
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

; RV64-NEXT:    ret
   ret void
 }
 
 define void @mscatter_baseidx_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_v8i8_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_v8i8_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i8> %idxs
   call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_sext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
   call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_zext_v8i8_v8i16(<8 x i16> %val, i16* %base, <8 x i8> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vzext.vf4 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vzext.vf8 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %eidxs
   call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_v8i16(<8 x i16> %val, i16* %base, <8 x i16> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf2 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf4 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <8 x i16> %idxs
   call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> %val, <8 x i16*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
; RV64-NEXT:    ret
   ret void
 }
 
 define void @mscatter_baseidx_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_v8i8_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_v8i8_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <8 x i8> %idxs
   call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_sext_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_sext_v8i8_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf4 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_sext_v8i8_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf8 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
   call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_zext_v8i8_v8f16(<8 x half> %val, half* %base, <8 x i8> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_zext_v8i8_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vzext.vf4 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_zext_v8i8_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vzext.vf8 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <8 x i8> %idxs to <8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %eidxs
   call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_v8f16(<8 x half> %val, half* %base, <8 x i16> %idxs, <8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_v8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, mu
 ; RV32-NEXT:    vsext.vf2 v26, v9
-; RV32-NEXT:    vsll.vi v26, v26, 1
+; RV32-NEXT:    vadd.vv v26, v26, v26
 ; RV32-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v26, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_v8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, mu
 ; RV64-NEXT:    vsext.vf4 v28, v9
-; RV64-NEXT:    vsll.vi v28, v28, 1
+; RV64-NEXT:    vadd.vv v28, v28, v28
 ; RV64-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v28, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <8 x i16> %idxs
   call void @llvm.masked.scatter.v8f16.v8p0f16(<8 x half> %val, <8 x half*> %ptrs, i32 2, <8 x i1> %m)
   ret void
 }
 

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

; RV64-NEXT:    ret
   ret <vscale x 8 x i16> %v
 }
 
 define <vscale x 8 x i16> @mgather_baseidx_nxv8i8_nxv8i16(i16* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_nxv8i8_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i8> %idxs
   %v = call <vscale x 8 x i16> @llvm.masked.gather.nxv8i16.nxv8p0i16(<vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru)
   ret <vscale x 8 x i16> %v
 }
 
 define <vscale x 8 x i16> @mgather_baseidx_sext_nxv8i8_nxv8i16(i16* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_sext_nxv8i8_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i16> %eidxs
   %v = call <vscale x 8 x i16> @llvm.masked.gather.nxv8i16.nxv8p0i16(<vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru)
   ret <vscale x 8 x i16> %v
 }
 
 define <vscale x 8 x i16> @mgather_baseidx_zext_nxv8i8_nxv8i16(i16* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vzext.vf4 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_zext_nxv8i8_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vzext.vf8 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i16> %eidxs
   %v = call <vscale x 8 x i16> @llvm.masked.gather.nxv8i16.nxv8p0i16(<vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru)
   ret <vscale x 8 x i16> %v
 }
 
 define <vscale x 8 x i16> @mgather_baseidx_nxv8i16(i16* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru) {
 ; RV32-LABEL: mgather_baseidx_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf2 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i16> %idxs
   %v = call <vscale x 8 x i16> @llvm.masked.gather.nxv8i16.nxv8p0i16(<vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x i16> %passthru)
   ret <vscale x 8 x i16> %v
 }
; RV64-NEXT:    ret
   ret <vscale x 8 x half> %v
 }
 
 define <vscale x 8 x half> @mgather_baseidx_nxv8i8_nxv8f16(half* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_nxv8i8_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_nxv8i8_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i8> %idxs
   %v = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16.nxv8p0f16(<vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru)
   ret <vscale x 8 x half> %v
 }
 
 define <vscale x 8 x half> @mgather_baseidx_sext_nxv8i8_nxv8f16(half* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_sext_nxv8i8_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i16> %eidxs
   %v = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16.nxv8p0f16(<vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru)
   ret <vscale x 8 x half> %v
 }
 
 define <vscale x 8 x half> @mgather_baseidx_zext_nxv8i8_nxv8f16(half* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vzext.vf4 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_zext_nxv8i8_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vzext.vf8 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i16> %eidxs
   %v = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16.nxv8p0f16(<vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru)
   ret <vscale x 8 x half> %v
 }
 
 define <vscale x 8 x half> @mgather_baseidx_nxv8f16(half* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru) {
 ; RV32-LABEL: mgather_baseidx_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf2 v28, v8
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV32-NEXT:    vluxei32.v v10, (a0), v28, v0.t
 ; RV32-NEXT:    vmv2r.v v8, v10
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mgather_baseidx_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v16, v8
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, tu, mu
 ; RV64-NEXT:    vluxei64.v v10, (a0), v16, v0.t
 ; RV64-NEXT:    vmv2r.v v8, v10
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i16> %idxs
   %v = call <vscale x 8 x half> @llvm.masked.gather.nxv8f16.nxv8p0f16(<vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m, <vscale x 8 x half> %passthru)
   ret <vscale x 8 x half> %v
 }

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

; RV64-NEXT:    ret
   ret void
 }
 
 define void @mscatter_baseidx_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i8> %idxs
   call void @llvm.masked.scatter.nxv8i16.nxv8p0i16(<vscale x 8 x i16> %val, <vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_sext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i16> %eidxs
   call void @llvm.masked.scatter.nxv8i16.nxv8p0i16(<vscale x 8 x i16> %val, <vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_zext_nxv8i8_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vzext.vf4 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vzext.vf8 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i16> %eidxs
   call void @llvm.masked.scatter.nxv8i16.nxv8p0i16(<vscale x 8 x i16> %val, <vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_nxv8i16(<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_nxv8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf2 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_nxv8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds i16, i16* %base, <vscale x 8 x i16> %idxs
   call void @llvm.masked.scatter.nxv8i16.nxv8p0i16(<vscale x 8 x i16> %val, <vscale x 8 x i16*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
; RV64-NEXT:    ret
   ret void
 }
 
 define void @mscatter_baseidx_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_nxv8i8_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_nxv8i8_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i8> %idxs
   call void @llvm.masked.scatter.nxv8f16.nxv8p0f16(<vscale x 8 x half> %val, <vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_sext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf4 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_sext_nxv8i8_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf8 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %eidxs = sext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i16> %eidxs
   call void @llvm.masked.scatter.nxv8f16.nxv8p0f16(<vscale x 8 x half> %val, <vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_zext_nxv8i8_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i8> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vzext.vf4 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_zext_nxv8i8_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vzext.vf8 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %eidxs = zext <vscale x 8 x i8> %idxs to <vscale x 8 x i16>
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i16> %eidxs
   call void @llvm.masked.scatter.nxv8f16.nxv8p0f16(<vscale x 8 x half> %val, <vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 
 define void @mscatter_baseidx_nxv8f16(<vscale x 8 x half> %val, half* %base, <vscale x 8 x i16> %idxs, <vscale x 8 x i1> %m) {
 ; RV32-LABEL: mscatter_baseidx_nxv8f16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
 ; RV32-NEXT:    vsext.vf2 v28, v10
-; RV32-NEXT:    vsll.vi v28, v28, 1
+; RV32-NEXT:    vadd.vv v28, v28, v28
 ; RV32-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV32-NEXT:    vsoxei32.v v8, (a0), v28, v0.t
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mscatter_baseidx_nxv8f16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64-NEXT:    vsext.vf4 v16, v10
-; RV64-NEXT:    vsll.vi v16, v16, 1
+; RV64-NEXT:    vadd.vv v16, v16, v16
 ; RV64-NEXT:    vsetvli zero, zero, e16, m2, ta, mu
 ; RV64-NEXT:    vsoxei64.v v8, (a0), v16, v0.t
 ; RV64-NEXT:    ret
   %ptrs = getelementptr inbounds half, half* %base, <vscale x 8 x i16> %idxs
   call void @llvm.masked.scatter.nxv8f16.nxv8p0f16(<vscale x 8 x half> %val, <vscale x 8 x half*> %ptrs, i32 2, <vscale x 8 x i1> %m)
   ret void
 }
 

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = shl <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
+define <vscale x 1 x i64> @vshl_vx_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
 define <vscale x 2 x i64> @vshl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = shl <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
+define <vscale x 2 x i64> @vshl_vx_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
 define <vscale x 4 x i64> @vshl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = shl <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
+define <vscale x 4 x i64> @vshl_vx_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
 define <vscale x 8 x i64> @vshl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv8i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = shl <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i64> @vshl_vx_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}

llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = shl <vscale x 1 x i64> %va, %splat
   ret <vscale x 1 x i64> %vc
 }
 
+define <vscale x 1 x i64> @vshl_vx_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
 define <vscale x 2 x i64> @vshl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = shl <vscale x 2 x i64> %va, %splat
   ret <vscale x 2 x i64> %vc
 }
 
+define <vscale x 2 x i64> @vshl_vx_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
 define <vscale x 4 x i64> @vshl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = shl <vscale x 4 x i64> %va, %splat
   ret <vscale x 4 x i64> %vc
 }
 
+define <vscale x 4 x i64> @vshl_vx_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
 define <vscale x 8 x i64> @vshl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
 ; CHECK-LABEL: vshl_vx_nxv8i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer

 ; CHECK-NEXT:    vsll.vx v8, v8, a0
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = shl <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i64> @vshl_vx_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV32MV-NEXT:    addi a1, sp, 8
 ; RV32MV-NEXT:    vle16.v v25, (a1)
 ; RV32MV-NEXT:    lui a1, %hi(.LCPI4_0)
 ; RV32MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; RV32MV-NEXT:    vle16.v v26, (a1)
 ; RV32MV-NEXT:    vid.v v27
 ; RV32MV-NEXT:    vsub.vv v25, v25, v27
 ; RV32MV-NEXT:    vmul.vv v25, v25, v26
-; RV32MV-NEXT:    vsll.vi v26, v25, 1
+; RV32MV-NEXT:    vadd.vv v26, v25, v25
 ; RV32MV-NEXT:    addi a1, zero, 9
 ; RV32MV-NEXT:    vmv.v.i v27, 10
 ; RV32MV-NEXT:    vsetvli zero, zero, e16, mf2, tu, mu
 ; RV32MV-NEXT:    vmv.s.x v27, a1
 ; RV32MV-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
 ; RV32MV-NEXT:    vsll.vv v26, v26, v27
 ; RV32MV-NEXT:    addi a1, zero, 2047
 ; RV32MV-NEXT:    vand.vx v25, v25, a1

 ; RV64MV-NEXT:    addi a1, sp, 8
 ; RV64MV-NEXT:    vle16.v v25, (a1)
 ; RV64MV-NEXT:    lui a1, %hi(.LCPI4_0)
 ; RV64MV-NEXT:    addi a1, a1, %lo(.LCPI4_0)
 ; RV64MV-NEXT:    vle16.v v26, (a1)
 ; RV64MV-NEXT:    vid.v v27
 ; RV64MV-NEXT:    vsub.vv v25, v25, v27
 ; RV64MV-NEXT:    vmul.vv v25, v25, v26
-; RV64MV-NEXT:    vsll.vi v26, v25, 1
+; RV64MV-NEXT:    vadd.vv v26, v25, v25
 ; RV64MV-NEXT:    addi a1, zero, 9
 ; RV64MV-NEXT:    vmv.v.i v27, 10
 ; RV64MV-NEXT:    vsetvli zero, zero, e16, mf2, tu, mu
 ; RV64MV-NEXT:    vmv.s.x v27, a1
 ; RV64MV-NEXT:    vsetvli zero, zero, e16, mf2, ta, mu
 ; RV64MV-NEXT:    vsll.vv v26, v26, v27
 ; RV64MV-NEXT:    addi a1, zero, 2047
 ; RV64MV-NEXT:    vand.vx v25, v25, a1