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Differential D117466

[RISCV] Add patterns for vector widening floating-point add/subtract instructions
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Authored by jacquesguan on Jan 17 2022, 4:10 AM.

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asb
luismarques
frasercrmck
HsiangKai
khchen
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rGc29d6c410e76: [RISCV] Add patterns for vector widening floating-point add/subtract…
Summary

Add patterns for Vector Widening Floating-Point Add/Subtract Instructions

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jacquesguan created this revision.Jan 17 2022, 4:10 AM
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Harbormaster completed remote builds in B143754: Diff 400488.Jan 17 2022, 4:59 AM
craig.topper accepted this revision.Jan 17 2022, 11:44 AM

LGTM

This revision is now accepted and ready to land.Jan 17 2022, 11:44 AM
This revision was landed with ongoing or failed builds.Jan 17 2022, 6:51 PM
Closed by commit rGc29d6c410e76: [RISCV] Add patterns for vector widening floating-point add/subtract… (authored by jacquesguan). · Explain Why
This revision was automatically updated to reflect the committed changes.
jacquesguan added a commit: rGc29d6c410e76: [RISCV] Add patterns for vector widening floating-point add/subtract….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
5 lines
39 lines
test/
CodeGen/
RISCV/
rvv/
217 lines
217 lines

Diff 400691

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 1,040 Lines • ▼ Show 20 Lines
def zext_oneuse : PatFrag<(ops node:$A), (zext node:$A), [{ def zext_oneuse : PatFrag<(ops node:$A), (zext node:$A), [{
return N->hasOneUse(); return N->hasOneUse();
}]>; }]>;
def anyext_oneuse : PatFrag<(ops node:$A), (anyext node:$A), [{ def anyext_oneuse : PatFrag<(ops node:$A), (anyext node:$A), [{
return N->hasOneUse(); return N->hasOneUse();
}]>; }]>;
def fpext_oneuse : PatFrag<(ops node:$A),
(any_fpextend node:$A), [{
return N->hasOneUse();
}]>;
/// Simple arithmetic operations /// Simple arithmetic operations
def : PatGprGpr<add, ADD>; def : PatGprGpr<add, ADD>;
def : PatGprSimm12<add, ADDI>; def : PatGprSimm12<add, ADDI>;
def : PatGprGpr<sub, SUB>; def : PatGprGpr<sub, SUB>;
def : PatGprGpr<or, OR>; def : PatGprGpr<or, OR>;
def : PatGprSimm12<or, ORI>; def : PatGprSimm12<or, ORI>;
def : PatGprGpr<and, AND>; def : PatGprGpr<and, AND>;
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llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 407 Lines • ▼ Show 20 Lines def : Pat<
(vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))), (vti.Wti.Vector (extop2 (vti.Vti.Vector vti.Vti.RegClass:$rs2))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rd, GPR:$rs1, vti.Vti.RegClass:$rs2, vti.Wti.RegClass:$rd, GPR:$rs1, vti.Vti.RegClass:$rs2,
vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC vti.Vti.AVL, vti.Vti.Log2SEW, TAIL_AGNOSTIC
)>; )>;
} }
} }
multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
foreach vti = AllWidenableFloatVectors in {
def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatPat vti.Vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
}
}
multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
foreach vti = AllWidenableFloatVectors in {
def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatPat vti.Vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
vti.Vti.AVL, vti.Vti.Log2SEW)>;
}
}
multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, string instruction_name> {
defm : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>;
defm : VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
// 7.4. Vector Unit-Stride Instructions // 7.4. Vector Unit-Stride Instructions
foreach vti = !listconcat(FractionalGroupIntegerVectors, foreach vti = !listconcat(FractionalGroupIntegerVectors,
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Lines
let Predicates = [HasVInstructionsAnyF] in { let Predicates = [HasVInstructionsAnyF] in {
// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">; defm : VPatBinaryFPSDNode_VV_VF<fadd, "PseudoVFADD">;
defm : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">; defm : VPatBinaryFPSDNode_VV_VF<fsub, "PseudoVFSUB">;
defm : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">; defm : VPatBinaryFPSDNode_R_VF<fsub, "PseudoVFRSUB">;
// 14.3. Vector Widening Floating-Point Add/Subtract Instructions
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fadd, "PseudoVFWADD">;
defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF<fsub, "PseudoVFWSUB">;
// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions // 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">; defm : VPatBinaryFPSDNode_VV_VF<fmul, "PseudoVFMUL">;
defm : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">; defm : VPatBinaryFPSDNode_VV_VF<fdiv, "PseudoVFDIV">;
defm : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">; defm : VPatBinaryFPSDNode_R_VF<fdiv, "PseudoVFRDIV">;
// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. // 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions.
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
// NOTE: We choose VFMADD because it has the most commuting freedom. So it // NOTE: We choose VFMADD because it has the most commuting freedom. So it
▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd-sdnode.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x double> @vfwadd_vv_nxv1f64(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwadd.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%ve = fadd <vscale x 1 x double> %vc, %vd
ret <vscale x 1 x double> %ve
}
define <vscale x 1 x double> @vfwadd_vf_nxv1f64(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfwadd_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwadd.vf v9, v8, fa0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
%ve = fadd <vscale x 1 x double> %vc, %vd
ret <vscale x 1 x double> %ve
}
define <vscale x 1 x double> @vfwadd_wv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwadd.wv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%vd = fadd <vscale x 1 x double> %va, %vc
ret <vscale x 1 x double> %vd
}
define <vscale x 1 x double> @vfwadd_wf_nxv1f64(<vscale x 1 x double> %va, float %b) {
; CHECK-LABEL: vfwadd_wf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwadd.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
%vd = fadd <vscale x 1 x double> %va, %vc
ret <vscale x 1 x double> %vd
}
define <vscale x 2 x double> @vfwadd_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwadd.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%ve = fadd <vscale x 2 x double> %vc, %vd
ret <vscale x 2 x double> %ve
}
define <vscale x 2 x double> @vfwadd_vf_nxv2f64(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfwadd_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwadd.vf v10, v8, fa0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
%ve = fadd <vscale x 2 x double> %vc, %vd
ret <vscale x 2 x double> %ve
}
define <vscale x 2 x double> @vfwadd_wv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwadd.wv v12, v8, v10
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%vd = fadd <vscale x 2 x double> %va, %vc
ret <vscale x 2 x double> %vd
}
define <vscale x 2 x double> @vfwadd_wf_nxv2f64(<vscale x 2 x double> %va, float %b) {
; CHECK-LABEL: vfwadd_wf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwadd.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
%vd = fadd <vscale x 2 x double> %va, %vc
ret <vscale x 2 x double> %vd
}
define <vscale x 4 x double> @vfwadd_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwadd.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%ve = fadd <vscale x 4 x double> %vc, %vd
ret <vscale x 4 x double> %ve
}
define <vscale x 4 x double> @vfwadd_vf_nxv4f64(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfwadd_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwadd.vf v12, v8, fa0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
%ve = fadd <vscale x 4 x double> %vc, %vd
ret <vscale x 4 x double> %ve
}
define <vscale x 4 x double> @vfwadd_wv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwadd.wv v16, v8, v12
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%vd = fadd <vscale x 4 x double> %va, %vc
ret <vscale x 4 x double> %vd
}
define <vscale x 4 x double> @vfwadd_wf_nxv4f64(<vscale x 4 x double> %va, float %b) {
; CHECK-LABEL: vfwadd_wf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwadd.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
%vd = fadd <vscale x 4 x double> %va, %vc
ret <vscale x 4 x double> %vd
}
define <vscale x 8 x double> @vfwadd_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwadd_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwadd.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%ve = fadd <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
define <vscale x 8 x double> @vfwadd_vf_nxv8f64(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfwadd_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwadd.vf v16, v8, fa0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
%ve = fadd <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
define <vscale x 8 x double> @vfwadd_wv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwadd_wv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwadd.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%vd = fadd <vscale x 8 x double> %va, %vc
ret <vscale x 8 x double> %vd
}
define <vscale x 8 x double> @vfwadd_wf_nxv8f64(<vscale x 8 x double> %va, float %b) {
; CHECK-LABEL: vfwadd_wf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwadd.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
%vd = fadd <vscale x 8 x double> %va, %vc
ret <vscale x 8 x double> %vd
}

llvm/test/CodeGen/RISCV/rvv/vfwsub-sdnode.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x double> @vfwsub_vv_nxv1f64(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwsub.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%ve = fsub <vscale x 1 x double> %vc, %vd
ret <vscale x 1 x double> %ve
}
define <vscale x 1 x double> @vfwsub_vf_nxv1f64(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfwsub_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwsub.vf v9, v8, fa0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
%ve = fsub <vscale x 1 x double> %vc, %vd
ret <vscale x 1 x double> %ve
}
define <vscale x 1 x double> @vfwsub_wv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwsub.wv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%vd = fsub <vscale x 1 x double> %va, %vc
ret <vscale x 1 x double> %vd
}
define <vscale x 1 x double> @vfwsub_wf_nxv1f64(<vscale x 1 x double> %va, float %b) {
; CHECK-LABEL: vfwsub_wf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> undef, <vscale x 1 x i32> zeroinitializer
%vc = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
%vd = fsub <vscale x 1 x double> %va, %vc
ret <vscale x 1 x double> %vd
}
define <vscale x 2 x double> @vfwsub_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwsub.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%ve = fsub <vscale x 2 x double> %vc, %vd
ret <vscale x 2 x double> %ve
}
define <vscale x 2 x double> @vfwsub_vf_nxv2f64(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfwsub_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwsub.vf v10, v8, fa0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
%ve = fsub <vscale x 2 x double> %vc, %vd
ret <vscale x 2 x double> %ve
}
define <vscale x 2 x double> @vfwsub_wv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwsub.wv v12, v8, v10
; CHECK-NEXT: vmv2r.v v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%vd = fsub <vscale x 2 x double> %va, %vc
ret <vscale x 2 x double> %vd
}
define <vscale x 2 x double> @vfwsub_wf_nxv2f64(<vscale x 2 x double> %va, float %b) {
; CHECK-LABEL: vfwsub_wf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer
%vc = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
%vd = fsub <vscale x 2 x double> %va, %vc
ret <vscale x 2 x double> %vd
}
define <vscale x 4 x double> @vfwsub_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwsub.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%ve = fsub <vscale x 4 x double> %vc, %vd
ret <vscale x 4 x double> %ve
}
define <vscale x 4 x double> @vfwsub_vf_nxv4f64(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfwsub_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwsub.vf v12, v8, fa0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
%ve = fsub <vscale x 4 x double> %vc, %vd
ret <vscale x 4 x double> %ve
}
define <vscale x 4 x double> @vfwsub_wv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwsub.wv v16, v8, v12
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%vd = fsub <vscale x 4 x double> %va, %vc
ret <vscale x 4 x double> %vd
}
define <vscale x 4 x double> @vfwsub_wf_nxv4f64(<vscale x 4 x double> %va, float %b) {
; CHECK-LABEL: vfwsub_wf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
%vc = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
%vd = fsub <vscale x 4 x double> %va, %vc
ret <vscale x 4 x double> %vd
}
define <vscale x 8 x double> @vfwsub_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwsub_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwsub.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%ve = fsub <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
define <vscale x 8 x double> @vfwsub_vf_nxv8f64(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfwsub_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwsub.vf v16, v8, fa0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
%ve = fsub <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
define <vscale x 8 x double> @vfwsub_wv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwsub_wv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%vd = fsub <vscale x 8 x double> %va, %vc
ret <vscale x 8 x double> %vd
}
define <vscale x 8 x double> @vfwsub_wf_nxv8f64(<vscale x 8 x double> %va, float %b) {
; CHECK-LABEL: vfwsub_wf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfwsub.wf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
%vd = fsub <vscale x 8 x double> %va, %vc
ret <vscale x 8 x double> %vd
}