[mlir] Drop the leading space when printing regions

[Mogball]

Summary

The leading space that is always printed at the beginning of regions is not consistent with other parts of the printing API. Moreover, this leading space can lead to undesirable assembly formats:

attr-dict-with-keyword $region

Prints as:

// Two spaces between `}` and `{`
attributes {foo}  { ... }

Moreover, the leading space results in the odd generic op format:

"test.op"() ( {...}) : () -> ()

[mehdi_amini]

LGTM, but please wait for River to double check that this does not induce new ambiguity.

Also the two examples you give in your description could be handled in the respective places (declarative ASM and generic printer) instead, but I agree that this API contract is more in-line with the other APIs here.

[Mogball]

Fix flang

flang/lib/Optimizer/Dialect/FIROps.cpp

 static void print(mlir::OpAsmPrinter &p, fir::DispatchTableOp &op) {
   auto tableName =
       op.getOperation()
           ->getAttrOfType<StringAttr>(mlir::SymbolTable::getSymbolAttrName())
           .getValue();
   p << " @" << tableName;
 
   Region &body = op.getOperation()->getRegion(0);
-  if (!body.empty())
+  if (!body.empty()) {
+    p << ' ';
     p.printRegion(body, /*printEntryBlockArgs=*/false,
                   /*printBlockTerminators=*/false);
   }
+}
 
 static mlir::LogicalResult verify(fir::DispatchTableOp &op) {
   for (auto &op : op.getBlock())
     if (!(isa<fir::DTEntryOp>(op) || isa<fir::FirEndOp>(op)))
       return op.emitOpError("dispatch table must contain dt_entry");
   return mlir::success();
 }
 
static void print(mlir::OpAsmPrinter &p, fir::GlobalOp &op) {
   p << ' ';
   p.printAttributeWithoutType(op.getSymrefAttr());
   if (auto val = op.getValueOrNull())
     p << '(' << val << ')';
   if (op.getOperation()->getAttr(fir::GlobalOp::getConstantAttrNameStr()))
     p << " constant";
   p << " : ";
   p.printType(op.getType());
-  if (op.hasInitializationBody())
+  if (op.hasInitializationBody()) {
+    p << ' ';
     p.printRegion(op.getOperation()->getRegion(0),
                   /*printEntryBlockArgs=*/false,
                   /*printBlockTerminators=*/true);
   }
+}
 
 void fir::GlobalOp::appendInitialValue(mlir::Operation *op) {
   getBlock().getOperations().push_back(op);
 }
 
 void fir::GlobalOp::build(mlir::OpBuilder &builder, OperationState &result,
                           StringRef name, bool isConstant, Type type,
                           Attribute initialVal, StringAttr linkage,
if (regionArgs.size() > 1) {
     llvm::interleaveComma(
         llvm::drop_begin(op.getResultTypes(), op.finalValue() ? 0 : 1), p);
     p << ")";
   } else if (op.finalValue()) {
     p << " -> (" << op.getResultTypes() << ')';
   }
   p.printOptionalAttrDictWithKeyword(op->getAttrs(),
                                      {op.getFinalValueAttrNameStr()});
+  p << ' ';
   p.printRegion(op.region(), /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/true);
 }
 
 mlir::Region &fir::IterWhileOp::getLoopBody() { return region(); }
 
 bool fir::IterWhileOp::isDefinedOutsideOfLoop(mlir::Value value) {
   return !region().isAncestor(value.getParentRegion());
if (op.hasIterOperands()) {
     p << ") -> (" << op.getResultTypes() << ')';
     printBlockTerminators = true;
   } else if (op.finalValue()) {
     p << " -> " << op.getResultTypes();
     printBlockTerminators = true;
   }
   p.printOptionalAttrDictWithKeyword(op->getAttrs(),
                                      {"unordered", "finalValue"});
+  p << ' ';
   p.printRegion(op.region(), /*printEntryBlockArgs=*/false,
                 printBlockTerminators);
 }
 
 mlir::Region &fir::DoLoopOp::getLoopBody() { return region(); }
 
 bool fir::DoLoopOp::isDefinedOutsideOfLoop(mlir::Value value) {
   return !region().isAncestor(value.getParentRegion());

 
 static void print(mlir::OpAsmPrinter &p, fir::IfOp op) {
   bool printBlockTerminators = false;
   p << ' ' << op.condition();
   if (!op.results().empty()) {
     p << " -> (" << op.getResultTypes() << ')';
     printBlockTerminators = true;
   }
+  p << ' ';
   p.printRegion(op.thenRegion(), /*printEntryBlockArgs=*/false,
                 printBlockTerminators);
 
   // Print the 'else' regions if it exists and has a block.
   auto &otherReg = op.elseRegion();
   if (!otherReg.empty()) {
-    p << " else";
+    p << " else ";
     p.printRegion(otherReg, /*printEntryBlockArgs=*/false,
                   printBlockTerminators);
   }
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 void fir::IfOp::resultToSourceOps(llvm::SmallVectorImpl<mlir::Value> &results,
                                   unsigned resultNum) {

mlir/lib/Dialect/Affine/IR/AffineOps.cpp

if (op.getNumIterOperands() > 0) {
 
     llvm::interleaveComma(llvm::zip(regionArgs, operands), p, [&](auto it) {
       p << std::get<0>(it) << " = " << std::get<1>(it);
     });
     p << ") -> (" << op.getResultTypes() << ")";
     printBlockTerminators = true;
   }
 
+  p << ' ';
   p.printRegion(op.region(),
                 /*printEntryBlockArgs=*/false, printBlockTerminators);
   p.printOptionalAttrDict(op->getAttrs(),
                           /*elidedAttrs=*/{op.getLowerBoundAttrName(),
                                            op.getUpperBoundAttrName(),
                                            op.getStepAttrName()});
 }
 

 
 static void print(OpAsmPrinter &p, AffineIfOp op) {
   auto conditionAttr =
       op->getAttrOfType<IntegerSetAttr>(op.getConditionAttrName());
   p << " " << conditionAttr;
   printDimAndSymbolList(op.operand_begin(), op.operand_end(),
                         conditionAttr.getValue().getNumDims(), p);
   p.printOptionalArrowTypeList(op.getResultTypes());
+  p << ' ';
   p.printRegion(op.thenRegion(),
                 /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/op.getNumResults());
 
   // Print the 'else' regions if it has any blocks.
   auto &elseRegion = op.elseRegion();
   if (!elseRegion.empty()) {
-    p << " else";
+    p << " else ";
     p.printRegion(elseRegion,
                   /*printEntryBlockArgs=*/false,
                   /*printBlockTerminators=*/op.getNumResults());
   }
 
   // Print the attribute list.
   p.printOptionalAttrDict(op->getAttrs(),
                           /*elidedAttrs=*/op.getConditionAttrName());
if (op.getNumResults()) {
     llvm::interleaveComma(op.reductions(), p, [&](auto &attr) {
       arith::AtomicRMWKind sym = *arith::symbolizeAtomicRMWKind(
           attr.template cast<IntegerAttr>().getInt());
       p << "\"" << arith::stringifyAtomicRMWKind(sym) << "\"";
     });
     p << ") -> (" << op.getResultTypes() << ")";
   }
 
+  p << ' ';
   p.printRegion(op.region(), /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/op.getNumResults());
   p.printOptionalAttrDict(
       op->getAttrs(),
       /*elidedAttrs=*/{AffineParallelOp::getReductionsAttrName(),
                        AffineParallelOp::getLowerBoundsMapAttrName(),
                        AffineParallelOp::getLowerBoundsGroupsAttrName(),
                        AffineParallelOp::getUpperBoundsMapAttrName(),

mlir/lib/Dialect/Async/IR/Async.cpp

if (!op.operands().empty()) {
     });
     p << ")";
   }
 
   // -> (!async.value<!return.type>, ...)
   p.printOptionalArrowTypeList(llvm::drop_begin(op.getResultTypes()));
   p.printOptionalAttrDictWithKeyword(op->getAttrs(),
                                      {kOperandSegmentSizesAttr});
+  p << ' ';
   p.printRegion(op.body(), /*printEntryBlockArgs=*/false);
 }
 
 static ParseResult parseExecuteOp(OpAsmParser &parser, OperationState &result) {
   MLIRContext *ctx = result.getContext();
 
   // Sizes of parsed variadic operands, will be updated below after parsing.
   int32_t numDependencies = 0;

mlir/lib/Dialect/GPU/IR/GPUDialect.cpp

printSizeAssignment(p, op.getGridSize(), op.getGridSizeOperandValues(),
                       op.getBlockIds());
   p << ' ' << op.getThreadsKeyword();
   printSizeAssignment(p, op.getBlockSize(), op.getBlockSizeOperandValues(),
                       op.getThreadIds());
   if (op.dynamicSharedMemorySize())
     p << ' ' << op.getDynamicSharedMemorySizeKeyword() << ' '
       << op.dynamicSharedMemorySize();
 
+  p << ' ';
   p.printRegion(op.body(), /*printEntryBlockArgs=*/false);
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 // Parse the size assignment blocks for blocks and threads.  These have the form
 //   (%region_arg, %region_arg, %region_arg) in
 //   (%region_arg = %operand, %region_arg = %operand, %region_arg = %operand)
 // where %region_arg are percent-identifiers for the region arguments to be
static void printGPUFuncOp(OpAsmPrinter &p, GPUFuncOp op) {
   printAttributions(p, op.getPrivateKeyword(), op.getPrivateAttributions());
   if (op.isKernel())
     p << ' ' << op.getKernelKeyword();
 
   function_like_impl::printFunctionAttributes(
       p, op.getOperation(), type.getNumInputs(), type.getNumResults(),
       {op.getNumWorkgroupAttributionsAttrName(),
        GPUDialect::getKernelFuncAttrName()});
+  p << ' ';
   p.printRegion(op.getBody(), /*printEntryBlockArgs=*/false);
 }
 
 /// Hook for FunctionLike verifier.
 LogicalResult GPUFuncOp::verifyType() {
   Type type = getTypeAttr().getValue();
   if (!type.isa<FunctionType>())
     return emitOpError("requires '" + getTypeAttrName() +
static ParseResult parseGPUModuleOp(OpAsmParser &parser,
   return success();
 }
 
 static void print(OpAsmPrinter &p, GPUModuleOp op) {
   p << ' ';
   p.printSymbolName(op.getName());
   p.printOptionalAttrDictWithKeyword(op->getAttrs(),
                                      {SymbolTable::getSymbolAttrName()});
+  p << ' ';
   p.printRegion(op->getRegion(0), /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/false);
 }
 
 //===----------------------------------------------------------------------===//
 // GPUMemcpyOp
 //===----------------------------------------------------------------------===//
 

mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp

p.printOptionalAttrDict(op->getAttrs(),
                            getUnnamedAddrAttrName()});
 
   // Print the trailing type unless it's a string global.
   if (op.getValueOrNull().dyn_cast_or_null<StringAttr>())
     return;
   p << " : " << op.getType();
 
   Region &initializer = op.getInitializerRegion();
-  if (!initializer.empty())
+  if (!initializer.empty()) {
+    p << ' ';
     p.printRegion(initializer, /*printEntryBlockArgs=*/false);
   }
+}
 
 // Parses one of the keywords provided in the list `keywords` and returns the
 // position of the parsed keyword in the list. If none of the keywords from the
 // list is parsed, returns -1.
 static int parseOptionalKeywordAlternative(OpAsmParser &parser,
                                            ArrayRef<StringRef> keywords) {
   for (const auto &en : llvm::enumerate(keywords)) {
     if (succeeded(parser.parseOptionalKeyword(en.value())))
static void printLLVMFuncOp(OpAsmPrinter &p, LLVMFuncOp op) {
 
   function_like_impl::printFunctionSignature(p, op, argTypes, op.isVarArg(),
                                              resTypes);
   function_like_impl::printFunctionAttributes(
       p, op, argTypes.size(), resTypes.size(), {getLinkageAttrName()});
 
   // Print the body if this is not an external function.
   Region &body = op.getBody();
-  if (!body.empty())
+  if (!body.empty()) {
+    p << ' ';
     p.printRegion(body, /*printEntryBlockArgs=*/false,
                   /*printBlockTerminators=*/true);
   }
+}
 
 // Hook for OpTrait::FunctionLike, called after verifying that the 'type'
 // attribute is present.  This can check for preconditions of the
 // getNumArguments hook not failing.
 LogicalResult LLVMFuncOp::verifyType() {
   auto llvmType = getTypeAttr().getValue().dyn_cast_or_null<LLVMFunctionType>();
   if (!llvmType)
     return emitOpError("requires '" + getTypeAttrName() +

mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp

if ((hasExtraAttrs = !genericAttrNamesSet.contains(n.getName().strref())))
       break;
   }
   if (hasExtraAttrs) {
     p << " attrs = ";
     p.printOptionalAttrDict(op->getAttrs(), /*elidedAttrs=*/genericAttrNames);
   }
 
   // Print region.
-  if (!op.region().empty())
+  if (!op.region().empty()) {
+    p << ' ';
     p.printRegion(op.region());
+  }
 
   // Print results.
   printNamedStructuredOpResults(p, op.result_tensors().getTypes());
 }
 
 static ParseResult parseGenericOp(OpAsmParser &parser, OperationState &result) {
   DictionaryAttr dictAttr;
   // Parse the core linalg traits that must check into a dictAttr.
llvm::interleaveComma(llvm::zip(op.getRegionOutputArgs(), op.outputs()), p,
                           });
     p << ")";
   }
 
   if (llvm::any_of(op.iterator_types(), [](Attribute attr) {
         return attr.cast<StringAttr>().getValue() !=
                getParallelIteratorTypeName();
       }))
-    p << " iterators" << op.iterator_types() << "";
+    p << " iterators" << op.iterator_types();
 
   if (op.distribution_types().hasValue())
-    p << " distribution" << op.distribution_types().getValue() << "";
+    p << " distribution" << op.distribution_types().getValue();
 
+  p << ' ';
   p.printRegion(op.region(), /*printEntryBlockArgs=*/false);
   p.printOptionalAttrDict(
       op->getAttrs(), /*elidedAttrs=*/{TiledLoopOp::getOperandSegmentSizeAttr(),
                                        getIteratorTypesAttrName(),
                                        getDistributionTypesAttrName()});
 }
 
 static ParseResult parseTiledLoopOp(OpAsmParser &parser,

mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp

 
 //===----------------------------------------------------------------------===//
 // AllocaScopeOp
 //===----------------------------------------------------------------------===//
 
 static void print(OpAsmPrinter &p, AllocaScopeOp &op) {
   bool printBlockTerminators = false;
 
-  p << " ";
+  p << ' ';
   if (!op.results().empty()) {
     p << " -> (" << op.getResultTypes() << ")";
     printBlockTerminators = true;
   }
+  p << ' ';
   p.printRegion(op.bodyRegion(),
                 /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/printBlockTerminators);
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 static ParseResult parseAllocaScopeOp(OpAsmParser &parser,
                                       OperationState &result) {

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

static void print(OpAsmPrinter &printer, ParallelOp &op) {
   // private()?
   printOperandList(op.gangPrivateOperands(), ParallelOp::getPrivateKeyword(),
                    printer);
 
   // firstprivate()?
   printOperandList(op.gangFirstPrivateOperands(),
                    ParallelOp::getFirstPrivateKeyword(), printer);
 
+  printer << ' ';
   printer.printRegion(op.region(),
                       /*printEntryBlockArgs=*/false,
                       /*printBlockTerminators=*/true);
   printer.printOptionalAttrDictWithKeyword(
       op->getAttrs(), ParallelOp::getOperandSegmentSizeAttr());
 }
 
 unsigned ParallelOp::getNumDataOperands() {
static void print(OpAsmPrinter &printer, LoopOp &op) {
 
   // reduction()?
   printOperandList(op.reductionOperands(), LoopOp::getReductionKeyword(),
                    printer);
 
   if (op.getNumResults() > 0)
     printer << " -> (" << op.getResultTypes() << ")";
 
+  printer << ' ';
   printer.printRegion(op.region(),
                       /*printEntryBlockArgs=*/false,
                       /*printBlockTerminators=*/true);
 
   printer.printOptionalAttrDictWithKeyword(
       op->getAttrs(), {LoopOp::getExecutionMappingAttrName(),
                        LoopOp::getOperandSegmentSizeAttr()});
 }

mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp

if (!op.allocate_vars().empty())
     printAllocateAndAllocator(p, op.allocate_vars(), op.allocators_vars());
 
   if (auto def = op.default_val())
     p << "default(" << def->drop_front(3) << ") ";
 
   if (auto bind = op.proc_bind_val())
     p << "proc_bind(" << bind << ") ";
 
+  p << ' ';
   p.printRegion(op.getRegion());
 }
 
 //===----------------------------------------------------------------------===//
 // Parser and printer for Linear Clause
 //===----------------------------------------------------------------------===//
 
 /// linear ::= `linear` `(` linear-list `)`
static void printSectionsOp(OpAsmPrinter &p, SectionsOp op) {
 
   if (!op.reduction_vars().empty())
     printReductionVarList(p, op.reductions(), op.reduction_vars());
 
   if (!op.allocate_vars().empty())
     printAllocateAndAllocator(p, op.allocate_vars(), op.allocators_vars());
 
   if (op.nowait())
-    p << "nowait ";
+    p << "nowait";
 
+  p << ' ';
   p.printRegion(op.region());
 }
 
 static LogicalResult verifySectionsOp(SectionsOp op) {
 
   // A list item may not appear in more than one clause on the same directive,
   // except that it may be specified in both firstprivate and lastprivate
   // clauses.
if (auto ordered = op.ordered_val())
     p << "ordered(" << ordered << ") ";
 
   if (auto order = op.order_val())
     p << "order(" << order << ") ";
 
   if (!op.reduction_vars().empty())
     printReductionVarList(p, op.reductions(), op.reduction_vars());
 
+  p << ' ';
   p.printRegion(op.region(), /*printEntryBlockArgs=*/false);
 }
 
 //===----------------------------------------------------------------------===//
 // ReductionOp
 //===----------------------------------------------------------------------===//
 
 static ParseResult parseAtomicReductionRegion(OpAsmParser &parser,

mlir/lib/Dialect/PDLInterp/IR/PDLInterp.cpp

if (parser.parseArrow() || parser.parseSuccessor(successor))
     return failure();
   result.addSuccessors(successor);
 
   return success();
 }
 
 static void print(OpAsmPrinter &p, ForEachOp op) {
   BlockArgument arg = op.getLoopVariable();
-  p << ' ' << arg << " : " << arg.getType() << " in " << op.values();
+  p << ' ' << arg << " : " << arg.getType() << " in " << op.values() << ' ';
   p.printRegion(op.region(), /*printEntryBlockArgs=*/false);
   p.printOptionalAttrDict(op->getAttrs());
   p << " -> ";
   p.printSuccessor(op.successor());
 }
 
 static LogicalResult verify(ForEachOp op) {
   // Verify that the operation has exactly one argument.

mlir/lib/Dialect/SCF/SCF.cpp

if (parser.parseRegion(*body, /*arguments=*/{}, /*argTypes=*/{}) ||
     return failure();
 
   return success();
 }
 
 static void print(OpAsmPrinter &p, ExecuteRegionOp op) {
   p.printOptionalArrowTypeList(op.getResultTypes());
 
+  p << ' ';
   p.printRegion(op.getRegion(),
                 /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/true);
 
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 static LogicalResult verify(ExecuteRegionOp op) {

 static void print(OpAsmPrinter &p, ForOp op) {
   p << " " << op.getInductionVar() << " = " << op.getLowerBound() << " to "
     << op.getUpperBound() << " step " << op.getStep();
 
   printInitializationList(p, op.getRegionIterArgs(), op.getIterOperands(),
                           " iter_args");
   if (!op.getIterOperands().empty())
     p << " -> (" << op.getIterOperands().getTypes() << ')';
+  p << ' ';
   p.printRegion(op.getRegion(),
                 /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/op.hasIterOperands());
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 static ParseResult parseForOp(OpAsmParser &parser, OperationState &result) {
   auto &builder = parser.getBuilder();
static void print(OpAsmPrinter &p, IfOp op) {
   bool printBlockTerminators = false;
 
   p << " " << op.getCondition();
   if (!op.getResults().empty()) {
     p << " -> (" << op.getResultTypes() << ")";
     // Print yield explicitly if the op defines values.
     printBlockTerminators = true;
   }
+  p << ' ';
   p.printRegion(op.getThenRegion(),
                 /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/printBlockTerminators);
 
   // Print the 'else' regions if it exists and has a block.
   auto &elseRegion = op.getElseRegion();
   if (!elseRegion.empty()) {
-    p << " else";
+    p << " else ";
     p.printRegion(elseRegion,
                   /*printEntryBlockArgs=*/false,
                   /*printBlockTerminators=*/printBlockTerminators);
   }
 
   p.printOptionalAttrDict(op->getAttrs());
 }
 

 }
 
 static void print(OpAsmPrinter &p, ParallelOp op) {
   p << " (" << op.getBody()->getArguments() << ") = (" << op.getLowerBound()
     << ") to (" << op.getUpperBound() << ") step (" << op.getStep() << ")";
   if (!op.getInitVals().empty())
     p << " init (" << op.getInitVals() << ")";
   p.printOptionalArrowTypeList(op.getResultTypes());
+  p << ' ';
   p.printRegion(op.getRegion(), /*printEntryBlockArgs=*/false);
   p.printOptionalAttrDict(
       op->getAttrs(), /*elidedAttrs=*/ParallelOp::getOperandSegmentSizeAttr());
 }
 
 Region &ParallelOp::getLoopBody() { return getRegion(); }
 
 bool ParallelOp::isDefinedOutsideOfLoop(Value value) {
static ParseResult parseReduceOp(OpAsmParser &parser, OperationState &result) {
   if (parser.parseRegion(*body, /*arguments=*/{}, /*argTypes=*/{}))
     return failure();
 
   return success();
 }
 
 static void print(OpAsmPrinter &p, ReduceOp op) {
   p << "(" << op.getOperand() << ") ";
-  p << " : " << op.getOperand().getType();
+  p << " : " << op.getOperand().getType() << ' ';
   p.printRegion(op.getReductionOperator());
 }
 
 //===----------------------------------------------------------------------===//
 // ReduceReturnOp
 //===----------------------------------------------------------------------===//
 
 static LogicalResult verify(ReduceReturnOp op) {

 }
 
 /// Prints a `while` op.
 static void print(OpAsmPrinter &p, scf::WhileOp op) {
   printInitializationList(p, op.getBefore().front().getArguments(),
                           op.getInits(), " ");
   p << " : ";
   p.printFunctionalType(op.getInits().getTypes(), op.getResults().getTypes());
+  p << ' ';
   p.printRegion(op.getBefore(), /*printEntryBlockArgs=*/false);
-  p << " do";
+  p << " do ";
   p.printRegion(op.getAfter());
   p.printOptionalAttrDictWithKeyword(op->getAttrs());
 }
 
 /// Verifies that two ranges of types match, i.e. have the same number of
 /// entries and that types are pairwise equals. Reports errors on the given
 /// operation in case of mismatch.
 template <typename OpTy>

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

static void print(spirv::FuncOp fnOp, OpAsmPrinter &printer) {
   printer << " \"" << spirv::stringifyFunctionControl(fnOp.function_control())
           << "\"";
   function_like_impl::printFunctionAttributes(
       printer, fnOp, fnType.getNumInputs(), fnType.getNumResults(),
       {spirv::attributeName<spirv::FunctionControl>()});
 
   // Print the body if this is not an external function.
   Region &body = fnOp.body();
-  if (!body.empty())
+  if (!body.empty()) {
+    printer << ' ';
     printer.printRegion(body, /*printEntryBlockArgs=*/false,
                         /*printBlockTerminators=*/true);
   }
+}
 
 LogicalResult spirv::FuncOp::verifyType() {
   auto type = getTypeAttr().getValue();
   if (!type.isa<FunctionType>())
     return emitOpError("requires '" + getTypeAttrName() +
                        "' attribute of function type");
   if (getType().getNumResults() > 1)
     return emitOpError("cannot have more than one result");

 }
 
 static void print(spirv::LoopOp loopOp, OpAsmPrinter &printer) {
   auto *op = loopOp.getOperation();
 
   auto control = loopOp.loop_control();
   if (control != spirv::LoopControl::None)
     printer << " control(" << spirv::stringifyLoopControl(control) << ")";
+  printer << ' ';
   printer.printRegion(op->getRegion(0), /*printEntryBlockArgs=*/false,
                       /*printBlockTerminators=*/true);
 }
 
 /// Returns true if the given `srcBlock` contains only one `spv.Branch` to the
 /// given `dstBlock`.
 static inline bool hasOneBranchOpTo(Block &srcBlock, Block &dstBlock) {
   // Check that there is only one op in the `srcBlock`.
elidedAttrs.assign({addressingModelAttrName, memoryModelAttrName,
                       SymbolTable::getSymbolAttrName()});
 
   if (Optional<spirv::VerCapExtAttr> triple = moduleOp.vce_triple()) {
     printer << " requires " << *triple;
     elidedAttrs.push_back(spirv::ModuleOp::getVCETripleAttrName());
   }
 
   printer.printOptionalAttrDictWithKeyword(moduleOp->getAttrs(), elidedAttrs);
+  printer << ' ';
   printer.printRegion(moduleOp.getRegion());
 }
 
 static LogicalResult verify(spirv::ModuleOp moduleOp) {
   auto &op = *moduleOp.getOperation();
   auto *dialect = op.getDialect();
   DenseMap<std::pair<spirv::FuncOp, spirv::ExecutionModel>, spirv::EntryPointOp>
       entryPoints;
return parser.parseRegion(*state.addRegion(), /*arguments=*/{},
                             /*argTypes=*/{});
 }
 
 static void print(spirv::SelectionOp selectionOp, OpAsmPrinter &printer) {
   auto *op = selectionOp.getOperation();
   auto control = selectionOp.selection_control();
   if (control != spirv::SelectionControl::None)
     printer << " control(" << spirv::stringifySelectionControl(control) << ")";
+  printer << ' ';
   printer.printRegion(op->getRegion(0), /*printEntryBlockArgs=*/false,
                       /*printBlockTerminators=*/true);
 }
 
 static LogicalResult verify(spirv::SelectionOp selectionOp) {
   auto *op = selectionOp.getOperation();
 
   // We need to verify that the blocks follow the following layout:

mlir/lib/Dialect/Shape/IR/Shape.cpp

if (parser.parseOptionalAttrDict(result.attributes))
     return failure();
   return success();
 }
 
 static void print(OpAsmPrinter &p, AssumingOp op) {
   bool yieldsResults = !op.getResults().empty();
 
   p << " " << op.getWitness();
-  if (yieldsResults) {
+  if (yieldsResults)
     p << " -> (" << op.getResultTypes() << ")";
-  }
+  p << ' ';
   p.printRegion(op.getDoRegion(),
                 /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/yieldsResults);
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 namespace {
 // Removes AssumingOp with a passing witness and inlines the region.
ParseResult parseFunctionLibraryOp(OpAsmParser &parser,
   return success();
 }
 
 void print(OpAsmPrinter &p, FunctionLibraryOp op) {
   p << ' ';
   p.printSymbolName(op.getName());
   p.printOptionalAttrDictWithKeyword(
       op->getAttrs(), {SymbolTable::getSymbolAttrName(), "mapping"});
+  p << ' ';
   p.printRegion(op.getOperation()->getRegion(0), /*printEntryBlockArgs=*/false,
                 /*printBlockTerminators=*/false);
   p << " mapping ";
   p.printAttributeWithoutType(op.getMappingAttr());
 }
 
 //===----------------------------------------------------------------------===//
 // GetExtentOp
static ParseResult parseReduceOp(OpAsmParser &parser, OperationState &result) {
 
   return success();
 }
 
 static void print(OpAsmPrinter &p, ReduceOp op) {
   p << '(' << op.getShape() << ", " << op.getInitVals()
     << ") : " << op.getShape().getType();
   p.printOptionalArrowTypeList(op.getResultTypes());
+  p << ' ';
   p.printRegion(op.getRegion());
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 #define GET_OP_CLASSES
 #include "mlir/Dialect/Shape/IR/ShapeOps.cpp.inc"

mlir/lib/Dialect/StandardOps/IR/Ops.cpp

if (parser.parseRegion(*body, llvm::None, llvm::None) ||
       parser.parseOptionalAttrDict(result.attributes))
     return failure();
   result.types.push_back(memrefType.cast<MemRefType>().getElementType());
   return success();
 }
 
 static void print(OpAsmPrinter &p, GenericAtomicRMWOp op) {
   p << ' ' << op.getMemref() << "[" << op.getIndices()
-    << "] : " << op.getMemref().getType();
+    << "] : " << op.getMemref().getType() << ' ';
   p.printRegion(op.getRegion());
   p.printOptionalAttrDict(op->getAttrs());
 }
 
 //===----------------------------------------------------------------------===//
 // AtomicYieldOp
 //===----------------------------------------------------------------------===//
 

mlir/lib/IR/AsmPrinter.cpp

void OperationPrinter::printSuccessorAndUseList(Block *successor,
   interleaveComma(succOperands,
                   [this](Value operand) { printType(operand.getType()); });
   os << ')';
 }
 
 void OperationPrinter::printRegion(Region &region, bool printEntryBlockArgs,
                                    bool printBlockTerminators,
                                    bool printEmptyBlock) {
-  os << " {" << newLine;
+  os << "{" << newLine;
   if (!region.empty()) {
     auto restoreDefaultDialect =
         llvm::make_scope_exit([&]() { defaultDialectStack.pop_back(); });
     if (auto iface = dyn_cast<OpAsmOpInterface>(region.getParentOp()))
       defaultDialectStack.push_back(iface.getDefaultDialect());
     else
       defaultDialectStack.push_back("");
 

mlir/lib/IR/FunctionImplementation.cpp

if (auto visibility = op->getAttrOfType<StringAttr>(visibilityAttrName))
     p << visibility.getValue() << ' ';
   p.printSymbolName(funcName);
 
   printFunctionSignature(p, op, argTypes, isVariadic, resultTypes);
   printFunctionAttributes(p, op, argTypes.size(), resultTypes.size(),
                           {visibilityAttrName});
   // Print the body if this is not an external function.
   Region &body = op->getRegion(0);
-  if (!body.empty())
+  if (!body.empty()) {
+    p << ' ';
     p.printRegion(body, /*printEntryBlockArgs=*/false,
                   /*printBlockTerminators=*/true);
   }
+}

mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir

 }
 
 // CHECK-LABEL: @wsloop
 // CHECK: (%[[ARG0:.*]]: i64, %[[ARG1:.*]]: i64, %[[ARG2:.*]]: i64, %[[ARG3:.*]]: i64, %[[ARG4:.*]]: i64, %[[ARG5:.*]]: i64)
 func @wsloop(%arg0: index, %arg1: index, %arg2: index, %arg3: index, %arg4: index, %arg5: index) {
   // CHECK: omp.parallel
   omp.parallel {
     // CHECK: omp.wsloop (%[[ARG6:.*]], %[[ARG7:.*]]) : i64 = (%[[ARG0]], %[[ARG1]]) to (%[[ARG2]], %[[ARG3]]) step (%[[ARG4]], %[[ARG5]]) {
-    "omp.wsloop"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5) ( {
+    "omp.wsloop"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5) ({
     ^bb0(%arg6: index, %arg7: index):  // no predecessors
       // CHECK-DAG: %[[CAST_ARG6:.*]] = builtin.unrealized_conversion_cast %[[ARG6]] : i64 to index
       // CHECK-DAG: %[[CAST_ARG7:.*]] = builtin.unrealized_conversion_cast %[[ARG7]] : i64 to index
       // CHECK: "test.payload"(%[[CAST_ARG6]], %[[CAST_ARG7]]) : (index, index) -> ()
       "test.payload"(%arg6, %arg7) : (index, index) -> ()
       omp.yield
     }) {operand_segment_sizes = dense<[2, 2, 2, 0, 0, 0, 0, 0, 0, 0]> : vector<10xi32>} : (index, index, index, index, index, index) -> ()
     omp.terminator
   }
   return
 }

mlir/test/Conversion/TosaToSCF/tosa-to-scf.mlir

 // RUN: mlir-opt --split-input-file --tosa-to-scf %s -verify-diagnostics -o -| FileCheck %s
 
 // CHECK-LABEL: func @while_test
 // CHECK-SAME: ([[ARG0:%.+]]: tensor<i32>)
 func @while_test(%arg0 : tensor<i32>) -> (tensor<i32>) {
   // CHECK: [[WHILE:%.+]] = scf.while ([[ARG1:%.+]] = [[ARG0]])
-  %1 = "tosa.while_loop"(%arg0) ( {
+  %1 = "tosa.while_loop"(%arg0) ({
   ^bb0(%arg2: tensor<i32>):
     // CHECK: "tosa.const"
     %2 = "tosa.const"() {value = dense<3> : tensor<i32>} : () -> tensor<i32>
 
     // CHECK: [[COMPARE:%.+]] = "tosa.greater_equal"
     %3 = "tosa.greater_equal"(%2, %arg2) : (tensor<i32>, tensor<i32>) -> tensor<i1>
 
     // CHECK: [[EX:%.+]] = tensor.extract [[COMPARE]]

mlir/test/Dialect/Affine/ops.mlir

 
 // Check that an explicit affine.yield is not printed in custom format.
 // Check that no extra terminator is introduced.
 // CHECK-LABEL: @affine.yield
 func @affine.yield() {
   // CHECK: affine.for
   // CHECK-NEXT: }
   //
-  // GENERIC:      "affine.for"() ( {
+  // GENERIC:      "affine.for"() ({
   // GENERIC-NEXT: ^bb0(%{{.*}}: index):  // no predecessors
   // GENERIC-NEXT:   "affine.yield"() : () -> ()
   // GENERIC-NEXT: }) {lower_bound = #map0, step = 1 : index, upper_bound = #map1} : () -> ()
   affine.for %i = 0 to 10 {
     "affine.yield"() : () -> ()
   }
   return
 }

mlir/test/Dialect/Bufferization/Transforms/buffer-deallocation.mlir

 
 // -----
 
 // Test Case: The op "test.bar" does not implement the RegionBranchOpInterface.
 // This is not allowed in buffer deallocation.
 
 func @noRegionBranchOpInterface() {
 // expected-error@+1 {{All operations with attached regions need to implement the RegionBranchOpInterface.}}
-  %0 = "test.bar"() ( {
+  %0 = "test.bar"() ({
 // expected-error@+1 {{All operations with attached regions need to implement the RegionBranchOpInterface.}}
-    %1 = "test.bar"() ( {
+    %1 = "test.bar"() ({
       "test.yield"() : () -> ()
     }) : () -> (i32)
     "test.yield"() : () -> ()
   }) : () -> (i32)
   "test.terminator"() : () -> ()
 }
 
 // -----

mlir/test/Dialect/GPU/invalid.mlir

module {
   }
 }
 
 // -----
 
 module {
   gpu.module @gpu_funcs {
     // expected-error @+1 {{'gpu.func' op expected at least 5 arguments to body region}}
-    "gpu.func"() ( {
+    "gpu.func"() ({
     ^bb0(%arg0: f32, %arg1: memref<?xf32>, %arg2: memref<5xf32, 3>, %arg3: memref<5xf32, 5>):
       "gpu.return"() : () -> ()
     } ) {gpu.kernel, sym_name = "kernel_1", type = (f32, memref<?xf32>) -> (), workgroup_attributions = 3: i64} : () -> ()
   }
 }
 
 // -----
 

mlir/test/Dialect/GPU/ops.mlir

gpu.module @gpu_funcs {
     // CHECK:       {
     gpu.func @empty_attribution(%arg0: f32) workgroup() private() {
       gpu.return
     }
   }
 
   gpu.module @explicit_attributions {
     // CHECK-LABEL: gpu.func @kernel_1({{.*}}: f32, {{.*}}: memref<?xf32>) workgroup({{.*}}: memref<5xf32, 3>) private({{.*}}: memref<5xf32, 5>)
-    "gpu.func"() ( {
+    "gpu.func"() ({
     ^bb0(%arg0: f32, %arg1: memref<?xf32>, %arg2: memref<5xf32, 3>, %arg3: memref<5xf32, 5>):
       "gpu.return"() : () -> ()
     } ) {gpu.kernel, sym_name = "kernel_1", type = (f32, memref<?xf32>) -> (), workgroup_attributions = 1: i64} : () -> ()
   }
 
   func @alloc() {
     // CHECK-LABEL: func @alloc()
 

mlir/test/Dialect/Linalg/invalid.mlir

 
 func @tiled_loop_incorrent_iterator_types_count(%A: memref<192x192xf32>,
     %B: memref<192x192xf32>, %C: memref<192x192xf32>,
     %C_tensor: tensor<192x192xf32>) {
   %c24 = arith.constant 24 : index
   %c0 = arith.constant 0 : index
   %c192 = arith.constant 192 : index
   // expected-error @+1 {{expected iterator types array attribute size = 1 to match the number of loops = 2}}
-  %0 = "linalg.tiled_loop"(%c0, %c0, %c192, %c192, %c24, %c24, %A, %B, %C_tensor, %C) ( {
+  %0 = "linalg.tiled_loop"(%c0, %c0, %c192, %c192, %c24, %c24, %A, %B, %C_tensor, %C) ({
     ^bb0(%arg4: index, %arg5: index, %A_: memref<192x192xf32>,
          %B_: memref<192x192xf32>, %CT_: tensor<192x192xf32>,
          %C_: memref<192x192xf32>):
       call @foo(%A_, %B_, %C_)
           : (memref<192x192xf32>, memref<192x192xf32>, memref<192x192xf32>)-> ()
       linalg.yield %CT_ : tensor<192x192xf32>
     }) {
       iterator_types = ["parallel"],
       operand_segment_sizes = dense<2> : vector<5xi32>
     } : (index, index, index, index, index, index, memref<192x192xf32>,
       memref<192x192xf32>, tensor<192x192xf32>, memref<192x192xf32>
     ) -> tensor<192x192xf32>
   return
 }
 
 // -----
 
 func private @foo(%A: memref<100xf32>) -> ()
 
 func @tiled_loop_incorrent_block_arg_type(%A: memref<192xf32>) {
   %c0 = arith.constant 0 : index
   %c192 = arith.constant 192 : index
   %c24 = arith.constant 24 : index
   // expected-error @+1 {{expected output arg 0 with type = 'memref<192xf32>' to match region arg 1 type = 'memref<100xf32>'}}
-  "linalg.tiled_loop"(%c0, %c192, %c24, %A) ( {
+  "linalg.tiled_loop"(%c0, %c192, %c24, %A) ({
     ^bb0(%arg4: index, %A_: memref<100xf32>):
       call @foo(%A_) : (memref<100xf32>)-> ()
       linalg.yield
     }) {
       iterator_types = ["parallel"],
       operand_segment_sizes = dense<[1, 1, 1, 0, 1]> : vector<5xi32>
     } : (index, index, index, memref<192xf32>) -> ()
   return

mlir/test/Dialect/Linalg/named-ops.mlir

 // -----
 
 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1 * 2, d2 * 2 + d5, d6)>
 #map1 = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d4, d5, d6, d3)>
 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d3)>
 func @conv_interface_wrong_input_indexing_map(
     %arg0 : tensor<?x?x?x?xf32>, %arg2 : tensor<?x?x?x?xf32>, %arg1 : tensor<?x?x?x?xf32>) -> tensor<?x?x?x?xf32> {
   // expected-error @+1 {{unexpected input index map for convolutions}}
-  %0 = "linalg.conv_2d_nhwc_hwcf"(%arg0, %arg1, %arg2) ( {
+  %0 = "linalg.conv_2d_nhwc_hwcf"(%arg0, %arg1, %arg2) ({
     ^bb0(%arg3: f32, %arg4: f32, %arg5 : f32):  // no predecessors
       %1 = "arith.mulf"(%arg3, %arg4) : (f32, f32) -> f32
       %2 = "arith.addf"(%arg5, %1) : (f32, f32) -> f32
       "linalg.yield"(%2) : (f32) -> ()
     }) {dilations = dense<1> : tensor<2xi64>, linalg.memoized_indexing_maps = [#map0, #map1, #map2], operand_segment_sizes = dense<[2, 1]> : vector<2xi32>, strides = dense<2> : tensor<2xi64>} : (tensor<?x?x?x?xf32>, tensor<?x?x?x?xf32>, tensor<?x?x?x?xf32>) -> tensor<?x?x?x?xf32>
   return %0 : tensor<?x?x?x?xf32>
 }
 
 // -----
 
 #map0 = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1 + d4, d2 + d5, d6)>
 #map1 = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d4, d5, d6, d3, d5 + 1)>
 #map2 = affine_map<(d0, d1, d2, d3, d4, d5, d6) -> (d0, d1, d2, d3)>
 func @conv_interface_wrong_num_operands(
     %arg0 : tensor<?x?x?x?xf32>, %arg1 : tensor<?x?x?x?x?xf32>, %arg2 : tensor<?x?x?x?xf32>) -> tensor<?x?x?x?xf32> {
   // expected-error @+1 {{expected output/filter indexing maps to be projected permutations}}
-  %0 = "linalg.conv_2d_nhwc_hwcf"(%arg0, %arg1, %arg2) ( {
+  %0 = "linalg.conv_2d_nhwc_hwcf"(%arg0, %arg1, %arg2) ({
     ^bb0(%arg3: f32, %arg4: f32, %arg5 : f32):  // no predecessors
       %1 = "arith.mulf"(%arg3, %arg4) : (f32, f32) -> f32
       %2 = "arith.addf"(%arg5, %1) : (f32, f32) -> f32
       "linalg.yield"(%2) : (f32) -> ()
     }) {dilations = dense<1> : tensor<2xi64>, linalg.memoized_indexing_maps = [#map0, #map1, #map2], operand_segment_sizes = dense<[2, 1]> : vector<2xi32>, strides = dense<1> : tensor<2xi64>} : (tensor<?x?x?x?xf32>, tensor<?x?x?x?x?xf32>, tensor<?x?x?x?xf32>) -> tensor<?x?x?x?xf32>
   return %0 : tensor<?x?x?x?xf32>
 }

mlir/test/Dialect/MemRef/invalid.mlir

 func @assume_alignment(%0: memref<4x4xf16>) {
   // expected-error@+1 {{attribute 'alignment' failed to satisfy constraint: 32-bit signless integer attribute whose value is positive}}
   memref.assume_alignment %0, 0 : memref<4x4xf16>
   return
 }
 
 // -----
 
-"alloca_without_scoped_alloc_parent"() ( {
+"alloca_without_scoped_alloc_parent"() ({
   memref.alloca() : memref<1xf32>
   // expected-error@-1 {{requires an ancestor op with AutomaticAllocationScope trait}}
   return
 }) : () -> ()
 
 // -----
 
 func @bad_alloc_wrong_dynamic_dim_count() {

mlir/test/Dialect/Tosa/inlining.mlir

 // RUN: mlir-opt %s -inline | FileCheck %s
 
 // These tests verify that regions with operations from TOSA dialect
 // can be inlined.
 
 // CHECK-LABEL: func @inlined_if_fn
 // Check that both the calls and the functions are eliminated after inlining:
 // CHECK-NOT: @add
 // CHECK-NOT: @sub
 func @inlined_if_fn(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<i1>) -> tensor<f32> {
-  %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ( {
+  %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ({
   ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):  // no predecessors
     %1 = call @add(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
     "tosa.yield"(%1) : (tensor<f32>) -> ()
   },  {
   ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):  // no predecessors
     %1 = call @sub(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
     "tosa.yield"(%1) : (tensor<f32>) -> ()
   }) : (tensor<i1>, tensor<f32>, tensor<f32>) -> tensor<f32>

 }
 
 // -----
 
 // CHECK-LABEL: func @inlined_while_fn
 func @inlined_while_fn(%arg0: tensor<i32>, %arg1: tensor<i32>, %arg2: tensor<i32>, %arg3: tensor<10xi32>) -> tensor<10xi32> {
   // Check that calls are inlined and functions eliminated:
   // CHECK-NOT: @while
-  %1:4 = "tosa.while_loop"(%arg0, %arg1, %arg2, %arg3) ( {
+  %1:4 = "tosa.while_loop"(%arg0, %arg1, %arg2, %arg3) ({
   ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):  // no predecessors
     %2 = call @while_cond_40(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> tensor<i1>
     "tosa.yield"(%2) : (tensor<i1>) -> ()
   },  {
   ^bb0(%arg4: tensor<i32>, %arg5: tensor<i32>, %arg6: tensor<i32>, %arg7: tensor<10xi32>):  // no predecessors
     %2:4 = call @while_body_50(%arg4, %arg5, %arg6, %arg7) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>)
     "tosa.yield"(%2#0, %2#1, %2#2, %2#3) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> ()
   }) : (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>) -> (tensor<i32>, tensor<i32>, tensor<i32>, tensor<10xi32>)

mlir/test/Dialect/Tosa/ops.mlir

 func @test_identity(%arg0: tensor<13x21x3xi32>) -> tensor<13x21x3xi32> {
   %0 = "tosa.identity"(%arg0) : (tensor<13x21x3xi32>) -> tensor<13x21x3xi32>
   return %0 : tensor<13x21x3xi32>
 }
 
 // -----
 // CHECK-LABEL: cond_if
 func @test_cond_if(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<i1>) -> tensor<f32> {
-  %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ( {
+  %0 = "tosa.cond_if"(%arg2, %arg0, %arg1) ({
   ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):  // no predecessors
     %1 = "tosa.add"(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
     "tosa.yield"(%1) : (tensor<f32>) -> ()
   },  {
   ^bb0(%arg3: tensor<f32>, %arg4: tensor<f32>):  // no predecessors
     %1 = "tosa.sub"(%arg3, %arg4) : (tensor<f32>, tensor<f32>) -> tensor<f32>
     "tosa.yield"(%1) : (tensor<f32>) -> ()
   }) : (tensor<i1>, tensor<f32>, tensor<f32>) -> tensor<f32>
   return %0 : tensor<f32>
 }
 
 // -----
 // CHECK-LABEL: while_loop
 func @test_while_loop(%arg0: tensor<10xi32>, %arg1: tensor<i32>) {
   %0 = "tosa.const"() {value = dense<0> : tensor<i32>} : () -> tensor<i32>
-  %1:3 = "tosa.while_loop"(%0, %0, %arg0) ( {
+  %1:3 = "tosa.while_loop"(%0, %0, %arg0) ({
   ^bb0(%arg2: tensor<i32>, %arg3: tensor<i32>, %arg4: tensor<10xi32>):  // no predecessors
     %2 = "tosa.greater_equal"(%arg3, %arg1) : (tensor<i32>, tensor<i32>) -> tensor<i1>
     %3 = "tosa.logical_not"(%2) : (tensor<i1>) -> tensor<i1>
     "tosa.yield"(%3) : (tensor<i1>) -> ()
   },  {
   ^bb0(%arg2: tensor<i32>, %arg3: tensor<i32>, %arg4: tensor<10xi32>):  // no predecessors
     %2 = "tosa.const"() {value = dense<1> : tensor<i32>} : () -> tensor<i32>
     %3 = "tosa.add"(%arg3, %2) : (tensor<i32>, tensor<i32>) -> tensor<i32>
     %4 = "tosa.reshape"(%2) {new_shape = [1]} : (tensor<i32>) -> tensor<1xi32>
     %5 = "tosa.add"(%arg4, %4) : (tensor<10xi32>, tensor<1xi32>) -> tensor<10xi32>
     %6 = "tosa.add"(%arg2, %2) : (tensor<i32>, tensor<i32>) -> tensor<i32>
     "tosa.yield"(%6, %3, %5) : (tensor<i32>, tensor<i32>, tensor<10xi32>) -> ()
   }) : (tensor<i32>, tensor<i32>, tensor<10xi32>) -> (tensor<i32>, tensor<i32>, tensor<10xi32>)
   return
 }

mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir

 
 // CHECK-LABEL: @while_test
 func @while_test(%arg0 : tensor<i32>) -> (tensor<*xi32>) {
   // CHECK:      "tosa.add" 
   // CHECK-SAME: (tensor<i32>, tensor<i32>) -> tensor<i32>
   %0 = "tosa.add"(%arg0, %arg0) : (tensor<i32>, tensor<i32>) -> tensor<*xi32>
 
   // CHECK:      "tosa.while_loop"
-  %1 = "tosa.while_loop"(%0) ( {
+  %1 = "tosa.while_loop"(%0) ({
 
   // CHECK:      ^bb0
   // CHECK-SAME: tensor<i32>
   ^bb0(%arg2: tensor<*xi32>):
     %2 = "tosa.const"() {value = dense<3> : tensor<i32>} : () -> tensor<i32>
     // CHECK:       "tosa.greater_equal"
     // CHECK-SAME: (tensor<i32>, tensor<i32>) -> tensor<i1>
     %3 = "tosa.greater_equal"(%2, %arg2) : (tensor<i32>, tensor<*xi32>) -> tensor<*xi1>
func @while_test(%arg0 : tensor<i32>) -> (tensor<*xi32>) {
   return %1 : tensor<*xi32>
 }
 
 // -----
 
 // CHECK-LABEL: @while_test
 func @while_test(%arg0 : tensor<i32>, %arg1 : tensor<1xi32>) -> () {
   // CHECK:      "tosa.while_loop"
-  %1:2 = "tosa.while_loop"(%arg0, %arg1) ( {
+  %1:2 = "tosa.while_loop"(%arg0, %arg1) ({
 
   // CHECK:      ^bb0
   // CHECK-SAME: tensor<i32>
   // CHECK-SAME: tensor<?xi32>
   ^bb0(%arg2: tensor<*xi32>, %arg3: tensor<*xi32>):
     %2 = "tosa.const"() {value = dense<3> : tensor<i32>} : () -> tensor<i32>
 
     // CHECK:       "tosa.greater_equal"

mlir/test/IR/invalid-ops.mlir

func @generic_atomic_rmw_wrong_arg_type(%I: memref<10xf32>, %i : index) {
   }
   return
 }
 
 // -----
 
 func @generic_atomic_rmw_result_type_mismatch(%I: memref<10xf32>, %i : index) {
  // expected-error@+1 {{failed to verify that result type matches element type of memref}}
- %0 = "std.generic_atomic_rmw"(%I, %i) ( {
+ %0 = "std.generic_atomic_rmw"(%I, %i) ({
     ^bb0(%old_value: f32):
       %c1 = arith.constant 1.0 : f32
       atomic_yield %c1 : f32
     }) : (memref<10xf32>, index) -> i32
   return
 }
 
 // -----

mlir/test/IR/parser.mlir

func @verbose_if(%N: index) {
   })
   { condition = #set0 } : (index, index, index) -> ()
   return
 }
 
 // CHECK-LABEL: func @terminator_with_regions
 func @terminator_with_regions() {
   // Combine successors and regions in the same operation.
-  // CHECK: "region"()[^bb1] ( {
+  // CHECK: "region"()[^bb1] ({
   // CHECK: }) : () -> ()
   "region"()[^bb2] ({}) : () -> ()
 ^bb2:
   return
 }
 
 // CHECK-LABEL: func @unregistered_term
 func @unregistered_term(%arg0 : i1) -> i1 {
func @special_float_values_in_tensors() {
   "foo"(){bar = sparse<[[1,1,0],[0,1,1]], [0xFFFFFFFF, 0x7F800001]> : tensor<2x2x2xf32>} : () -> ()
 }
 
 // Test parsing of an op with multiple region arguments, and without a
 // delimiter.
 
 // CHECK-LABEL: func @op_with_region_args
 func @op_with_region_args() {
-  // CHECK: "test.polyfor"() ( {
+  // CHECK: "test.polyfor"() ({
   // CHECK-NEXT: ^bb{{.*}}(%{{.*}}: index, %{{.*}}: index, %{{.*}}: index):
   test.polyfor %i, %j, %k {
     "foo"() : () -> ()
   }
   return
 }
 
 // Test allowing different name scopes for regions isolated from above.
test.graph_region {
     "test.terminator"() : ()->()
   }
   return
 }
 
 // CHECK: test.graph_region {
 test.graph_region {
 // CHECK:   [[VAL1:%.*]] = "op1"([[VAL3:%.*]]) : (i32) -> i32
-// CHECK:   [[VAL2:%.*]] = "test.ssacfg_region"([[VAL1]], [[VAL2]], [[VAL3]], [[VAL4:%.*]]) ( {
+// CHECK:   [[VAL2:%.*]] = "test.ssacfg_region"([[VAL1]], [[VAL2]], [[VAL3]], [[VAL4:%.*]]) ({
 // CHECK:     [[VAL5:%.*]] = "op2"([[VAL1]], [[VAL2]], [[VAL3]], [[VAL4]]) : (i32, i32, i32, i32) -> i32
 // CHECK:   }) : (i32, i32, i32, i32) -> i32
 // CHECK:   [[VAL3]] = "op2"([[VAL1]], [[VAL4]]) : (i32, i32) -> i32
 // CHECK:   [[VAL4]] = "op3"([[VAL1]]) : (i32) -> i32
   %1 = "op1"(%3) : (i32) -> (i32)
   %2 = "test.ssacfg_region"(%1, %2, %3, %4) ({
     %5 = "op2"(%1, %2, %3, %4) :
    (i32, i32, i32, i32) -> (i32)
   }) : (i32, i32, i32, i32) -> (i32)
   %3 = "op2"(%1, %4) : (i32, i32) -> (i32)
   %4 = "op3"(%1) : (i32) -> (i32)
 }
 
-// CHECK: "unregistered_func_might_have_graph_region"() ( {
+// CHECK: "unregistered_func_might_have_graph_region"() ({
 // CHECK: [[VAL1:%.*]] = "foo"([[VAL1]], [[VAL2:%.*]]) : (i64, i64) -> i64
 // CHECK: [[VAL2]] = "bar"([[VAL1]])
-"unregistered_func_might_have_graph_region"() ( {
+"unregistered_func_might_have_graph_region"() ({
   %1 = "foo"(%1, %2) : (i64, i64) -> i64
   %2 = "bar"(%1) : (i64) -> i64
   "unregistered_terminator"() : () -> ()
 }) {sym_name = "unregistered_op_dominance_violation_ok", type = () -> i1} : () -> ()
 
 // This is an unregister operation, the printing/parsing is handled by the dialect.
 // CHECK: test.dialect_custom_printer custom_format
 test.dialect_custom_printer custom_format
 
 // This is a registered operation with no custom parser and printer, and should
 // be handled by the dialect.
 // CHECK: test.dialect_custom_format_fallback custom_format_fallback
 test.dialect_custom_format_fallback custom_format_fallback

mlir/test/IR/pretty-region-args.mlir

 // RUN: mlir-opt -allow-unregistered-dialect %s | FileCheck %s
 
 // CHECK-LABEL: func @custom_region_names
 func @custom_region_names() -> () {
-  "test.polyfor"() ( {
+  "test.polyfor"() ({
   ^bb0(%arg0: index, %arg1: index, %arg2: index):
     "foo"() : () -> ()
   }) { arg_names = ["i", "j", "k"] } : () -> ()
   // CHECK: test.polyfor
   // CHECK-NEXT: ^bb{{.*}}(%i: index, %j: index, %k: index):
   return
 }
 
 // CHECK-LABEL: func @weird_names
 // Make sure the asmprinter handles weird names correctly.
 func @weird_names() -> () {
-  "test.polyfor"() ( {
+  "test.polyfor"() ({
   ^bb0(%arg0: i32, %arg1: i32, %arg2: index):
     "foo"() : () -> i32
   }) { arg_names = ["a .^x", "0"] } : () -> ()
   // CHECK: test.polyfor
   // CHECK-NEXT: ^bb{{.*}}(%a_.5Ex: i32, %_0: i32, %arg0: index):
   // CHECK-NEXT: %0 = "foo"()
   return
 }
 

mlir/test/IR/pretty_printed_region_op.mlir

 func @pretty_printed_region_op(%arg0 : f32, %arg1 : f32) -> (f32) {
 // CHECK-CUSTOM:  test.pretty_printed_region %arg1, %arg0
 // CHECK-GENERIC: "test.pretty_printed_region"(%arg1, %arg0)
 // CHECK:          ^bb0(%arg[[x:[0-9]+]]: f32, %arg[[y:[0-9]+]]: f32):
 // CHECK:            %[[RES:.*]] = "non.special.op"(%arg[[x]], %arg[[y]]) : (f32, f32) -> f32
 // CHECK:            "test.return"(%[[RES]]) : (f32) -> ()
 // CHECK:          : (f32, f32) -> f32
 
-  %0 = test.pretty_printed_region %arg1, %arg0 ( {
+  %0 = test.pretty_printed_region %arg1, %arg0 ({
     ^bb0(%arg2: f32, %arg3: f32):
       %1 = "non.special.op"(%arg2, %arg3) : (f32, f32) -> f32
       "test.return"(%1) : (f32) -> ()
     }) : (f32, f32) -> f32
     return %0 : f32
 }
 

mlir/test/IR/region.mlir

func @named_region_has_wrong_number_of_blocks() {
     }) : () -> ()
     return
 }
 
 // -----
 
 // Region with single block and not terminator.
 // CHECK: unregistered_without_terminator
-"test.unregistered_without_terminator"() ( {
+"test.unregistered_without_terminator"() ({
   ^bb0:  // no predecessors
 }) : () -> ()
 
 // -----
 
 // CHECK: test.single_no_terminator_op
 "test.single_no_terminator_op"() (
   {

mlir/test/IR/wrapping_op.mlir

 // RUN: mlir-opt -allow-unregistered-dialect %s | FileCheck %s
 // RUN: mlir-opt -allow-unregistered-dialect -mlir-print-op-generic -mlir-print-debuginfo -mlir-print-local-scope %s | FileCheck %s --check-prefix=CHECK-GENERIC
 
 // CHECK-LABEL: func @wrapping_op
 // CHECK-GENERIC: "builtin.func"
 func @wrapping_op(%arg0 : i32, %arg1 : f32) -> (i3, i2, i1) {
 // CHECK: %0:3 = test.wrapping_region wraps "some.op"(%arg1, %arg0) {test.attr = "attr"} : (f32, i32) -> (i1, i2, i3)
-// CHECK-GENERIC: "test.wrapping_region"() ( {
+// CHECK-GENERIC: "test.wrapping_region"() ({
 // CHECK-GENERIC:   %[[NESTED_RES:.*]]:3 = "some.op"(%arg1, %arg0) {test.attr = "attr"} : (f32, i32) -> (i1, i2, i3) loc("some_NameLoc")
 // CHECK-GENERIC:   "test.return"(%[[NESTED_RES]]#0, %[[NESTED_RES]]#1, %[[NESTED_RES]]#2) : (i1, i2, i3) -> () loc("some_NameLoc")
 // CHECK-GENERIC: }) : () -> (i1, i2, i3) loc("some_NameLoc")
   %res:3 = test.wrapping_region wraps "some.op"(%arg1, %arg0) { test.attr = "attr" } : (f32, i32) -> (i1, i2, i3) loc("some_NameLoc")
   return %res#2, %res#1, %res#0 : i3, i2, i1
 }
 // CHECK-GENERIC: sym_name = "wrapping_op"

mlir/test/Target/LLVMIR/openmp-llvm.mlir

 // CHECK: @[[$wsloop_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$wsloop_loc]], {{.*}}
 
 // CHECK-LABEL: @wsloop_simple
 llvm.func @wsloop_simple(%arg0: !llvm.ptr<f32>) {
   %0 = llvm.mlir.constant(42 : index) : i64
   %1 = llvm.mlir.constant(10 : index) : i64
   %2 = llvm.mlir.constant(1 : index) : i64
   omp.parallel {
-    "omp.wsloop"(%1, %0, %2) ( {
+    "omp.wsloop"(%1, %0, %2) ({
     ^bb0(%arg1: i64):
       // The form of the emitted IR is controlled by OpenMPIRBuilder and
       // tested there. Just check that the right functions are called.
       // CHECK: call i32 @__kmpc_global_thread_num
       // CHECK: call void @__kmpc_for_static_init_{{.*}}(%struct.ident_t* @[[$wsloop_loc_struct]],
       %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32
       %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
       llvm.store %3, %4 : !llvm.ptr<f32>
       omp.yield
       // CHECK: call void @__kmpc_for_static_fini(%struct.ident_t* @[[$wsloop_loc_struct]],
     }) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0, 0, 0, 0]> : vector<10xi32>} : (i64, i64, i64) -> ()
     omp.terminator
   }
   llvm.return
 }
 
 // -----
 
 // CHECK-LABEL: @wsloop_inclusive_1
 llvm.func @wsloop_inclusive_1(%arg0: !llvm.ptr<f32>) {
   %0 = llvm.mlir.constant(42 : index) : i64
   %1 = llvm.mlir.constant(10 : index) : i64
   %2 = llvm.mlir.constant(1 : index) : i64
   // CHECK: store i64 31, i64* %{{.*}}upperbound
-  "omp.wsloop"(%1, %0, %2) ( {
+  "omp.wsloop"(%1, %0, %2) ({
   ^bb0(%arg1: i64):
     %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32
     %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
     llvm.store %3, %4 : !llvm.ptr<f32>
     omp.yield
   }) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0, 0, 0, 0]> : vector<10xi32>} : (i64, i64, i64) -> ()
   llvm.return
 }
 
 // -----
 
 // CHECK-LABEL: @wsloop_inclusive_2
 llvm.func @wsloop_inclusive_2(%arg0: !llvm.ptr<f32>) {
   %0 = llvm.mlir.constant(42 : index) : i64
   %1 = llvm.mlir.constant(10 : index) : i64
   %2 = llvm.mlir.constant(1 : index) : i64
   // CHECK: store i64 32, i64* %{{.*}}upperbound
-  "omp.wsloop"(%1, %0, %2) ( {
+  "omp.wsloop"(%1, %0, %2) ({
   ^bb0(%arg1: i64):
     %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32
     %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
     llvm.store %3, %4 : !llvm.ptr<f32>
     omp.yield
   }) {inclusive, operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0, 0, 0, 0]> : vector<10xi32>} : (i64, i64, i64) -> ()
   llvm.return
 }

mlir/test/Transforms/test-merge-blocks.mlir

 // RUN: mlir-opt -allow-unregistered-dialect -split-input-file -test-merge-blocks -verify-diagnostics %s | FileCheck %s
 
 // CHECK-LABEL: @merge_blocks
 func @merge_blocks(%arg0: i32, %arg1 : i32) -> () {
-  //      CHECK: "test.merge_blocks"() ( {
+  //      CHECK: "test.merge_blocks"() ({
   // CHECK-NEXT:   "test.return"
   // CHECK-NEXT: })
   // CHECK-NEXT: "test.return"
   %0:2 = "test.merge_blocks"() ({
   ^bb0:
      "test.br"(%arg0, %arg1)[^bb1] : (i32, i32) -> ()
   ^bb1(%arg3 : i32, %arg4 : i32):
      "test.return"(%arg3, %arg4) : (i32, i32) -> ()

mlir/test/lib/Dialect/Test/TestDialect.cpp

static ParseResult parseIsolatedRegionOp(OpAsmParser &parser,
   return parser.parseRegion(*body, argInfo, argType,
                             /*enableNameShadowing=*/true);
 }
 
 static void print(OpAsmPrinter &p, IsolatedRegionOp op) {
   p << "test.isolated_region ";
   p.printOperand(op.getOperand());
   p.shadowRegionArgs(op.getRegion(), op.getOperand());
+  p << ' ';
   p.printRegion(op.getRegion(), /*printEntryBlockArgs=*/false);
 }
 
 //===----------------------------------------------------------------------===//
 // Test SSACFGRegionOp
 //===----------------------------------------------------------------------===//
 
 RegionKind SSACFGRegionOp::getRegionKind(unsigned index) {

mlir/test/mlir-lsp-server/hover.test

// Hover on a region operation.
   "textDocument":{"uri":"test:///foo.mlir"},
   "position":{"line":0,"character":1}
 }}
 //      CHECK:  "id": 5,
 // CHECK-NEXT:  "jsonrpc": "2.0",
 // CHECK-NEXT:  "result": {
 // CHECK-NEXT:    "contents": {
 // CHECK-NEXT:      "kind": "markdown",
-// CHECK-NEXT:      "value": "\"builtin.func\" : public @foo\n\nGeneric Form:\n\n```mlir\n\"builtin.func\"() ( {\n}) {sym_name = \"foo\", type = (i1) -> ()} : () -> ()\n```\n"
+// CHECK-NEXT:      "value": "\"builtin.func\" : public @foo\n\nGeneric Form:\n\n```mlir\n\"builtin.func\"() ({\n}) {sym_name = \"foo\", type = (i1) -> ()} : () -> ()\n```\n"
 // CHECK-NEXT:    },
 // CHECK-NEXT:    "range": {
 // CHECK-NEXT:      "end": {
 // CHECK-NEXT:        "character": 4,
 // CHECK-NEXT:        "line": 0
 // CHECK-NEXT:      },
 // CHECK-NEXT:      "start": {
 // CHECK-NEXT:        "character": 0,
 // CHECK-NEXT:        "line": 0
 // CHECK-NEXT:      }
 // CHECK-NEXT:    }
 // CHECK-NEXT:  }
 // -----
 // Hover on a symbol reference.
 {"jsonrpc":"2.0","id":6,"method":"textDocument/hover","params":{
   "textDocument":{"uri":"test:///foo.mlir"},
   "position":{"line":0,"character":8}
 }}
 //      CHECK:  "id": 6,
 // CHECK-NEXT:  "jsonrpc": "2.0",
 // CHECK-NEXT:  "result": {
 // CHECK-NEXT:    "contents": {
 // CHECK-NEXT:      "kind": "markdown",
-// CHECK-NEXT:      "value": "\"builtin.func\" : public @foo\n\nGeneric Form:\n\n```mlir\n\"builtin.func\"() ( {\n}) {sym_name = \"foo\", type = (i1) -> ()} : () -> ()\n```\n"
+// CHECK-NEXT:      "value": "\"builtin.func\" : public @foo\n\nGeneric Form:\n\n```mlir\n\"builtin.func\"() ({\n}) {sym_name = \"foo\", type = (i1) -> ()} : () -> ()\n```\n"
 // CHECK-NEXT:    },
 // CHECK-NEXT:    "range": {
 // CHECK-NEXT:      "end": {
 // CHECK-NEXT:        "character": 9,
 // CHECK-NEXT:        "line": 0
 // CHECK-NEXT:      },
 // CHECK-NEXT:      "start": {
 // CHECK-NEXT:        "character": 5,
 // CHECK-NEXT:        "line": 0
 // CHECK-NEXT:      }
 // CHECK-NEXT:    }
 // CHECK-NEXT:  }
 // -----
 {"jsonrpc":"2.0","id":7,"method":"shutdown"}
 // -----
 {"jsonrpc":"2.0","method":"exit"}

mlir/test/mlir-tblgen/op-format.mlir

 
 // CHECK: test.format_multiple_variadic_operands (%[[I64]], %[[I64]], %[[I64]]), (%[[I64]], %[[I32]] : i64, i32)
 test.format_multiple_variadic_operands (%i64, %i64, %i64), (%i64, %i32 : i64, i32)
 
 //===----------------------------------------------------------------------===//
 // Format successors
 //===----------------------------------------------------------------------===//
 
-"foo.successor_test_region"() ( {
+"foo.successor_test_region"() ({
   ^bb0:
     // CHECK: test.format_successor_a_op ^bb1 {attr}
     test.format_successor_a_op ^bb1 {attr}
 
   ^bb1:
     // CHECK: test.format_successor_a_op ^bb1, ^bb2 {attr}
     test.format_successor_a_op ^bb1, ^bb2 {attr}
 

mlir/test/python/ir/operation.py

with Location.unknown(ctx):
     op1 = Operation.create(
         "custom.op1",
         results=[i32, i32],
         regions=1,
         attributes={
             "foo": StringAttr.get("foo_value"),
             "bar": StringAttr.get("bar_value"),
         })
-    # CHECK: %0:2 = "custom.op1"() ( {
+    # CHECK: %0:2 = "custom.op1"() ({
     # CHECK: }) {bar = "bar_value", foo = "foo_value"} : () -> (si32, si32)
     print(op1)
 
   # TODO: Check successors once enough infra exists to do it properly.
 
 
 # CHECK-LABEL: TEST: testOperationInsertionPoint
 @run

 @run
 def testOperationWithRegion():
   ctx = Context()
   ctx.allow_unregistered_dialects = True
   with Location.unknown(ctx):
     i32 = IntegerType.get_signed(32)
     op1 = Operation.create("custom.op1", regions=1)
     block = op1.regions[0].blocks.append(i32, i32)
-    # CHECK: "custom.op1"() ( {
+    # CHECK: "custom.op1"() ({
     # CHECK: ^bb0(%arg0: si32, %arg1: si32):  // no predecessors
     # CHECK:   "custom.terminator"() : () -> ()
     # CHECK: }) : () -> ()
     terminator = Operation.create("custom.terminator")
     ip = InsertionPoint(block)
     ip.insert(terminator)
     print(op1)
 

 # CHECK-LABEL: TEST: testInvalidOperationStrSoftFails
 @run
 def testInvalidOperationStrSoftFails():
   ctx = Context()
   with Location.unknown(ctx):
     invalid_op = create_invalid_operation()
     # Verify that we fallback to the generic printer for safety.
     # CHECK: // Verification failed, printing generic form
-    # CHECK: "builtin.module"() ( {
+    # CHECK: "builtin.module"() ({
     # CHECK: }) : () -> ()
     print(invalid_op)
     # CHECK: .verify = False
     print(f".verify = {invalid_op.operation.verify()}")
 
 
 # CHECK-LABEL: TEST: testInvalidModuleStrSoftFails
 @run