[LegalizeIntegerTypes][RISCV] Teach PromoteSetCCOperands to check sign bits of unsigned compares.

[craig.topper]

Summary

Unsigned compares work with either zero extended or sign extended
inputs just like equality comparisons. I didn't allow this when
I refactored the code in D116421 due to lack of tests. But I've
since found a simple C test case that demonstrates when this can be
useful.

[efriedma]

LGTM

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType())) {
     // The promoted values aren't zero extended, use a sext_inreg.
     LHS = SExtPromotedInteger(LHS);
     RHS = SExtPromotedInteger(RHS);
     return;
   }
 
   // Prefer to promote the comparison operand with zero extension.
 
-  // If this is an equality comparison and the width of OpL/OpR excluding the
-  // duplicated sign bits is no greater than the width of LHS/RHS, we can avoid
-  // inserting a zext_inreg operation that we might not be able to remove.
-  if (ISD::isIntEqualitySetCC(CCCode)) {
-    unsigned OpLEffectiveBits = DAG.ComputeMaxSignificantBits(OpL);
-    unsigned OpREffectiveBits = DAG.ComputeMaxSignificantBits(OpR);
-    if (OpLEffectiveBits <= LHS.getScalarValueSizeInBits() &&
-        OpREffectiveBits <= RHS.getScalarValueSizeInBits()) {
-      LHS = OpL;
-      RHS = OpR;
-      return;
-    }
-  }
+  // If the width of OpL/OpR excluding the duplicated sign bits is no greater
+  // than the width of LHS/RHS, we can avoid/ inserting a zext_inreg operation
+  // that we might not be able to remove.
 
   // Otherwise, use zext_inreg.
   LHS = ZExtPromotedInteger(LHS);
   RHS = ZExtPromotedInteger(RHS);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
   SDValue Op = GetPromotedInteger(N->getOperand(0));

llvm/test/CodeGen/RISCV/alu16.ll

 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    sltiu a0, a0, 3
 ; RV64I-NEXT:    ret
   %1 = icmp ult i16 %a, 3
   %2 = zext i1 %1 to i16
   ret i16 %2
 }
 
+; Make sure we avoid an AND, if the input of an unsigned compare is known
+; to be sign extended. This can occur due to InstCombine canonicalizing
+; x s>= 0 && x s< 10 to x u< 10.
+define i16 @sltiu_signext(i16 signext %a) nounwind {
+; RV32I-LABEL: sltiu_signext:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltiu a0, a0, 10
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sltiu_signext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sltiu a0, a0, 10
+; RV64I-NEXT:    ret
+  %1 = icmp ult i16 %a, 10
+  %2 = zext i1 %1 to i16
+  ret i16 %2
+}
+
 define i16 @xori(i16 %a) nounwind {
 ; RV32I-LABEL: xori:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xori a0, a0, 4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: xori:
 ; RV64I:       # %bb.0:

llvm/test/CodeGen/RISCV/alu8.ll

 ; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    sltiu a0, a0, 3
 ; RV64I-NEXT:    ret
   %1 = icmp ult i8 %a, 3
   %2 = zext i1 %1 to i8
   ret i8 %2
 }
 
+; Make sure we avoid an AND, if the input of an unsigned compare is known
+; to be sign extended. This can occur due to InstCombine canonicalizing
+; x s>= 0 && x s< 10 to x u< 10.
+define i8 @sltiu_signext(i8 signext %a) nounwind {
+; RV32I-LABEL: sltiu_signext:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltiu a0, a0, 10
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: sltiu_signext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sltiu a0, a0, 10
+; RV64I-NEXT:    ret
+  %1 = icmp ult i8 %a, 10
+  %2 = zext i1 %1 to i8
+  ret i8 %2
+}
+
 define i8 @xori(i8 %a) nounwind {
 ; RV32I-LABEL: xori:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xori a0, a0, 4
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: xori:
 ; RV64I:       # %bb.0: