[RISCV] Reduce repetitive codes in flw, fsw

[achieveartificialintelligence]

Summary

Trying to improve code reuse in F,D,Zfh *.td files.

[achieveartificialintelligence]

Reduce more codes.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

91

This is starting to break down the boundary between these files. You now have a D and Zfh extension predicate in the F file.

[achieveartificialintelligence]

Reduce flw,fsw

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

91

This is starting to break down the boundary between these files. You now have a D and Zfh extension predicate in the F file.

I've removed this kind of codes.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 def RISCVBuildPairF64 : SDNode<"RISCVISD::BuildPairF64", SDT_RISCVBuildPairF64>;
 def RISCVSplitF64     : SDNode<"RISCVISD::SplitF64", SDT_RISCVSplitF64>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtD] in {
-
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def FLD : RVInstI<0b011, OPC_LOAD_FP, (outs FPR64:$rd),
-                  (ins GPR:$rs1, simm12:$imm12),
-                  "fld", "$rd, ${imm12}(${rs1})">,
-          Sched<[WriteFLD64, ReadFMemBase]>;
+def FLD : FPLoad_r<0b011, "fld", FPR64, WriteFLD64>;
 
 // Operands for stores are in the order srcreg, base, offset rather than
 // reflecting the order these fields are specified in the instruction
 // encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
-                  (ins FPR64:$rs2, GPR:$rs1, simm12:$imm12),
-                   "fsd", "$rs2, ${imm12}(${rs1})">,
-          Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>;
-
-let SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in {
-def FMADD_D  : FPFMA_rrr_frm<OPC_MADD,  0b01, "fmadd.d",  FPR64>;
-def FMSUB_D  : FPFMA_rrr_frm<OPC_MSUB,  0b01, "fmsub.d",  FPR64>;
-def FNMSUB_D : FPFMA_rrr_frm<OPC_NMSUB, 0b01, "fnmsub.d", FPR64>;
-def FNMADD_D : FPFMA_rrr_frm<OPC_NMADD, 0b01, "fnmadd.d", FPR64>;
-}
+def FSD : FPStore_r<0b011, "fsd", FPR64, WriteFST64>;
 
 def : FPFMADynFrmAlias<FMADD_D,  "fmadd.d",  FPR64>;
 def : FPFMADynFrmAlias<FMSUB_D,  "fmsub.d",  FPR64>;
 def : FPFMADynFrmAlias<FNMSUB_D, "fnmsub.d", FPR64>;
 def : FPFMADynFrmAlias<FNMADD_D, "fnmadd.d", FPR64>;
 
-def FADD_D : FPALU_rr_frm<0b0000001, "fadd.d", FPR64>,
-             Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def FSUB_D : FPALU_rr_frm<0b0000101, "fsub.d", FPR64>,
-             Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
-def FMUL_D : FPALU_rr_frm<0b0001001, "fmul.d", FPR64>,
-             Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
-def FDIV_D : FPALU_rr_frm<0b0001101, "fdiv.d", FPR64>,
-             Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
-
-def        : FPALUDynFrmAlias<FADD_D, "fadd.d", FPR64>;
-def        : FPALUDynFrmAlias<FSUB_D, "fsub.d", FPR64>;
-def        : FPALUDynFrmAlias<FMUL_D, "fmul.d", FPR64>;
-def        : FPALUDynFrmAlias<FDIV_D, "fdiv.d", FPR64>;
+def : FPALUDynFrmAlias<FADD_D, "fadd.d", FPR64>;
+def : FPALUDynFrmAlias<FSUB_D, "fsub.d", FPR64>;
+def : FPALUDynFrmAlias<FMUL_D, "fmul.d", FPR64>;
+def : FPALUDynFrmAlias<FDIV_D, "fdiv.d", FPR64>;
 
 def FSQRT_D : FPUnaryOp_r_frm<0b0101101, 0b00000, FPR64, FPR64, "fsqrt.d">,
               Sched<[WriteFSqrt64, ReadFSqrt64]>;
 def         : FPUnaryOpDynFrmAlias<FSQRT_D, "fsqrt.d", FPR64, FPR64>;
 
-let SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64],
-    mayRaiseFPException = 0 in {
-def FSGNJ_D  : FPALU_rr<0b0010001, 0b000, "fsgnj.d", FPR64>;
-def FSGNJN_D : FPALU_rr<0b0010001, 0b001, "fsgnjn.d", FPR64>;
-def FSGNJX_D : FPALU_rr<0b0010001, 0b010, "fsgnjx.d", FPR64>;
-}
-
-let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
-def FMIN_D   : FPALU_rr<0b0010101, 0b000, "fmin.d", FPR64>;
-def FMAX_D   : FPALU_rr<0b0010101, 0b001, "fmax.d", FPR64>;
-}
-
 def FCVT_S_D : FPUnaryOp_r_frm<0b0100000, 0b00001, FPR32, FPR64, "fcvt.s.d">,
                Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
 def          : FPUnaryOpDynFrmAlias<FCVT_S_D, "fcvt.s.d", FPR32, FPR64>;
 
 def FCVT_D_S : FPUnaryOp_r<0b0100001, 0b00000, 0b000, FPR64, FPR32, "fcvt.d.s">,
                Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
 
-let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {
-def FEQ_D : FPCmp_rr<0b1010001, 0b010, "feq.d", FPR64>;
-def FLT_D : FPCmp_rr<0b1010001, 0b001, "flt.d", FPR64>;
-def FLE_D : FPCmp_rr<0b1010001, 0b000, "fle.d", FPR64>;
-}
-
 let mayRaiseFPException = 0 in
 def FCLASS_D : FPUnaryOp_r<0b1110001, 0b00000, 0b001, GPR, FPR64, "fclass.d">,
                Sched<[WriteFClass64, ReadFClass64]>;
 
 def FCVT_W_D : FPUnaryOp_r_frm<0b1100001, 0b00000, GPR, FPR64, "fcvt.w.d">,
                Sched<[WriteFCvtF64ToI32, ReadFCvtF64ToI32]>;
 def          : FPUnaryOpDynFrmAlias<FCVT_W_D, "fcvt.w.d", GPR, FPR64>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

def frmarg : Operand<XLenVT> {
   let PrintMethod = "printFRMArg";
   let DecoderMethod = "decodeFRMArg";
 }
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class FPLoad_r<bits<3> funct3, string opcodestr, RegisterClass rty,
+               SchedWrite sw>
+    : RVInstI<funct3, OPC_LOAD_FP, (outs rty:$rd),
+              (ins GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rd, ${imm12}(${rs1})">,
+      Sched<[sw, ReadFMemBase]>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class FPStore_r<bits<3> funct3, string opcodestr, RegisterClass rty,
+                SchedWrite sw>
+    : RVInstS<funct3, OPC_STORE_FP, (outs),
+              (ins rty:$rs2, GPR:$rs1, simm12:$imm12),
+              opcodestr, "$rs2, ${imm12}(${rs1})">,
+      Sched<[sw, ReadStoreData, ReadFMemBase]>;
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
     UseNamedOperandTable = 1, hasPostISelHook = 1 in
 class FPFMA_rrr_frm<RISCVOpcode opcode, bits<2> funct2, string opcodestr,
                     RegisterClass rty>
     : RVInstR4Frm<funct2, opcode, (outs rty:$rd),
                   (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
                   opcodestr, "$rd, $rs1, $rs2, $rs3, $frm">;
 
+multiclass FPFMA_rrr_frm_m<RISCVOpcode opcode, string opcodestr> {
+  let Predicates = [HasStdExtF],
+      SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in
+  def _S : FPFMA_rrr_frm<opcode, 0b00, opcodestr#".s", FPR32>;
+
+  let Predicates = [HasStdExtD],
+      SchedRW = [WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64] in
+  def _D : FPFMA_rrr_frm<opcode, 0b01, opcodestr#".d", FPR64>;
+
+  let Predicates = [HasStdExtZfh],
+      SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in
+  def _H : FPFMA_rrr_frm<opcode, 0b10, opcodestr#".h", FPR16>;
+}
+
 class FPFMADynFrmAlias<FPFMA_rrr_frm Inst, string OpcodeStr,
                        RegisterClass rty>
     : InstAlias<OpcodeStr#" $rd, $rs1, $rs2, $rs3",
                 (Inst rty:$rd, rty:$rs1, rty:$rs2, rty:$rs3, 0b111)>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
 class FPALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
                RegisterClass rty>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs rty:$rd),
               (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
+multiclass FPSGNJ_rr<bits<3> funct3, string OpcodeStr> {
+  defvar funct5 = 0b00100;
+  let mayRaiseFPException = 0 in {
+    let Predicates = [HasStdExtF],
+        SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32] in
+    def _S : FPALU_rr<{funct5, 0b00}, funct3, OpcodeStr#".s", FPR32>;
+
+    let Predicates = [HasStdExtD],
+        SchedRW = [WriteFSGNJ64, ReadFSGNJ64, ReadFSGNJ64] in
+    def _D : FPALU_rr<{funct5, 0b01}, funct3, OpcodeStr#".d", FPR64>;
+
+    let Predicates = [HasStdExtZfh],
+        SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16] in
+    def _H : FPALU_rr<{funct5, 0b10}, funct3, OpcodeStr#".h", FPR16>;
+  }
+}
+
+multiclass FPSGNJ_rr_m {
+  defm "" : FPSGNJ_rr<0b000, "fsgnj">;
+  defm N  : FPSGNJ_rr<0b001, "fsgnjn">;
+  defm X  : FPSGNJ_rr<0b010, "fsgnjx">;
+}
+
+multiclass FPMinMax_rr_m<bits<3> funct3, string OpcodeStr> {
+  defvar funct5 = 0b00101;
+  let Predicates = [HasStdExtF],
+      SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in
+  def _S : FPALU_rr<{funct5, 0b00}, funct3, OpcodeStr#".s", FPR32>;
+
+  let Predicates = [HasStdExtD],
+      SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in
+  def _D : FPALU_rr<{funct5, 0b01}, funct3, OpcodeStr#".d", FPR64>;
+
+  let Predicates = [HasStdExtZfh],
+      SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in
+  def _H : FPALU_rr<{funct5, 0b10}, funct3, OpcodeStr#".h", FPR16>;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
     UseNamedOperandTable = 1, hasPostISelHook = 1 in
 class FPALU_rr_frm<bits<7> funct7, string opcodestr, RegisterClass rty>
     : RVInstRFrm<funct7, OPC_OP_FP, (outs rty:$rd),
                  (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
                   "$rd, $rs1, $rs2, $frm">;
 
+multiclass FPALU_rr_frm_m<bits<5> funct5, string opcodestr> {
+  let Predicates = [HasStdExtF] in
+  def _S : FPALU_rr_frm<{funct5, 0b00}, opcodestr#".s", FPR32>,
+           Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
+
+  let Predicates = [HasStdExtD] in
+  def _D : FPALU_rr_frm<{funct5, 0b01}, opcodestr#".d", FPR64>,
+           Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
+
+  let Predicates = [HasStdExtZfh] in
+  def _H : FPALU_rr_frm<{funct5, 0b10}, opcodestr#".h", FPR16>,
+           Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
+}
+
+multiclass FPMUL_rr_frm_m {
+  defvar funct5 = 0b00010;
+  let Predicates = [HasStdExtF] in
+  def _S : FPALU_rr_frm<{funct5, 0b00}, "fmul.s", FPR32>,
+          Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
+
+  let Predicates = [HasStdExtD] in
+  def _D : FPALU_rr_frm<{funct5, 0b01}, "fmul.d", FPR64>,
+          Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
+
+  let Predicates = [HasStdExtZfh] in
+  def _H : FPALU_rr_frm<{funct5, 0b10}, "fmul.h", FPR16>,
+          Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>;
+}
+
+multiclass FPDIV_rr_frm_m {
+  defvar funct5 = 0b00011;
+  let Predicates = [HasStdExtF] in
+  def _S : FPALU_rr_frm<{funct5, 0b00}, "fdiv.s", FPR32>,
+           Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
+
+  let Predicates = [HasStdExtD] in
+  def _D : FPALU_rr_frm<{funct5, 0b01}, "fdiv.d", FPR64>,
+           Sched<[WriteFDiv64, ReadFDiv64, ReadFDiv64]>;
+
+  let Predicates = [HasStdExtZfh] in
+  def _H : FPALU_rr_frm<{funct5, 0b10}, "fdiv.h", FPR16>,
+           Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>;
+}
+
 class FPALUDynFrmAlias<FPALU_rr_frm Inst, string OpcodeStr,
                        RegisterClass rty>
     : InstAlias<OpcodeStr#" $rd, $rs1, $rs2",
                 (Inst rty:$rd, rty:$rs1, rty:$rs2, 0b111)>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
 class FPUnaryOp_r<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
                   RegisterClass rdty, RegisterClass rs1ty, string opcodestr>
: InstAlias<OpcodeStr#" $rd, $rs1",
                 (Inst rdty:$rd, rs1ty:$rs1, 0b111)>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1 in
 class FPCmp_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
                RegisterClass rty>
     : RVInstR<funct7, funct3, OPC_OP_FP, (outs GPR:$rd),
               (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
+multiclass FPCmp_rr_m<bits<3> funct3, string opcodestr> {
+  defvar funct5 = 0b10100;
+  let Predicates = [HasStdExtF],
+      SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in
+  def _S : FPCmp_rr<{funct5, 0b00}, funct3, opcodestr#".s", FPR32>;
+
+  let Predicates = [HasStdExtD],
+      SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in
+  def _D : FPCmp_rr<{funct5, 0b01}, funct3, opcodestr#".d", FPR64>;
+
+  let Predicates = [HasStdExtZfh],
+      SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in
+  def _H : FPCmp_rr<{funct5, 0b10}, funct3, opcodestr#".h", FPR16>;
+}
+
+//===----------------------------------------------------------------------===//
+// Multiclass Instructions
+//===----------------------------------------------------------------------===//
+
+defm FMADD  : FPFMA_rrr_frm_m<OPC_MADD,  "fmadd">;
+defm FMSUB  : FPFMA_rrr_frm_m<OPC_MSUB,  "fmsub">;
+defm FNMSUB : FPFMA_rrr_frm_m<OPC_NMSUB, "fnmsub">;
+defm FNMADD : FPFMA_rrr_frm_m<OPC_NMADD, "fnmadd">;
+
+defm FADD : FPALU_rr_frm_m<0b00000, "fadd">;
+defm FSUB : FPALU_rr_frm_m<0b00001, "fsub">;
+defm FMUL : FPMUL_rr_frm_m;
+defm FDIV : FPDIV_rr_frm_m;
+
+defm FSGNJ : FPSGNJ_rr_m;
+
+defm FMIN : FPMinMax_rr_m<0b000, "fmin">;
+defm FMAX : FPMinMax_rr_m<0b001, "fmax">;
+
+defm FEQ : FPCmp_rr_m<0b010, "feq">;
+defm FLT : FPCmp_rr_m<0b001, "flt">;
+defm FLE : FPCmp_rr_m<0b000, "fle">;
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtF] in {
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
-                  (ins GPR:$rs1, simm12:$imm12),
-                   "flw", "$rd, ${imm12}(${rs1})">,
-          Sched<[WriteFLD32, ReadFMemBase]>;
+def FLW : FPLoad_r<0b010, "flw", FPR32, WriteFLD32>;
 
 // Operands for stores are in the order srcreg, base, offset rather than
 // reflecting the order these fields are specified in the instruction
 // encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
-                  (ins FPR32:$rs2, GPR:$rs1, simm12:$imm12),
-                   "fsw", "$rs2, ${imm12}(${rs1})">,
-          Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>;
-
-let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
-def FMADD_S  : FPFMA_rrr_frm<OPC_MADD,  0b00, "fmadd.s",  FPR32>;
-def FMSUB_S  : FPFMA_rrr_frm<OPC_MSUB,  0b00, "fmsub.s",  FPR32>;
-def FNMSUB_S : FPFMA_rrr_frm<OPC_NMSUB, 0b00, "fnmsub.s", FPR32>;
-def FNMADD_S : FPFMA_rrr_frm<OPC_NMADD, 0b00, "fnmadd.s", FPR32>;
-}
+def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
 
 def : FPFMADynFrmAlias<FMADD_S,  "fmadd.s",  FPR32>;
 def : FPFMADynFrmAlias<FMSUB_S,  "fmsub.s",  FPR32>;
 def : FPFMADynFrmAlias<FNMSUB_S, "fnmsub.s", FPR32>;
 def : FPFMADynFrmAlias<FNMADD_S, "fnmadd.s", FPR32>;
 
-def FADD_S : FPALU_rr_frm<0b0000000, "fadd.s", FPR32>,
-             Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def FSUB_S : FPALU_rr_frm<0b0000100, "fsub.s", FPR32>,
-             Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
-def FMUL_S : FPALU_rr_frm<0b0001000, "fmul.s", FPR32>,
-             Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
-def FDIV_S : FPALU_rr_frm<0b0001100, "fdiv.s", FPR32>,
-             Sched<[WriteFDiv32, ReadFDiv32, ReadFDiv32]>;
-
-def        : FPALUDynFrmAlias<FADD_S, "fadd.s", FPR32>;
-def        : FPALUDynFrmAlias<FSUB_S, "fsub.s", FPR32>;
-def        : FPALUDynFrmAlias<FMUL_S, "fmul.s", FPR32>;
-def        : FPALUDynFrmAlias<FDIV_S, "fdiv.s", FPR32>;
+def : FPALUDynFrmAlias<FADD_S, "fadd.s", FPR32>;
+def : FPALUDynFrmAlias<FSUB_S, "fsub.s", FPR32>;
+def : FPALUDynFrmAlias<FMUL_S, "fmul.s", FPR32>;
+def : FPALUDynFrmAlias<FDIV_S, "fdiv.s", FPR32>;
 
 def FSQRT_S : FPUnaryOp_r_frm<0b0101100, 0b00000, FPR32, FPR32, "fsqrt.s">,
               Sched<[WriteFSqrt32, ReadFSqrt32]>;
 def         : FPUnaryOpDynFrmAlias<FSQRT_S, "fsqrt.s", FPR32, FPR32>;
 
-let SchedRW = [WriteFSGNJ32, ReadFSGNJ32, ReadFSGNJ32],
-    mayRaiseFPException = 0 in {
-def FSGNJ_S  : FPALU_rr<0b0010000, 0b000, "fsgnj.s", FPR32>;
-def FSGNJN_S : FPALU_rr<0b0010000, 0b001, "fsgnjn.s", FPR32>;
-def FSGNJX_S : FPALU_rr<0b0010000, 0b010, "fsgnjx.s", FPR32>;
-}
-
-let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {
-def FMIN_S   : FPALU_rr<0b0010100, 0b000, "fmin.s", FPR32>;
-def FMAX_S   : FPALU_rr<0b0010100, 0b001, "fmax.s", FPR32>;
-}
-
 def FCVT_W_S : FPUnaryOp_r_frm<0b1100000, 0b00000, GPR, FPR32, "fcvt.w.s">,
                Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
 def          : FPUnaryOpDynFrmAlias<FCVT_W_S, "fcvt.w.s", GPR, FPR32>;
 
 def FCVT_WU_S : FPUnaryOp_r_frm<0b1100000, 0b00001, GPR, FPR32, "fcvt.wu.s">,
                 Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
 def           : FPUnaryOpDynFrmAlias<FCVT_WU_S, "fcvt.wu.s", GPR, FPR32>;
 
 let mayRaiseFPException = 0 in
 def FMV_X_W : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR32, "fmv.x.w">,
               Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 
-let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in {
-def FEQ_S : FPCmp_rr<0b1010000, 0b010, "feq.s", FPR32>;
-def FLT_S : FPCmp_rr<0b1010000, 0b001, "flt.s", FPR32>;
-def FLE_S : FPCmp_rr<0b1010000, 0b000, "fle.s", FPR32>;
-}
-
 let mayRaiseFPException = 0 in
 def FCLASS_S : FPUnaryOp_r<0b1110000, 0b00000, 0b001, GPR, FPR32, "fclass.s">,
                Sched<[WriteFClass32, ReadFClass32]>;
 
 def FCVT_S_W : FPUnaryOp_r_frm<0b1101000, 0b00000, FPR32, GPR, "fcvt.s.w">,
                Sched<[WriteFCvtI32ToF32, ReadFCvtI32ToF32]>;
 def          : FPUnaryOpDynFrmAlias<FCVT_S_W, "fcvt.s.w", FPR32, GPR>;
 

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

 def riscv_fmv_x_anyexth
     : SDNode<"RISCVISD::FMV_X_ANYEXTH", SDT_RISCVFMV_X_ANYEXTH>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfhmin] in {
-let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-def FLH : RVInstI<0b001, OPC_LOAD_FP, (outs FPR16:$rd),
-                  (ins GPR:$rs1, simm12:$imm12),
-                   "flh", "$rd, ${imm12}(${rs1})">,
-          Sched<[WriteFLD16, ReadFMemBase]>;
+def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>;
 
 // Operands for stores are in the order srcreg, base, offset rather than
 // reflecting the order these fields are specified in the instruction
 // encoding.
-let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
-def FSH : RVInstS<0b001, OPC_STORE_FP, (outs),
-                  (ins FPR16:$rs2, GPR:$rs1, simm12:$imm12),
-                   "fsh", "$rs2, ${imm12}(${rs1})">,
-          Sched<[WriteFST16, ReadStoreData, ReadFMemBase]>;
+def FSH : FPStore_r<0b001, "fsh", FPR16, WriteFST16>;
 } // Predicates = [HasStdExtZfhmin]
 
 let Predicates = [HasStdExtZfh] in {
-let SchedRW = [WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16] in {
-def FMADD_H  : FPFMA_rrr_frm<OPC_MADD,  0b10, "fmadd.h",  FPR16>;
-def FMSUB_H  : FPFMA_rrr_frm<OPC_MSUB,  0b10, "fmsub.h",  FPR16>;
-def FNMSUB_H : FPFMA_rrr_frm<OPC_NMSUB, 0b10, "fnmsub.h", FPR16>;
-def FNMADD_H : FPFMA_rrr_frm<OPC_NMADD, 0b10, "fnmadd.h", FPR16>;
-}
-
 def : FPFMADynFrmAlias<FMADD_H,  "fmadd.h",  FPR16>;
 def : FPFMADynFrmAlias<FMSUB_H,  "fmsub.h",  FPR16>;
 def : FPFMADynFrmAlias<FNMSUB_H, "fnmsub.h", FPR16>;
 def : FPFMADynFrmAlias<FNMADD_H, "fnmadd.h", FPR16>;
 
-def FADD_H : FPALU_rr_frm<0b0000010, "fadd.h", FPR16>,
-             Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
-def FSUB_H : FPALU_rr_frm<0b0000110, "fsub.h", FPR16>,
-             Sched<[WriteFALU16, ReadFALU16, ReadFALU16]>;
-def FMUL_H : FPALU_rr_frm<0b0001010, "fmul.h", FPR16>,
-             Sched<[WriteFMul16, ReadFMul16, ReadFMul16]>;
-def FDIV_H : FPALU_rr_frm<0b0001110, "fdiv.h", FPR16>,
-             Sched<[WriteFDiv16, ReadFDiv16, ReadFDiv16]>;
-
-def        : FPALUDynFrmAlias<FADD_H, "fadd.h", FPR16>;
-def        : FPALUDynFrmAlias<FSUB_H, "fsub.h", FPR16>;
-def        : FPALUDynFrmAlias<FMUL_H, "fmul.h", FPR16>;
-def        : FPALUDynFrmAlias<FDIV_H, "fdiv.h", FPR16>;
+def : FPALUDynFrmAlias<FADD_H, "fadd.h", FPR16>;
+def : FPALUDynFrmAlias<FSUB_H, "fsub.h", FPR16>;
+def : FPALUDynFrmAlias<FMUL_H, "fmul.h", FPR16>;
+def : FPALUDynFrmAlias<FDIV_H, "fdiv.h", FPR16>;
 
 def FSQRT_H : FPUnaryOp_r_frm<0b0101110, 0b00000, FPR16, FPR16, "fsqrt.h">,
               Sched<[WriteFSqrt16, ReadFSqrt16]>;
 def         : FPUnaryOpDynFrmAlias<FSQRT_H, "fsqrt.h", FPR16, FPR16>;
 
-let SchedRW = [WriteFSGNJ16, ReadFSGNJ16, ReadFSGNJ16],
-    mayRaiseFPException = 0 in {
-def FSGNJ_H  : FPALU_rr<0b0010010, 0b000, "fsgnj.h", FPR16>;
-def FSGNJN_H : FPALU_rr<0b0010010, 0b001, "fsgnjn.h", FPR16>;
-def FSGNJX_H : FPALU_rr<0b0010010, 0b010, "fsgnjx.h", FPR16>;
-}
-
-let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {
-def FMIN_H   : FPALU_rr<0b0010110, 0b000, "fmin.h", FPR16>;
-def FMAX_H   : FPALU_rr<0b0010110, 0b001, "fmax.h", FPR16>;
-}
-
 def FCVT_W_H : FPUnaryOp_r_frm<0b1100010, 0b00000, GPR, FPR16, "fcvt.w.h">,
                Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;
 def          : FPUnaryOpDynFrmAlias<FCVT_W_H, "fcvt.w.h", GPR, FPR16>;
 
 def FCVT_WU_H : FPUnaryOp_r_frm<0b1100010, 0b00001, GPR, FPR16, "fcvt.wu.h">,
                 Sched<[WriteFCvtF16ToI32, ReadFCvtF16ToI32]>;
 def           : FPUnaryOpDynFrmAlias<FCVT_WU_H, "fcvt.wu.h", GPR, FPR16>;
 

 def FMV_X_H : FPUnaryOp_r<0b1110010, 0b00000, 0b000, GPR, FPR16, "fmv.x.h">,
               Sched<[WriteFMovF16ToI16, ReadFMovF16ToI16]>;
 
 let mayRaiseFPException = 0 in
 def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,
               Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>;
 } // Predicates = [HasStdExtZfhmin]
 
-let Predicates = [HasStdExtZfh] in {
-
-let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {
-def FEQ_H : FPCmp_rr<0b1010010, 0b010, "feq.h", FPR16>;
-def FLT_H : FPCmp_rr<0b1010010, 0b001, "flt.h", FPR16>;
-def FLE_H : FPCmp_rr<0b1010010, 0b000, "fle.h", FPR16>;
-}
-
+let Predicates = [HasStdExtZfh] in
 let mayRaiseFPException = 0 in
 def FCLASS_H : FPUnaryOp_r<0b1110010, 0b00000, 0b001, GPR, FPR16, "fclass.h">,
                Sched<[WriteFClass16, ReadFClass16]>;
-} // Predicates = [HasStdExtZfh]
 
 let Predicates = [HasStdExtZfh, IsRV64] in {
 def FCVT_L_H  : FPUnaryOp_r_frm<0b1100010, 0b00010, GPR, FPR16, "fcvt.l.h">,
                 Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;
 def           : FPUnaryOpDynFrmAlias<FCVT_L_H, "fcvt.l.h", GPR, FPR16>;
 
 def FCVT_LU_H  : FPUnaryOp_r_frm<0b1100010, 0b00011, GPR, FPR16, "fcvt.lu.h">,
                  Sched<[WriteFCvtF16ToI64, ReadFCvtF16ToI64]>;