[RISCV] Align odd address in assemble code

[StephenFan]

Summary

In the past, llvm riscv assember can't align odd address. It can only align address which is multiple of 2 or 4.

In this patch, first insert zeros to make the address is 2 or 4 align, then utilize the nop instruction to align the address to the given align value.

[jrtc27]

llvm/test/MC/RISCV/align-odd.s

2

+relax? +c? (and maybe riscv32?)

3

Pipe to llvm-objdump, don't needlessly create temporary files

5

Weird formatting in this whole block, and I don't see why we need this particular CHECK line

13

.text is the default

Don't indent assembly when there are no labels involved

15

This only ever tests odd->even, it doesn't test 1mod4->multiple of 4 for !RVC

[jrtc27]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

360–363

IALIGN is the architecturally-defined term for the minimum instruction alignment, and is precisely this

363

You don't need the if any more, write_zeros can happily take in 0 as the length (see AArch64 that does this, for example). Probably worth copying the comment from there too; it's also present for AMDGPU.

[StephenFan]

Address jrtc27's comments. Thank you, @jrtc27!

[jrtc27]

llvm/test/MC/RISCV/align-odd.s

19

Pad after the colon not before the CHECK prefix

20

Why a two space gap?

46

These are still broken, and we should probably be checking where the R_RISCV_RELAX is pointing

69

Double blank line

78

Double blank line

[MaskRay]

llvm/test/MC/RISCV/align-odd.s

20

It will make sense when the address takes 2 digits, which can happen if the test gets more instructions. So I won't disallow two spaces here

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,
   return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
 }
 
 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
                                    const MCSubtargetInfo *STI) const {
   bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC];
   unsigned MinNopLen = HasStdExtC ? 2 : 4;
 
-  if ((Count % MinNopLen) != 0)
-    return false;
+  // If the count is not 4-byte (or 2 byte if HasStdExtC) aligned, we must be writing data into the text
+  // section (otherwise we have unaligned instructions, and thus have far
+  // bigger problems), so just write zeros instead.
+  OS.write_zeros(Count % MinNopLen);
 
   // The canonical nop on RISC-V is addi x0, x0, 0.
   for (; Count >= 4; Count -= 4)
     OS.write("\x13\0\0\0", 4);
 
   // The canonical nop on RVC is c.nop.
   if (Count && HasStdExtC)
     OS.write("\x01\0", 2);

llvm/test/MC/RISCV/align-odd.s

+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,-relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV64-C-EXT-NORELAX %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV64-NORELAX %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,-relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV32-C-EXT-NORELAX %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV32-NORELAX %s
+
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV64-C-EXT-RELAX %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV64-RELAX %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV32-C-EXT-RELAX %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+relax < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=RV32-RELAX %s
+
+#      RV64-C-EXT-NORELAX:  0: 01 00
+# RV64-C-EXT-NORELAX-NEXT:  2: 00 00
+# RV64-C-EXT-NORELAX-NEXT:  4: 00 00
+# RV64-C-EXT-NORELAX-NEXT:  6: 01 00
+# RV64-C-EXT-NORELAX-NEXT:  8: 2a 95
+
+#      RV64-NORELAX:  0: 01 00
+# RV64-NORELAX-NEXT:  2: 00 00
+# RV64-NORELAX-NEXT:  4: 00 00
+# RV64-NORELAX-NEXT:  6: 00 00
+# RV64-NORELAX-NEXT:  8: 33 05 a5 00
+
+# RV32-C-EXT-NORELAX:  0: 01 00
+# RV32-C-EXT-NORELAX-NEXT:  2: 00 00
+# RV32-C-EXT-NORELAX-NEXT:  4: 00 00
+# RV32-C-EXT-NORELAX-NEXT:  6: 01 00
+# RV32-C-EXT-NORELAX-NEXT:  8: 2a 95
+
+#      RV32-NORELAX:  0: 01 00
+# RV32-NORELAX-NEXT:  2: 00 00
+# RV32-NORELAX-NEXT:  4: 00 00
+# RV32-NORELAX-NEXT:  6: 00 00
+# RV32-NORELAX-NEXT:  8: 33 05 a5 00
+
+
+#      RV64-C-EXT-RELAX:  0: 01 00
+# RV64-C-EXT-RELAX-NEXT:  2: 00 00
+# RV64-C-EXT-RELAX-NEXT:  4: 00 13
+# RV64-C-EXT-RELAX-NEXT:  6: 00 00
+# RV64-C-EXT-RELAX-NEXT:  8: 00 01
+# RV64-C-EXT-RELAX-NEXT:  a: 00 2a
+# RV64-C-EXT-RELAX-NEXT:  c: 95
+
+
+#      RV64-RELAX:  0: 01 00
+# RV64-RELAX-NEXT:  2: 00 00
+# RV64-RELAX-NEXT:  4: 00 13
+# RV64-RELAX-NEXT:  6: 00 00
+# RV64-RELAX-NEXT:  8: 00 33
+# RV64-RELAX-NEXT:  a: 05 a5
+# RV64-RELAX-NEXT:  c: 00
+
+#      RV32-C-EXT-RELAX:  0: 01 00
+# RV32-C-EXT-RELAX-NEXT:  2: 00 00
+# RV32-C-EXT-RELAX-NEXT:  4: 00 13
+# RV32-C-EXT-RELAX-NEXT:  6: 00 00
+# RV32-C-EXT-RELAX-NEXT:  8: 00 01
+# RV32-C-EXT-RELAX-NEXT:  a: 00 2a
+# RV32-C-EXT-RELAX-NEXT:  c: 95
+
+
+#      RV32-RELAX:  0: 01 00
+# RV32-RELAX-NEXT:  2: 00 00
+# RV32-RELAX-NEXT:  4: 00 13
+# RV32-RELAX-NEXT:  6: 00 00
+# RV32-RELAX-NEXT:  8: 00 33
+# RV32-RELAX-NEXT:  a: 05 a5
+# RV32-RELAX-NEXT:  c: 00
+
+
+.byte 1
+.word 0
+.p2align 3
+add a0, a0, a0