[CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors

[david-arm]

Summary

I tried to exercise the existing combine patterns in performConcatVectorsCombine
for scalable vectors and at the moment it doesn't seem possible. Parts of
the code currently assume we're dealing with fixed-width vectors with calls
to getVectorNumElements(), therefore I've decided to simply bail out early
for scalable vectors.

[sdesmalen]

This is missing a test?

[david-arm]

• Added test to an existing file.

[sdesmalen]

llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll

53

It's a bit of a pity that we can't properly express a concat_vector directly. I tried creating a test using vector.insert in the hope that would lead to a concat_vector, without success.

Can you maybe add a comment explaining why this test relates to a 'concat_vector' issue ?

[david-arm]

• Added comment to the test.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 static SDValue performConcatVectorsCombine(SDNode *N,
                                            TargetLowering::DAGCombinerInfo &DCI,
                                            SelectionDAG &DAG) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
   unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
 
+  if (VT.isScalableVector())
+    return SDValue();
+
   // Optimize concat_vectors of truncated vectors, where the intermediate
   // type is illegal, to avoid said illegality,  e.g.,
   //   (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
   //                          (v2i16 (truncate (v2i64)))))
   // ->
   //   (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
   //                                    (v4i32 (bitcast (v2i64))),
   //                                    <0, 2, 4, 6>)))

llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll

 ; CHECK-NEXT: xtn2.8h v0, v1
 ; CHECK-NEXT: ret
   %at = trunc <4 x i32> %a to <4 x i16>
   %bt = trunc <4 x i32> %b to <4 x i16>
   %shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %shuffle
 }
 
+
+; The concat_vectors operation in this test is introduced when splitting
+; the fptrunc operation due to the split <vscale x 4 x double> input operand.
+define void @test_concat_fptrunc_v4f64_to_v4f32(<vscale x 4 x float>* %ptr) #1 {
+entry:
+; CHECK-LABEL: test_concat_fptrunc_v4f64_to_v4f32:
+; CHECK:       fmov    z0.d, #1.00000000
+; CHECK-NEXT:  ptrue   p0.d
+; CHECK-NEXT:  fcvt    z0.s, p0/m, z0.d
+; CHECK-NEXT:  ptrue   p0.s
+; CHECK-NEXT:  uzp1    z0.s, z0.s, z0.s
+; CHECK-NEXT:  st1w    { z0.s }, p0, [x0]
+; CHECK-NEXT:  ret
+  %0 = shufflevector <vscale x 4 x double> insertelement (<vscale x 4 x double> poison, double 1.000000e+00, i32 0), <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
+  %1 = fptrunc <vscale x 4 x double> %0 to <vscale x 4 x float>
+  store <vscale x 4 x float> %1, <vscale x 4 x float>* %ptr, align 4
+  ret void
+}
+
 attributes #0 = { nounwind }
+attributes #1 = { "target-features"="+sve" }