[CodeGen][AArch64] Bail out in performConcatVectorsCombine for scalable vectors

[david-arm]

Summary

I tried to exercise the existing combine patterns in performConcatVectorsCombine
for scalable vectors and at the moment it doesn't seem possible. Parts of
the code currently assume we're dealing with fixed-width vectors with calls
to getVectorNumElements(), therefore I've decided to simply bail out early
for scalable vectors.

[sdesmalen]

This is missing a test?

[david-arm]

• Added test to an existing file.

[sdesmalen]

llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll

53 ↗

(On Diff #389937)

It's a bit of a pity that we can't properly express a concat_vector directly. I tried creating a test using vector.insert in the hope that would lead to a concat_vector, without success.

Can you maybe add a comment explaining why this test relates to a 'concat_vector' issue ?

[david-arm]

• Added comment to the test.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 static SDValue performConcatVectorsCombine(SDNode *N,
                                            TargetLowering::DAGCombinerInfo &DCI,
                                            SelectionDAG &DAG) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
   unsigned N0Opc = N0->getOpcode(), N1Opc = N1->getOpcode();
 
+  if (VT.isScalableVector())
+    return SDValue();
+
   // Optimize concat_vectors of truncated vectors, where the intermediate
   // type is illegal, to avoid said illegality,  e.g.,
   //   (v4i16 (concat_vectors (v2i16 (truncate (v2i64))),
   //                          (v2i16 (truncate (v2i64)))))
   // ->
   //   (v4i16 (truncate (vector_shuffle (v4i32 (bitcast (v2i64))),
   //                                    (v4i32 (bitcast (v2i64))),
   //                                    <0, 2, 4, 6>)))