[lld][ELF] Support for R_ARM_THM_JUMP8

[phosek]

Summary

This change implements support for R_ARM_THM_JUMP8 relocation in
addition to R_ARM_THM_JUMP11 which is already supported by LLD.

[MaskRay]

There should be a regular test in arm-thumb-narrow-branch-check.s.

LGTM, but I am unfamiliar with ARM so it'd be good checked by Peter as well.

[peter.smith]

Code looks good to me.

Will probably need to use the .reloc directive in a regular test. Most assemblers don't emit the relocation for the Thumb conditional branch as it is so small in range that going out of the section usually means it will be out of range of its target. I think something like:

.text
.thumb
.global undefined
.inst.n 0xd0fe
.reloc 0, R_ARM_THM_JUMP8, undefined

Should work, this produces:

00000000 <$t.0>:
       0: fe d0         beq     0x0 <$t.0>              @ imm = #-4
                        00000000:  R_ARM_THM_JUMP8      undefined

lld/test/ELF/arm-thumb-undefined-weak-narrow.test

27

The R_ARM_THM_JUMP8 is for the thumb conditional branch. I think that for a jump to a symbol this should be with little-endian fed0 for beq undefined_weak

0xd	0x0	0xfe
1101	cond	imm8

Where the imm8 is -4 (Thumb PC-bias).

[phosek]

I've added regular test in arm-thumb-narrow-branch-check.s, let me know if this makes sense.

[peter.smith]

Thanks for the updates LGTM. In theory we can now rewrite arm-thumb-narrow-branch-check.s using .reloc but that could be done in a future patch.

lld/test/ELF/Inputs/arm-thumb-narrow-branch.s

4

R_ARM_THM_JUMP8 has an even smaller range of +- 256 bytes, but I don't think it is worth changing the comment as the point still stands.

lld/ELF/Arch/ARM.cpp

RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
                         const uint8_t *loc) const {
   switch (type) {
   case R_ARM_ABS32:
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVT_ABS:
   case R_ARM_THM_MOVW_ABS_NC:
   case R_ARM_THM_MOVT_ABS:
     return R_ABS;
+  case R_ARM_THM_JUMP8:
   case R_ARM_THM_JUMP11:
     return R_PC;
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_PREL31:
   case R_ARM_THM_JUMP19:
void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   }
     LLVM_FALLTHROUGH;
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
     checkInt(loc, val, 26, rel);
     write32le(loc, (read32le(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
     break;
+  case R_ARM_THM_JUMP8:
+    // We do a 9 bit check because val is right-shifted by 1 bit.
+    checkInt(loc, val, 9, rel);
+    write16le(loc, (read32le(loc) & 0xff00) | ((val >> 1) & 0x00ff));
+    break;
   case R_ARM_THM_JUMP11:
+    // We do a 12 bit check because val is right-shifted by 1 bit.
     checkInt(loc, val, 12, rel);
     write16le(loc, (read32le(loc) & 0xf800) | ((val >> 1) & 0x07ff));
     break;
   case R_ARM_THM_JUMP19:
     // Encoding T3: Val = S:J2:J1:imm6:imm11:0
     checkInt(loc, val, 21, rel);
     write16le(loc,
               (read16le(loc) & 0xfbc0) |   // opcode cond
case R_ARM_TLS_TPOFF32:
     return SignExtend64<32>(read32le(buf));
   case R_ARM_PREL31:
     return SignExtend64<31>(read32le(buf));
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
     return SignExtend64<26>(read32le(buf) << 2);
+  case R_ARM_THM_JUMP8:
+    return SignExtend64<9>(read16le(buf) << 1);
   case R_ARM_THM_JUMP11:
     return SignExtend64<12>(read16le(buf) << 1);
   case R_ARM_THM_JUMP19: {
     // Encoding T3: A = S:J2:J1:imm10:imm6:0
     uint16_t hi = read16le(buf);
     uint16_t lo = read16le(buf + 2);
     return SignExtend64<20>(((hi & 0x0400) << 10) | // S
                             ((lo & 0x0800) << 8) |  // J2

lld/ELF/InputSection.cpp

 // this context is the address of the place P. A further special case is that
 // branch relocations to an undefined weak reference resolve to the next
 // instruction.
 static uint32_t getARMUndefinedRelativeWeakVA(RelType type, uint32_t a,
                                               uint32_t p) {
   switch (type) {
   // Unresolved branch relocations to weak references resolve to next
   // instruction, this will be either 2 or 4 bytes on from P.
+  case R_ARM_THM_JUMP8:
   case R_ARM_THM_JUMP11:
     return p + 2 + a;
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_PREL31:
   case R_ARM_THM_JUMP19:

lld/test/ELF/Inputs/arm-thumb-narrow-branch.s

 // This input must be assembled by the GNU assembler, as llvm-mc does not emit
-// the R_ARM_JUMP11 relocation for a Thumb narrow branch. This is permissible
-// by the ABI for the ARM architecture as the range of the Thumb narrow branch
-// is short enough (+- 2048 bytes) that widespread use would be impractical.
+// the R_ARM_THM_JUMP11 and R_ARM_THM_JUMP8 relocations for a Thumb narrow
+// branch. This is permissible by the ABI for the ARM architecture as the range
+// of the Thumb narrow branch is short enough (+- 2048 bytes) that widespread
+// use would be impractical.
 //
 // The test case will use a pre compiled object arm-thumb-narrow-branch.o
  .syntax unified
  .section .caller, "ax",%progbits
  .thumb
  .align 2
  .type callers,%function
  .globl callers
 callers:
  b.n callee_low_far
  b.n callee_low
  b.n callee_high
  b.n callee_high_far
+ beq.n callee_low_near
+ beq.n callee_low
+ beq.n callee_high
+ beq.n callee_high_near
  bx lr

lld/test/ELF/arm-thumb-narrow-branch-check.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=thumbv7a-none-linux-gnueabi %s -o %t
 // RUN: echo "SECTIONS { \
 // RUN:          . = SIZEOF_HEADERS; \
-// RUN:          .R_ARM_PC11_1 : { *(.R_ARM_PC11_1) } \
+// RUN:          .callee_low : { *(.callee_low) } \
 // RUN:          .caller : { *(.caller) } \
-// RUN:          .R_ARM_PC11_2 : { *(.R_ARM_PC11_2) } \
+// RUN:          .callee_high : { *(.callee_high) } \
 // RUN:          .text : { *(.text) } } " > %t.script
 // RUN: ld.lld --script %t.script %t %S/Inputs/arm-thumb-narrow-branch.o -o %t2
 // RUN: llvm-objdump -d %t2 | FileCheck %s
 
-// Test the R_ARM_PC11 relocation which is used with the narrow encoding of B.N
-// the source of these relocations is a binary file arm-thumb-narrow-branch.o
+// Test the R_ARM_THM_JUMP11 and R_ARM_THM_JUMP8 relocations which are used
+// with the narrow encoding of B.N and BEQ.N.
+//
+// The source of these relocations is a binary file arm-thumb-narrow-branch.o
 // which has been assembled with the GNU assembler as llvm-mc doesn't emit it
 // as the range of +-2048 bytes is too small to be practically useful for out
 // of section branches.
  .syntax unified
 
 .global callee_low_far
 .type callee_low_far,%function
 callee_low_far = 0x809
 
- .section .R_ARM_PC11_1,"ax",%progbits
+.global callee_low_near
+.type callee_low_near,%function
+callee_low_near = 0xfff
+
+ .section .callee_low,"ax",%progbits
  .thumb
  .balign 0x1000
  .type callee_low,%function
  .globl callee_low
 callee_low:
  bx lr
 
  .text
  .align 2
  .thumb
  .globl _start
  .type _start, %function
 _start:
  bl callers
  bx lr
 
- .section .R_ARM_PC11_2,"ax",%progbits
+ .section .callee_high,"ax",%progbits
  .thumb
  .align 2
  .type callee_high,%function
  .globl callee_high
 callee_high:
  bx lr
 
+.global callee_high_near
+.type callee_high_near,%function
+callee_high_near = 0x10ff
+
 .global callee_high_far
 .type callee_high_far,%function
 callee_high_far = 0x180d
 
-// CHECK: Disassembly of section .R_ARM_PC11_1:
+// CHECK: Disassembly of section .callee_low:
 // CHECK-EMPTY:
 // CHECK-NEXT: <callee_low>:
 // CHECK-NEXT:    1000:       70 47   bx      lr
 // CHECK-EMPTY:
 // CHECK-NEXT: Disassembly of section .caller:
 // CHECK-EMPTY:
 // CHECK-NEXT: <callers>:
 /// callee_low_far = 0x809
 // CHECK-NEXT:    1004:       00 e4   b       0x808
 // CHECK-NEXT:    1006:       fb e7   b       0x1000 <callee_low>
-// CHECK-NEXT:    1008:       02 e0   b       0x1010 <callee_high>
+// CHECK-NEXT:    1008:       06 e0   b       0x1018 <callee_high>
 /// callee_high_far = 0x180d
 // CHECK-NEXT:    100a:       ff e3   b       0x180c
-// CHECK-NEXT:    100c:       70 47   bx      lr
-// CHECK-NEXT:    100e:       00 bf   nop
+/// callee_low_near = 0xfff
+// CHECK-NEXT:    100c:       f7 d0   beq     0xffe
+// CHECK-NEXT:    100e:       f7 d0   beq     0x1000 <callee_low>
+// CHECK-NEXT:    1010:       02 d0   beq     0x1018 <callee_high>
+/// callee_high_near = 0x10ff
+// CHECK-NEXT:    1012:       74 d0   beq     0x10fe
+// CHECK-NEXT:    1014:       70 47   bx      lr
+// CHECK-NEXT:    1016:       c0 46   mov     r8, r8
 // CHECK-EMPTY:
-// CHECK-NEXT: Disassembly of section .R_ARM_PC11_2:
+// CHECK-NEXT: Disassembly of section .callee_high:
 // CHECK-EMPTY:
 // CHECK-NEXT: <callee_high>:
-// CHECK-NEXT:    1010:       70 47   bx      lr
+// CHECK-NEXT:    1018:       70 47   bx      lr
 // CHECK-EMPTY:
 // CHECK-NEXT: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:    1014:       ff f7 f6 ff     bl      0x1004 <callers>
-// CHECK-NEXT:    1018:       70 47   bx      lr
+// CHECK-NEXT:    101c:       ff f7 f2 ff     bl      0x1004 <callers>
+// CHECK-NEXT:    1020:       70 47   bx      lr

lld/test/ELF/arm-thumb-undefined-weak-narrow.test

 # REQUIRES: arm
 # RUN: yaml2obj %s -o %t.o
 # RUN: ld.lld %t.o -o %t
 # RUN: llvm-objdump -d %t | FileCheck %s
 
 # CHECK: Disassembly of section .text:
 # CHECK-EMPTY:
 # CHECK-NEXT: <_start>:
 # CHECK-NEXT:    ff e7   b       0x200b6 <_start+0x2> @ imm = #-2
+# CHECK-NEXT:    fe d0   beq     0x200b6 <_start+0x2> @ imm = #-4
 
-# Test the R_ARM_THM_JUMP11 relocation (102) to an undefined weak reference
-# It should resolve to the next instruction, which is an offset of -2 which
-# when added to the Thumb PC-bias of 4 is +2. We can't use llvm-mc to construct
-# the object as it relaxes b.n to b.w (R_ARM_JUMP24).
+# Test the R_ARM_THM_JUMP11 (102) and R_ARM_THM_JUMP8 (103) relocations to an
+# undefined weak reference.  It should resolve to the next instruction, which
+# is an offset of -2 which when added to the Thumb PC-bias of 4 is +2. We can't
+# use llvm-mc to construct the object as it relaxes b.n to b.w (R_ARM_JUMP24).
 
 !ELF
 FileHeader:
   Class:           ELFCLASS32
   Data:            ELFDATA2LSB
   Type:            ET_REL
   Machine:         EM_ARM
 Sections:
   - Type:            SHT_PROGBITS
     Name:            .text
     Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
-    Content:         "fee7"
+    Content:         "fee7fed0"
   - Type:            SHT_REL
     Name:            .rel.text
     Link:            .symtab
     Info:            .text
     Relocations:
       - Symbol:          undefined_weak
         Type:            R_ARM_THM_JUMP11
+      - Symbol:          undefined_weak
+        Type:            R_ARM_THM_JUMP8
 
 Symbols:
   - Type:             STT_NOTYPE
     Name:             "$t"
     Section:          .text
     Value:            0
   - Type:             STT_FUNC
     Name:             _start
     Value:            1
     Section:          .text
     Binding:          STB_GLOBAL
   - Type:             STT_NOTYPE
     Name:             undefined_weak
     Value:            0
     Binding:          STB_WEAK