[RISCV] Rewrite forwardCopyWillClobberTuple to not assume that there are exactly 32 registers. NFC

[craig.topper]

Summary

This function was copied from ARM where register pairs/triples/quads can wrap around the 32 encoding space. So register 31 can pair with register 0. This is not true for RISCV vectors. The spec specifically mentions the possibility of a future encoding that has more than 32 registers.

This patch removes the modulo from the code and directly checks that destination register is in the source register range and not the beginning of the range. Though I don't expect an identity copy will occur.

[frasercrmck]

LGTM. Are there any tests possible for this?

[craig.topper]

In D111467#3067184, @frasercrmck wrote:

LGTM. Are there any tests possible for this?

I don't think so. Since our register classes don't wrap around we should never see the wrap this was trying to handle. I think have tests for the different copy directions already though.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
     return MI.getOperand(0).getReg();
   }
 
   return 0;
 }
 
 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg,
                                         unsigned NumRegs) {
-  // We really want the positive remainder mod 32 here, that happens to be
-  // easily obtainable with a mask.
-  return ((DstReg - SrcReg) & 0x1f) < NumRegs;
+  return DstReg > SrcReg && (DstReg - SrcReg) < NumRegs;
 }
 
 void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  const DebugLoc &DL, MCRegister DstReg,
                                  MCRegister SrcReg, bool KillSrc) const {
   if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) {
     BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)