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Differential D111141

[RISCV] Optimize (add (mul r, c0), c1)
ClosedPublic

Authored by benshi001 on Oct 5 2021, 5:44 AM.

Details

Reviewers
luismarques
asb
craig.topper
jrtc27
Commits
rGe32cf690dfdc: [RISCV] Optimize (add (mul r, c0), c1)
Summary
Optimize (add (mul x, c0), c1) ->
         (add (mul (add x, c1/c0+1), c0), c1%c0-c0),
if c1/c0+1 and c1%c0-c0 are simm12, while c1 is not.

Optimize (add (mul x, c0), c1) ->
         (add (mul (add x, c1/c0-1), c0), c1%c0+c0),
if c1/c0-1 and c1%c0+c0 are simm12, while c1 is not.

Diff Detail

Event Timeline

benshi001 created this revision.Oct 5 2021, 5:44 AM
Herald added subscribers: achieveartificialintelligence, vkmr, frasercrmck and 22 others. · View Herald TranscriptOct 5 2021, 5:44 AM
benshi001 requested review of this revision.Oct 5 2021, 5:44 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 5 2021, 5:44 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
benshi001 updated this revision to Diff 377167.Oct 5 2021, 5:44 AM
benshi001 added a parent revision: D111140: [RISCV][test] Add more tests of (add (mul r, c0), c1).
Herald added a subscriber: hiraditya. · View Herald TranscriptOct 5 2021, 5:46 AM
benshi001 updated this revision to Diff 377222.Oct 5 2021, 7:01 AM
Harbormaster completed remote builds in B127055: Diff 377222.Oct 5 2021, 8:00 AM
benshi001 updated this revision to Diff 379580.Oct 13 2021, 6:55 PM
Harbormaster completed remote builds in B128762: Diff 379580.Oct 13 2021, 7:34 PM
benshi001 added inline comments.Oct 13 2021, 7:37 PM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
6451 ↗(On Diff #379580)

Repeated comments are removed.

asb added a comment.Nov 2 2021, 7:53 AM

I've suggested a slight tweak to the explanatory comments.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
6404 ↗(On Diff #379580)

"A special corner case that should be excluded is when ..., which will lead to an infinite loop in DAGCombine if transformed." would read more clearly (same for other instances below).

Herald added subscribers: VincentWu, luke957. · View Herald TranscriptNov 2 2021, 7:53 AM
benshi001 updated this revision to Diff 384298.Nov 2 2021, 6:37 PM
benshi001 marked an inline comment as done.
Harbormaster completed remote builds in B132119: Diff 384298.Nov 2 2021, 7:10 PM
asb accepted this revision.Nov 5 2021, 4:23 AM

I think this is correct. I'd certainly appreciate another pair of eyes confirming they agree though!

This revision is now accepted and ready to land.Nov 5 2021, 4:23 AM
benshi001 added a comment.Nov 7 2021, 5:54 PM

ping ... Can this patch be landed ?

craig.topper added a comment.Nov 7 2021, 6:05 PM

LGTM

craig.topper accepted this revision.Nov 7 2021, 6:05 PM
Closed by commit rGe32cf690dfdc: [RISCV] Optimize (add (mul r, c0), c1) (authored by benshi001). · Explain WhyNov 7 2021, 6:59 PM
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGe32cf690dfdc: [RISCV] Optimize (add (mul r, c0), c1).

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
324 lines

Diff 377166

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

Show First 20 Lines • Show All 562 Lines • ▼ Show 20 Lines
; RV64IMB-NEXT: lui a1, 1 ; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -2048 ; RV64IMB-NEXT: addiw a1, a1, -2048
; RV64IMB-NEXT: sh3add a0, a0, a1 ; RV64IMB-NEXT: sh3add a0, a0, a1
; RV64IMB-NEXT: ret ; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 24 %tmp0 = mul i64 %x, 24
%tmp1 = add i64 %tmp0, 2048 %tmp1 = add i64 %tmp0, 2048
ret i64 %tmp1 ret i64 %tmp1
} }
define i32 @mul3000_add8990_a(i32 %x) {
; RV32IMB-LABEL: mul3000_add8990_a:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1
; RV32IMB-NEXT: addi a1, a1, -1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 2
; RV32IMB-NEXT: addi a1, a1, 798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mul3000_add8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 2
; RV64IMB-NEXT: addiw a1, a1, 798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 3000
%tmp1 = add i32 %tmp0, 8990
ret i32 %tmp1
}
define signext i32 @mul3000_add8990_b(i32 signext %x) {
; RV32IMB-LABEL: mul3000_add8990_b:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1
; RV32IMB-NEXT: addi a1, a1, -1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 2
; RV32IMB-NEXT: addi a1, a1, 798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mul3000_add8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 2
; RV64IMB-NEXT: addiw a1, a1, 798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 3000
%tmp1 = add i32 %tmp0, 8990
ret i32 %tmp1
}
define i64 @mul3000_add8990_c(i64 %x) {
; RV32IMB-LABEL: mul3000_add8990_c:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a2, 1
; RV32IMB-NEXT: addi a2, a2, -1096
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 2
; RV32IMB-NEXT: addi a0, a0, 798
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mul3000_add8990_c:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 2
; RV64IMB-NEXT: addiw a1, a1, 798
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 3000
%tmp1 = add i64 %tmp0, 8990
ret i64 %tmp1
}
define i32 @mul3000_sub8990_a(i32 %x) {
; RV32IMB-LABEL: mul3000_sub8990_a:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1
; RV32IMB-NEXT: addi a1, a1, -1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 1048574
; RV32IMB-NEXT: addi a1, a1, -798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mul3000_sub8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 1048574
; RV64IMB-NEXT: addiw a1, a1, -798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 3000
%tmp1 = add i32 %tmp0, -8990
ret i32 %tmp1
}
define signext i32 @mul3000_sub8990_b(i32 signext %x) {
; RV32IMB-LABEL: mul3000_sub8990_b:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1
; RV32IMB-NEXT: addi a1, a1, -1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 1048574
; RV32IMB-NEXT: addi a1, a1, -798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mul3000_sub8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 1048574
; RV64IMB-NEXT: addiw a1, a1, -798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, 3000
%tmp1 = add i32 %tmp0, -8990
ret i32 %tmp1
}
define i64 @mul3000_sub8990_c(i64 %x) {
; RV32IMB-LABEL: mul3000_sub8990_c:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a2, 1
; RV32IMB-NEXT: addi a2, a2, -1096
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 1048574
; RV32IMB-NEXT: addi a0, a0, -798
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: addi a1, a1, -1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mul3000_sub8990_c:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1
; RV64IMB-NEXT: addiw a1, a1, -1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 1048574
; RV64IMB-NEXT: addiw a1, a1, -798
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, 3000
%tmp1 = add i64 %tmp0, -8990
ret i64 %tmp1
}
define i32 @mulneg3000_add8990_a(i32 %x) {
; RV32IMB-LABEL: mulneg3000_add8990_a:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1048575
; RV32IMB-NEXT: addi a1, a1, 1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 2
; RV32IMB-NEXT: addi a1, a1, 798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mulneg3000_add8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 2
; RV64IMB-NEXT: addiw a1, a1, 798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, -3000
%tmp1 = add i32 %tmp0, 8990
ret i32 %tmp1
}
define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
; RV32IMB-LABEL: mulneg3000_add8990_b:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1048575
; RV32IMB-NEXT: addi a1, a1, 1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 2
; RV32IMB-NEXT: addi a1, a1, 798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mulneg3000_add8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 2
; RV64IMB-NEXT: addiw a1, a1, 798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, -3000
%tmp1 = add i32 %tmp0, 8990
ret i32 %tmp1
}
define i64 @mulneg3000_add8990_c(i64 %x) {
; RV32IMB-LABEL: mulneg3000_add8990_c:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a2, 1048575
; RV32IMB-NEXT: addi a2, a2, 1096
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: sub a3, a3, a0
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 2
; RV32IMB-NEXT: addi a0, a0, 798
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mulneg3000_add8990_c:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 2
; RV64IMB-NEXT: addiw a1, a1, 798
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, -3000
%tmp1 = add i64 %tmp0, 8990
ret i64 %tmp1
}
define i32 @mulneg3000_sub8990_a(i32 %x) {
; RV32IMB-LABEL: mulneg3000_sub8990_a:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1048575
; RV32IMB-NEXT: addi a1, a1, 1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 1048574
; RV32IMB-NEXT: addi a1, a1, -798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mulneg3000_sub8990_a:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 1048574
; RV64IMB-NEXT: addiw a1, a1, -798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, -3000
%tmp1 = add i32 %tmp0, -8990
ret i32 %tmp1
}
define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
; RV32IMB-LABEL: mulneg3000_sub8990_b:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a1, 1048575
; RV32IMB-NEXT: addi a1, a1, 1096
; RV32IMB-NEXT: mul a0, a0, a1
; RV32IMB-NEXT: lui a1, 1048574
; RV32IMB-NEXT: addi a1, a1, -798
; RV32IMB-NEXT: add a0, a0, a1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mulneg3000_sub8990_b:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: mulw a0, a0, a1
; RV64IMB-NEXT: lui a1, 1048574
; RV64IMB-NEXT: addiw a1, a1, -798
; RV64IMB-NEXT: addw a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i32 %x, -3000
%tmp1 = add i32 %tmp0, -8990
ret i32 %tmp1
}
define i64 @mulneg3000_sub8990_c(i64 %x) {
; RV32IMB-LABEL: mulneg3000_sub8990_c:
; RV32IMB: # %bb.0:
; RV32IMB-NEXT: lui a2, 1048575
; RV32IMB-NEXT: addi a2, a2, 1096
; RV32IMB-NEXT: mul a1, a1, a2
; RV32IMB-NEXT: mulhu a3, a0, a2
; RV32IMB-NEXT: sub a3, a3, a0
; RV32IMB-NEXT: add a1, a3, a1
; RV32IMB-NEXT: mul a2, a0, a2
; RV32IMB-NEXT: lui a0, 1048574
; RV32IMB-NEXT: addi a0, a0, -798
; RV32IMB-NEXT: add a0, a2, a0
; RV32IMB-NEXT: sltu a2, a0, a2
; RV32IMB-NEXT: add a1, a1, a2
; RV32IMB-NEXT: addi a1, a1, -1
; RV32IMB-NEXT: ret
;
; RV64IMB-LABEL: mulneg3000_sub8990_c:
; RV64IMB: # %bb.0:
; RV64IMB-NEXT: lui a1, 1048575
; RV64IMB-NEXT: addiw a1, a1, 1096
; RV64IMB-NEXT: mul a0, a0, a1
; RV64IMB-NEXT: lui a1, 1048574
; RV64IMB-NEXT: addiw a1, a1, -798
; RV64IMB-NEXT: add a0, a0, a1
; RV64IMB-NEXT: ret
%tmp0 = mul i64 %x, -3000
%tmp1 = add i64 %tmp0, -8990
ret i64 %tmp1
}