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Differential D110675

[RISCV][test] Precommit tests for D108129.
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Authored by jacquesguan on Sep 28 2021, 7:07 PM.

Details

Reviewers
frasercrmck
craig.topper
RKSimon
Commits
rGa9a895207f85: [RISCV][test] Precommit tests for D108129.
Summary

Pre-commit tests for D108129.

Diff Detail

Unit TestsFailed

TimeTest
2,960 msx64 debian > libFuzzer.libFuzzer::fuzzer-finalstats.test

Event Timeline

jacquesguan created this revision.Sep 28 2021, 7:07 PM
Herald added subscribers: achieveartificialintelligence, vkmr, evandro and 24 others. · View Herald TranscriptSep 28 2021, 7:07 PM
jacquesguan requested review of this revision.Sep 28 2021, 7:07 PM
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jacquesguan mentioned this in D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector..Sep 28 2021, 7:09 PM
Harbormaster completed remote builds in B126231: Diff 375764.Sep 28 2021, 7:28 PM
RKSimon added inline comments.Sep 29 2021, 1:56 AM
llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode-rv32.ll
306 ↗(On Diff #375764)

you can probably get rid of cfi noise bv adding a nounwind attribute?

frasercrmck added a comment.Oct 21 2021, 1:42 AM

Is there a reason we're only testing on RV32?

jacquesguan updated this revision to Diff 382934.Oct 28 2021, 12:23 AM

Add rv64 tests.

Harbormaster completed remote builds in B131137: Diff 382934.Oct 28 2021, 1:02 AM
RKSimon accepted this revision.Oct 28 2021, 1:26 AM

LGTM

This revision is now accepted and ready to land.Oct 28 2021, 1:26 AM
frasercrmck requested changes to this revision.Oct 28 2021, 2:11 AM

LGTM if that issue is fixed.

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
40

Missing checks here and in other functions. Unless the file wasn't generated correctly, this is probably because the codegen differs between RV32 and RV64. You likely need --check-prefixes=RV32,CHECK and --check-prefixes=RV64,CHECK

This revision now requires changes to proceed.Oct 28 2021, 2:11 AM
RKSimon added a comment.Oct 28 2021, 3:56 AM

Nice catch!

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
4

As per @frasercrmck request:

; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
jacquesguan updated this revision to Diff 383226.Oct 28 2021, 8:19 PM

Add check prefix for difference between RV32 and RV64.

Herald added a subscriber: VincentWu. · View Herald TranscriptOct 28 2021, 8:19 PM
jacquesguan added a comment.Oct 28 2021, 8:20 PM
In D110675#3092751, @frasercrmck wrote:

LGTM if that issue is fixed.

Done, thanks a lot.

jacquesguan added inline comments.Oct 28 2021, 8:24 PM
llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
4

Done, thanks a lot.

Harbormaster completed remote builds in B131343: Diff 383226.Oct 28 2021, 8:58 PM
Herald added a subscriber: luke957. · View Herald TranscriptOct 28 2021, 8:58 PM
frasercrmck accepted this revision.Oct 29 2021, 3:35 AM

Thanks!

This revision is now accepted and ready to land.Oct 29 2021, 3:35 AM
This revision was landed with ongoing or failed builds.Nov 1 2021, 7:38 PM
Closed by commit rGa9a895207f85: [RISCV][test] Precommit tests for D108129. (authored by jacquesguan, committed by benshi001). · Explain Why
This revision was automatically updated to reflect the committed changes.
benshi001 added a commit: rGa9a895207f85: [RISCV][test] Precommit tests for D108129..

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
324 lines
411 lines

Diff 383226

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll

Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0 %head_six = insertelement <vscale x 4 x i8> undef, i8 6, i32 0
%splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer %splat_six = shufflevector <vscale x 4 x i8> %head_six, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
%rem = srem <vscale x 4 x i8> %va, %splat_six %rem = srem <vscale x 4 x i8> %va, %splat_six
%cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
ret <vscale x 4 x i1> %cc ret <vscale x 4 x i1> %cc
} }
define <vscale x 1 x i32> @vmulh_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmulh_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmulh.vv v8, v9, v8
; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = mul <vscale x 1 x i64> %vc, %vd
%head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%vf = lshr <vscale x 1 x i64> %ve, %splat
%vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vg
}
define <vscale x 1 x i32> @vmulh_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulh_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = mul <vscale x 1 x i64> %vb, %vc
%head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%ve = lshr <vscale x 1 x i64> %vd, %splat2
%vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vf
}
define <vscale x 1 x i32> @vmulh_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv1i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: addi a0, zero, -7
; CHECK-NEXT: vmul.vx v8, v9, a0
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = mul <vscale x 1 x i64> %vb, %vc
%head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%ve = lshr <vscale x 1 x i64> %vd, %splat2
%vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vf
}
define <vscale x 1 x i32> @vmulh_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv1i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vsext.vf2 v9, v8
; CHECK-NEXT: vsll.vi v8, v9, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
%vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = mul <vscale x 1 x i64> %vb, %vc
%head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%ve = lshr <vscale x 1 x i64> %vd, %splat2
%vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vf
}
define <vscale x 2 x i32> @vmulh_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmulh_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vmulh.vv v8, v9, v8
; CHECK-NEXT: ret
%vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = mul <vscale x 2 x i64> %vc, %vd
%head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%vf = lshr <vscale x 2 x i64> %ve, %splat
%vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vg
}
define <vscale x 2 x i32> @vmulh_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulh_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = mul <vscale x 2 x i64> %vb, %vc
%head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%ve = lshr <vscale x 2 x i64> %vd, %splat2
%vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vf
}
define <vscale x 2 x i32> @vmulh_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv2i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: addi a0, zero, -7
; CHECK-NEXT: vmul.vx v8, v10, a0
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = mul <vscale x 2 x i64> %vb, %vc
%head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%ve = lshr <vscale x 2 x i64> %vd, %splat2
%vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vf
}
define <vscale x 2 x i32> @vmulh_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv2i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vsext.vf2 v10, v8
; CHECK-NEXT: vsll.vi v8, v10, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
%vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = mul <vscale x 2 x i64> %vb, %vc
%head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%ve = lshr <vscale x 2 x i64> %vd, %splat2
%vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vf
}
define <vscale x 4 x i32> @vmulh_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmulh_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulh.vv v8, v10, v8
; CHECK-NEXT: ret
%vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = mul <vscale x 4 x i64> %vc, %vd
%head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%vf = lshr <vscale x 4 x i64> %ve, %splat
%vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vg
}
define <vscale x 4 x i32> @vmulh_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulh_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = mul <vscale x 4 x i64> %vb, %vc
%head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%ve = lshr <vscale x 4 x i64> %vd, %splat2
%vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vf
}
define <vscale x 4 x i32> @vmulh_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv4i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: addi a0, zero, -7
; CHECK-NEXT: vmul.vx v8, v12, a0
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v12, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = mul <vscale x 4 x i64> %vb, %vc
%head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%ve = lshr <vscale x 4 x i64> %vd, %splat2
%vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vf
}
define <vscale x 4 x i32> @vmulh_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv4i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vsext.vf2 v12, v8
; CHECK-NEXT: vsll.vi v8, v12, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v12, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
%vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = mul <vscale x 4 x i64> %vb, %vc
%head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%ve = lshr <vscale x 4 x i64> %vd, %splat2
%vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vf
}
define <vscale x 8 x i32> @vmulh_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmulh_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmulh.vv v8, v12, v8
; CHECK-NEXT: ret
%vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = mul <vscale x 8 x i64> %vc, %vd
%head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vf = lshr <vscale x 8 x i64> %ve, %splat
%vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vg
}
define <vscale x 8 x i32> @vmulh_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulh_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vmulh.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = mul <vscale x 8 x i64> %vb, %vc
%head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%ve = lshr <vscale x 8 x i64> %vd, %splat2
%vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vf
}
define <vscale x 8 x i32> @vmulh_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv8i32_0:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: addi a0, zero, -7
; CHECK-NEXT: vmul.vx v8, v16, a0
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = mul <vscale x 8 x i64> %vb, %vc
%head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%ve = lshr <vscale x 8 x i64> %vd, %splat2
%vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vf
}
define <vscale x 8 x i32> @vmulh_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmulh_vi_nxv8i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vsll.vi v8, v16, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
%vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = mul <vscale x 8 x i64> %vb, %vc
%head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%ve = lshr <vscale x 8 x i64> %vd, %splat2
%vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vf
}

llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
RKSimonUnsubmitted
Not Done
ReplyInline Actions

As per @frasercrmck request:

; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
RKSimon: As per @frasercrmck request: ``` ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify…
jacquesguanAuthorUnsubmitted
Done
ReplyInline Actions

Done, thanks a lot.

jacquesguan: Done, thanks a lot.
define <vscale x 1 x i32> @vmulhu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vmulhu_vv_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmulhu.vv v8, v9, v8
; CHECK-NEXT: ret
%vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%ve = mul <vscale x 1 x i64> %vc, %vd
%head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%vf = lshr <vscale x 1 x i64> %ve, %splat
%vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vg
}
define <vscale x 1 x i32> @vmulhu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulhu_vx_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = mul <vscale x 1 x i64> %vb, %vc
%head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%ve = lshr <vscale x 1 x i64> %vd, %splat2
%vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vf
}
define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
; RV32-LABEL: vmulhu_vi_nxv1i32_0:
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

Missing checks here and in other functions. Unless the file wasn't generated correctly, this is probably because the codegen differs between RV32 and RV64. You likely need --check-prefixes=RV32,CHECK and --check-prefixes=RV64,CHECK

frasercrmck: Missing checks here and in other functions. Unless the file wasn't generated correctly, this is…
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: addi a0, zero, -7
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vzext.vf2 v10, v8
; RV32-NEXT: vmul.vv v8, v10, v9
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsrl.vx v8, v8, a0
; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vmulhu_vi_nxv1i32_0:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; RV64-NEXT: vzext.vf2 v9, v8
; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: addi a0, a0, -7
; RV64-NEXT: vmul.vx v8, v9, a0
; RV64-NEXT: addi a0, zero, 32
; RV64-NEXT: vsrl.vx v8, v8, a0
; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v8, 0
; RV64-NEXT: ret
%head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = mul <vscale x 1 x i64> %vb, %vc
%head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%ve = lshr <vscale x 1 x i64> %vd, %splat2
%vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vf
}
define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vmulhu_vi_nxv1i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vzext.vf2 v9, v8
; CHECK-NEXT: vsll.vi v8, v9, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
%vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
%vd = mul <vscale x 1 x i64> %vb, %vc
%head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
%ve = lshr <vscale x 1 x i64> %vd, %splat2
%vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
ret <vscale x 1 x i32> %vf
}
define <vscale x 2 x i32> @vmulhu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
; CHECK-LABEL: vmulhu_vv_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vmulhu.vv v8, v9, v8
; CHECK-NEXT: ret
%vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
%vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%ve = mul <vscale x 2 x i64> %vc, %vd
%head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%vf = lshr <vscale x 2 x i64> %ve, %splat
%vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vg
}
define <vscale x 2 x i32> @vmulhu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulhu_vx_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = mul <vscale x 2 x i64> %vb, %vc
%head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%ve = lshr <vscale x 2 x i64> %vd, %splat2
%vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vf
}
define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
; RV32-LABEL: vmulhu_vi_nxv2i32_0:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: addi a0, zero, -7
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vzext.vf2 v12, v8
; RV32-NEXT: vmul.vv v8, v12, v10
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV32-NEXT: vnsrl.wi v8, v10, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vmulhu_vi_nxv2i32_0:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; RV64-NEXT: vzext.vf2 v10, v8
; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: addi a0, a0, -7
; RV64-NEXT: vmul.vx v8, v10, a0
; RV64-NEXT: addi a0, zero, 32
; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; RV64-NEXT: vnsrl.wi v8, v10, 0
; RV64-NEXT: ret
%head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = mul <vscale x 2 x i64> %vb, %vc
%head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%ve = lshr <vscale x 2 x i64> %vd, %splat2
%vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vf
}
define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vmulhu_vi_nxv2i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vsll.vi v8, v10, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
%vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
%vd = mul <vscale x 2 x i64> %vb, %vc
%head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
%ve = lshr <vscale x 2 x i64> %vd, %splat2
%vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
ret <vscale x 2 x i32> %vf
}
define <vscale x 4 x i32> @vmulhu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
; CHECK-LABEL: vmulhu_vv_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulhu.vv v8, v10, v8
; CHECK-NEXT: ret
%vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
%vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%ve = mul <vscale x 4 x i64> %vc, %vd
%head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%vf = lshr <vscale x 4 x i64> %ve, %splat
%vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vg
}
define <vscale x 4 x i32> @vmulhu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulhu_vx_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = mul <vscale x 4 x i64> %vb, %vc
%head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%ve = lshr <vscale x 4 x i64> %vd, %splat2
%vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vf
}
define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
; RV32-LABEL: vmulhu_vi_nxv4i32_0:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: addi a0, zero, -7
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v12, (a0), zero
; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: vmul.vv v8, v16, v12
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV32-NEXT: vnsrl.wi v8, v12, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vmulhu_vi_nxv4i32_0:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; RV64-NEXT: vzext.vf2 v12, v8
; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: addi a0, a0, -7
; RV64-NEXT: vmul.vx v8, v12, a0
; RV64-NEXT: addi a0, zero, 32
; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; RV64-NEXT: vnsrl.wi v8, v12, 0
; RV64-NEXT: ret
%head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = mul <vscale x 4 x i64> %vb, %vc
%head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%ve = lshr <vscale x 4 x i64> %vd, %splat2
%vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vf
}
define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vmulhu_vi_nxv4i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vzext.vf2 v12, v8
; CHECK-NEXT: vsll.vi v8, v12, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v12, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
%vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
%vd = mul <vscale x 4 x i64> %vb, %vc
%head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
%ve = lshr <vscale x 4 x i64> %vd, %splat2
%vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
ret <vscale x 4 x i32> %vf
}
define <vscale x 8 x i32> @vmulhu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
; CHECK-LABEL: vmulhu_vv_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmulhu.vv v8, v12, v8
; CHECK-NEXT: ret
%vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
%vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%ve = mul <vscale x 8 x i64> %vc, %vd
%head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vf = lshr <vscale x 8 x i64> %ve, %splat
%vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vg
}
define <vscale x 8 x i32> @vmulhu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
; CHECK-LABEL: vmulhu_vx_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
; CHECK-NEXT: vmulhu.vx v8, v8, a0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
%splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = mul <vscale x 8 x i64> %vb, %vc
%head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%ve = lshr <vscale x 8 x i64> %vd, %splat2
%vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vf
}
define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
; RV32-LABEL: vmulhu_vi_nxv8i32_0:
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: addi a0, zero, -7
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vzext.vf2 v24, v8
; RV32-NEXT: vmul.vv v8, v24, v16
; RV32-NEXT: addi a0, zero, 32
; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV32-NEXT: vnsrl.wi v8, v16, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vmulhu_vi_nxv8i32_0:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; RV64-NEXT: vzext.vf2 v16, v8
; RV64-NEXT: addi a0, zero, 1
; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: addi a0, a0, -7
; RV64-NEXT: vmul.vx v8, v16, a0
; RV64-NEXT: addi a0, zero, 32
; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; RV64-NEXT: vnsrl.wi v8, v16, 0
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
%splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = mul <vscale x 8 x i64> %vb, %vc
%head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%ve = lshr <vscale x 8 x i64> %vd, %splat2
%vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vf
}
define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vmulhu_vi_nxv8i32_1:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vsll.vi v8, v16, 4
; CHECK-NEXT: addi a0, zero, 32
; CHECK-NEXT: vsrl.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
%vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
%vd = mul <vscale x 8 x i64> %vb, %vc
%head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
%splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%ve = lshr <vscale x 8 x i64> %vd, %splat2
%vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
ret <vscale x 8 x i32> %vf
}