[AArch64][SVE] Remove redundant PTEST following PNEXT/PFIRST

[peterwaller-arm]

Summary

PNEXT and PFIRST set the NZCV flags, so the subsequent PTEST can be
optimized away in AArch64InstrInfo::optimizePTestInstr.

See-also: https://reviews.llvm.org/D93292

[sdesmalen]

llvm/test/CodeGen/AArch64/sve-ptest-removal-pfirst.mir

3 ↗

(On Diff #373927)

Do these tests necessarily need to be MIR tests? The reason I ask is because I generally find them more difficult to read and would have thought some LLVM IR intrinsics would have been sufficient to prove an extra ptest is not added.

[peterwaller-arm]

llvm/test/CodeGen/AArch64/sve-ptest-removal-pfirst.mir

3 ↗

(On Diff #373927)

Good question. These tests reuse the same form as the other tests for this. But I agree an IR test would be seem straightforward. I'll wait for anyone else to chime in with reasoning and if I don't hear anything I'll switch it on Monday next week. I have an open question in my mind of whether the other tests (llvm/test/CodeGen/AArch64/sve-ptest-removal-*.mir) should be migrated to IR tests too, as a separate commit.

[paulwalker-arm]

llvm/test/CodeGen/AArch64/sve-ptest-removal-pfirst.mir

3 ↗

(On Diff #373927)

My view is MIR tests are better at ensuring a specific piece of code within the code generator is exercised, which is a good fit for ensuring isPTestLike works as expected.

That said, this patch is only decorating more instructions with an existing property and so there isn't really any new functionality to exercise. For that reason I see no problem with using an LLVM IR test to validate the newly decorated instructions but please don't convert all the existing MIR tests.

Perhaps just one of the sve-ptest-removal-while##.mir tests is sufficient and the others can be converted to LLVM IR tests. Given the tests already exist I'm not sure what value there is in rewriting them, but that's your call.

[peterwaller-arm]

• Switch mir tests to a single ll test file, per review comments.

[peterwaller-arm]

• Remove bogus _neg tests, they were taken from the brk tests where they were applicable because there were non-flag-setting variants.
• Rename test file to pfirst-pnext since the one file tests both.

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs pprty:$Pdn), (ins PPRAny:$Pg, pprty:$_Pdn),
   let Inst{15-11} = 0b11000;
   let Inst{10-9}  = opc{1-0};
   let Inst{8-5}   = Pg;
   let Inst{4}     = 0;
   let Inst{3-0}   = Pdn;
 
   let Constraints = "$Pdn = $_Pdn";
   let Defs = [NZCV];
+  let isPTestLike = 1;
+  let ElementSize = pprty.ElementSize;
 }
 
 multiclass sve_int_pfirst<bits<5> opc, string asm, SDPatternOperator op> {
   def _B : sve_int_pfirst_next<0b01, opc, asm, PPR8>;
 
   def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>;
 }
 

llvm/test/CodeGen/AArch64/sve-ptest-removal-pnext.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
+
+define i32 @pfirst_16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: pfirst_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    pfirst p1.b, p0, p1.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pfirst_neg_16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: pfirst_neg_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov p2.b, p1.b
+; CHECK-NEXT:    pfirst p2.b, p0, p2.b
+; CHECK-NEXT:    ptest p1, p2.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: pnext_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    pnext p1.b, p0, p1.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_neg_16(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
+; CHECK-LABEL: pnext_neg_16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov p2.b, p1.b
+; CHECK-NEXT:    pnext p2.b, p0, p2.b
+; CHECK-NEXT:    ptest p1, p2.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_8(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
+; CHECK-LABEL: pnext_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    pnext p1.h, p0, p1.h
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_neg_8(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
+; CHECK-LABEL: pnext_neg_8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov p2.b, p1.b
+; CHECK-NEXT:    pnext p2.h, p0, p2.h
+; CHECK-NEXT:    ptest p1, p2.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_4(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
+; CHECK-LABEL: pnext_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    pnext p1.s, p0, p1.s
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_neg_4(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
+; CHECK-LABEL: pnext_neg_4:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov p2.b, p1.b
+; CHECK-NEXT:    pnext p2.s, p0, p2.s
+; CHECK-NEXT:    ptest p1, p2.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_2(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
+; CHECK-LABEL: pnext_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    pnext p1.d, p0, p1.d
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+define i32 @pnext_neg_2(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
+; CHECK-LABEL: pnext_neg_2:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov p2.b, p1.b
+; CHECK-NEXT:    pnext p2.d, p0, p2.d
+; CHECK-NEXT:    ptest p1, p2.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %1 = tail call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a)
+  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %1)
+  %conv = zext i1 %2 to i32
+  ret i32 %conv
+}
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+
+declare <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
+declare <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
+declare <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)
+
+declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
+declare i1 @llvm.aarch64.sve.ptest.any.nxv8i1(<vscale x 8 x i1>, <vscale x 8 x i1>)
+declare i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
+declare i1 @llvm.aarch64.sve.ptest.any.nxv2i1(<vscale x 2 x i1>, <vscale x 2 x i1>)