[AArch64][SVE] Add API for conversion between SVE predicate pattern and element count. NFC

[junparser]

Summary

This patch solely moves convert operation between SVE predicate pattern
and element count into two small functions. It's pre-commit patch for optimize
pture with known sve register width.

[david-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

18027

You're removing the unreachable here. Perhaps it's worth adding an assert:

assert(PgPattern && "Unexpected element count for SVE predicate")

18058

Maybe we should leave this TODO here as I think it still applies?

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

457

I think that using both inline and static keywords here causes clang-tidy to think it's unused. Can you just use the inline keyword here instead?

457

I think this breaks case style rules - perhaps this should be named something like getNumElementsFromSVEPredPattern?

492

Same comments as above.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

18031

This'll need to be validated as with the original code.

18058–18060

I think this is an important comment that should remain within getPredicateForFixedLengthVector. See comment on D108706.

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

457

I'm not a fan of the names of these functions as ElementCount has an existing meaning within LLVM and these function are not really honouring it. Perhaps getSVEPredicatePatternAsFixedLength/getSVEPredicatePatternForFixedLength? Or something of similar ilk.

Can you add a function comment that makes it explicit that zero is returned for the case where no translation is possible.

470–471

Is there an LLVM coding style policy here? For example is setting MinNumElts and breaking preferred over just using return.

498–499

Same "return" comment as above.

[junparser]

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

470–471

I checked https://llvm.org/docs/CodingStandards.html, There is no rules for switch cases.

[junparser]

Address comment.

[david-arm]

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

470–471

OK, I guess that's fine, but returning without breaks maybe does look nicer and more compact (it kills off 8 lines of code)? It's also more consistent with the default case that does return early.

i.e.

switch (Pattern) {
default:
  return 0;
case AArch64SVEPredPattern::vl1:
...
  return Pattern;
...
}

I don't feel too strongly about it though. :)

[junparser]

Address comment.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

655

As a bit of extra tidying perhaps merge this MinNumElts > NumElts with the new if (!MinNumElts).

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

 
 // Return a PTRUE with active lanes corresponding to the extent of VT.
 static SDValue getPredicateForFixedLengthVector(SelectionDAG &DAG, SDLoc &DL,
                                                 EVT VT) {
   assert(VT.isFixedLengthVector() &&
          DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
          "Expected legal fixed length vector!");
 
-  int PgPattern;
-  switch (VT.getVectorNumElements()) {
-  default:
-    llvm_unreachable("unexpected element count for SVE predicate");
-  case 1:
-    PgPattern = AArch64SVEPredPattern::vl1;
-    break;
-  case 2:
-    PgPattern = AArch64SVEPredPattern::vl2;
-    break;
-  case 4:
-    PgPattern = AArch64SVEPredPattern::vl4;
-    break;
-  case 8:
-    PgPattern = AArch64SVEPredPattern::vl8;
-    break;
-  case 16:
-    PgPattern = AArch64SVEPredPattern::vl16;
-    break;
-  case 32:
-    PgPattern = AArch64SVEPredPattern::vl32;
-    break;
-  case 64:
-    PgPattern = AArch64SVEPredPattern::vl64;
-    break;
-  case 128:
-    PgPattern = AArch64SVEPredPattern::vl128;
-    break;
-  case 256:
-    PgPattern = AArch64SVEPredPattern::vl256;
-    break;
-  }
+  unsigned PgPattern =
+      getSVEPredPatternFromNumElements(VT.getVectorNumElements());
+  assert(PgPattern && "Unexpected element count for SVE predicate");
 
   // TODO: For vectors that are exactly getMaxSVEVectorSizeInBits big, we can
   // use AArch64SVEPredPattern::all, which can enable the use of unpredicated
   // variants of instructions when available.
 
   MVT MaskVT;
   switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
   default:
     llvm_unreachable("unexpected element type for SVE predicate");
   case MVT::i8:
     MaskVT = MVT::nxv16i1;
     break;

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

static Optional<Instruction *> instCombineSVELast(InstCombiner &IC,
 
   if (IntrPG->getIntrinsicID() != Intrinsic::aarch64_sve_ptrue)
     return None;
 
   const auto PTruePattern =
       cast<ConstantInt>(IntrPG->getOperand(0))->getZExtValue();
 
   // Can the intrinsic's predicate be converted to a known constant index?
-  unsigned Idx;
-  switch (PTruePattern) {
-  default:
+  unsigned MinNumElts = getNumElementsFromSVEPredPattern(PTruePattern);
+  if (!MinNumElts)
     return None;
-  case AArch64SVEPredPattern::vl1:
-    Idx = 0;
-    break;
-  case AArch64SVEPredPattern::vl2:
-    Idx = 1;
-    break;
-  case AArch64SVEPredPattern::vl3:
-    Idx = 2;
-    break;
-  case AArch64SVEPredPattern::vl4:
-    Idx = 3;
-    break;
-  case AArch64SVEPredPattern::vl5:
-    Idx = 4;
-    break;
-  case AArch64SVEPredPattern::vl6:
-    Idx = 5;
-    break;
-  case AArch64SVEPredPattern::vl7:
-    Idx = 6;
-    break;
-  case AArch64SVEPredPattern::vl8:
-    Idx = 7;
-    break;
-  case AArch64SVEPredPattern::vl16:
-    Idx = 15;
-    break;
-  }
 
+  unsigned Idx = MinNumElts - 1;
   // Increment the index if extracting the element after the last active
   // predicate element.
   if (IsAfter)
     ++Idx;
 
   // Ignore extracts whose index is larger than the known minimum vector
   // length. NOTE: This is an artificial constraint where we prefer to
   // maintain what the user asked for until an alternative is proven faster.
if (Pattern == AArch64SVEPredPattern::all) {
     Builder.SetInsertPoint(&II);
 
     Constant *StepVal = ConstantInt::get(II.getType(), NumElts);
     auto *VScale = Builder.CreateVScale(StepVal);
     VScale->takeName(&II);
     return IC.replaceInstUsesWith(II, VScale);
   }
 
-  unsigned MinNumElts = 0;
-  switch (Pattern) {
-  default:
-    return None;
-  case AArch64SVEPredPattern::vl1:
-  case AArch64SVEPredPattern::vl2:
-  case AArch64SVEPredPattern::vl3:
-  case AArch64SVEPredPattern::vl4:
-  case AArch64SVEPredPattern::vl5:
-  case AArch64SVEPredPattern::vl6:
-  case AArch64SVEPredPattern::vl7:
-  case AArch64SVEPredPattern::vl8:
-    MinNumElts = Pattern;
-    break;
-  case AArch64SVEPredPattern::vl16:
-    MinNumElts = 16;
-    break;
-  }
+  unsigned MinNumElts = getNumElementsFromSVEPredPattern(Pattern);
 
-  return NumElts >= MinNumElts
+  return MinNumElts && NumElts >= MinNumElts
              ? Optional<Instruction *>(IC.replaceInstUsesWith(
                    II, ConstantInt::get(II.getType(), MinNumElts)))
              : None;
 }
 
 static Optional<Instruction *> instCombineSVEPTest(InstCombiner &IC,
                                                    IntrinsicInst &II) {
   IntrinsicInst *Op1 = dyn_cast<IntrinsicInst>(II.getArgOperand(0));

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

namespace AArch64SVEPredPattern {
   struct SVEPREDPAT {
     const char *Name;
     uint16_t Encoding;
   };
 #define GET_SVEPREDPAT_DECL
 #include "AArch64GenSystemOperands.inc"
 }
 
+/// Return the number of active elements for VL1 to VL256 predicate pattern,
+/// zero for all other patterns.
+inline unsigned getNumElementsFromSVEPredPattern(unsigned Pattern) {
+  switch (Pattern) {
+  default:
+    return 0;
+  case AArch64SVEPredPattern::vl1:
+  case AArch64SVEPredPattern::vl2:
+  case AArch64SVEPredPattern::vl3:
+  case AArch64SVEPredPattern::vl4:
+  case AArch64SVEPredPattern::vl5:
+  case AArch64SVEPredPattern::vl6:
+  case AArch64SVEPredPattern::vl7:
+  case AArch64SVEPredPattern::vl8:
+    return Pattern;
+  case AArch64SVEPredPattern::vl16:
+    return 16;
+  case AArch64SVEPredPattern::vl32:
+    return 32;
+  case AArch64SVEPredPattern::vl64:
+    return 64;
+  case AArch64SVEPredPattern::vl128:
+    return 128;
+  case AArch64SVEPredPattern::vl256:
+    return 256;
+  }
+}
+
+/// Return specific VL predicate pattern based on the number of elements.
+inline unsigned getSVEPredPatternFromNumElements(unsigned MinNumElts) {
+  switch (MinNumElts) {
+  default:
+    llvm_unreachable("unexpected element count for SVE predicate");
+  case 1:
+    return AArch64SVEPredPattern::vl1;
+  case 2:
+    return AArch64SVEPredPattern::vl2;
+  case 4:
+    return AArch64SVEPredPattern::vl4;
+  case 8:
+    return AArch64SVEPredPattern::vl8;
+  case 16:
+    return AArch64SVEPredPattern::vl16;
+  case 32:
+    return AArch64SVEPredPattern::vl32;
+  case 64:
+    return AArch64SVEPredPattern::vl64;
+  case 128:
+    return AArch64SVEPredPattern::vl128;
+  case 256:
+    return AArch64SVEPredPattern::vl256;
+  }
+}
+
 namespace AArch64ExactFPImm {
   struct ExactFPImm {
     const char *Name;
     int Enum;
     const char *Repr;
   };
 #define GET_EXACTFPIMM_DECL
 #include "AArch64GenSystemOperands.inc"